2 * Copyright 2021 Advanced Micro Devices, Inc.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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25 #include "athub_v3_0.h"
26 #include "athub/athub_3_0_0_offset.h"
27 #include "athub/athub_3_0_0_sh_mask.h"
28 #include "navi10_enum.h"
29 #include "soc15_common.h"
32 athub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
37 def = data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);
39 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_MGCG))
40 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
42 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
45 WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);
49 athub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
54 def = data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);
56 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_LS))
57 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
59 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
62 WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);
65 int athub_v3_0_set_clockgating(struct amdgpu_device *adev,
66 enum amd_clockgating_state state)
68 if (amdgpu_sriov_vf(adev))
71 switch (adev->ip_versions[ATHUB_HWIP][0]) {
72 case IP_VERSION(3, 0, 0):
73 case IP_VERSION(3, 0, 2):
74 athub_v3_0_update_medium_grain_clock_gating(adev,
75 state == AMD_CG_STATE_GATE);
76 athub_v3_0_update_medium_grain_light_sleep(adev,
77 state == AMD_CG_STATE_GATE);
86 void athub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
90 /* AMD_CG_SUPPORT_ATHUB_MGCG */
91 data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);
92 if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
93 *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
95 /* AMD_CG_SUPPORT_ATHUB_LS */
96 if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
97 *flags |= AMD_CG_SUPPORT_ATHUB_LS;