2 * Copyright 2022 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "soc15_common.h"
27 #include "amdgpu_xcp.h"
28 #include "gfx_v9_4_3.h"
29 #include "gfxhub_v1_2.h"
30 #include "sdma_v4_4_2.h"
32 #define XCP_INST_MASK(num_inst, xcp_id) \
33 (num_inst ? GENMASK(num_inst - 1, 0) << (xcp_id * num_inst) : 0)
35 #define AMDGPU_XCP_OPS_KFD (1 << 0)
37 void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev)
41 adev->doorbell_index.kiq = AMDGPU_DOORBELL_LAYOUT1_KIQ_START;
43 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_LAYOUT1_MEC_RING_START;
45 adev->doorbell_index.userqueue_start = AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_START;
46 adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL_LAYOUT1_USERQUEUE_END;
47 adev->doorbell_index.xcc_doorbell_range = AMDGPU_DOORBELL_LAYOUT1_XCC_RANGE;
49 adev->doorbell_index.sdma_doorbell_range = 20;
50 for (i = 0; i < adev->sdma.num_instances; i++)
51 adev->doorbell_index.sdma_engine[i] =
52 AMDGPU_DOORBELL_LAYOUT1_sDMA_ENGINE_START +
53 i * (adev->doorbell_index.sdma_doorbell_range >> 1);
55 adev->doorbell_index.ih = AMDGPU_DOORBELL_LAYOUT1_IH;
56 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_DOORBELL_LAYOUT1_VCN_START;
58 adev->doorbell_index.first_non_cp = AMDGPU_DOORBELL_LAYOUT1_FIRST_NON_CP;
59 adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL_LAYOUT1_LAST_NON_CP;
61 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT << 1;
64 static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev,
65 uint32_t inst_idx, struct amdgpu_ring *ring)
68 enum AMDGPU_XCP_IP_BLOCK ip_blk;
72 if (adev->xcp_mgr->mode == AMDGPU_XCP_MODE_NONE)
75 inst_mask = 1 << inst_idx;
77 switch (ring->funcs->type) {
78 case AMDGPU_HW_IP_GFX:
79 case AMDGPU_RING_TYPE_COMPUTE:
80 case AMDGPU_RING_TYPE_KIQ:
81 ip_blk = AMDGPU_XCP_GFX;
83 case AMDGPU_RING_TYPE_SDMA:
84 ip_blk = AMDGPU_XCP_SDMA;
86 case AMDGPU_RING_TYPE_VCN_ENC:
87 case AMDGPU_RING_TYPE_VCN_JPEG:
88 ip_blk = AMDGPU_XCP_VCN;
89 if (adev->xcp_mgr->mode == AMDGPU_CPX_PARTITION_MODE)
90 inst_mask = 1 << (inst_idx * 2);
93 DRM_ERROR("Not support ring type %d!", ring->funcs->type);
97 for (xcp_id = 0; xcp_id < adev->xcp_mgr->num_xcps; xcp_id++) {
98 if (adev->xcp_mgr->xcp[xcp_id].ip[ip_blk].inst_mask & inst_mask) {
99 ring->xcp_id = xcp_id;
105 static void aqua_vanjaram_xcp_gpu_sched_update(
106 struct amdgpu_device *adev,
107 struct amdgpu_ring *ring,
108 unsigned int sel_xcp_id)
110 unsigned int *num_gpu_sched;
112 num_gpu_sched = &adev->xcp_mgr->xcp[sel_xcp_id]
113 .gpu_sched[ring->funcs->type][ring->hw_prio].num_scheds;
114 adev->xcp_mgr->xcp[sel_xcp_id].gpu_sched[ring->funcs->type][ring->hw_prio]
115 .sched[(*num_gpu_sched)++] = &ring->sched;
116 DRM_DEBUG("%s :[%d] gpu_sched[%d][%d] = %d", ring->name,
117 sel_xcp_id, ring->funcs->type,
118 ring->hw_prio, *num_gpu_sched);
121 static int aqua_vanjaram_xcp_sched_list_update(
122 struct amdgpu_device *adev)
124 struct amdgpu_ring *ring;
127 for (i = 0; i < MAX_XCP; i++) {
128 atomic_set(&adev->xcp_mgr->xcp[i].ref_cnt, 0);
129 memset(adev->xcp_mgr->xcp[i].gpu_sched, 0, sizeof(adev->xcp_mgr->xcp->gpu_sched));
132 if (adev->xcp_mgr->mode == AMDGPU_XCP_MODE_NONE)
135 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
136 ring = adev->rings[i];
137 if (!ring || !ring->sched.ready)
140 aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id);
142 /* VCN is shared by two partitions under CPX MODE */
143 if ((ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||
144 ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) &&
145 adev->xcp_mgr->mode == AMDGPU_CPX_PARTITION_MODE)
146 aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id + 1);
152 static int aqua_vanjaram_update_partition_sched_list(struct amdgpu_device *adev)
156 for (i = 0; i < adev->num_rings; i++) {
157 struct amdgpu_ring *ring = adev->rings[i];
159 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ||
160 ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
161 aqua_vanjaram_set_xcp_id(adev, ring->xcc_id, ring);
163 aqua_vanjaram_set_xcp_id(adev, ring->me, ring);
166 return aqua_vanjaram_xcp_sched_list_update(adev);
169 int aqua_vanjaram_select_scheds(
170 struct amdgpu_device *adev,
173 struct amdgpu_fpriv *fpriv,
174 unsigned int *num_scheds,
175 struct drm_gpu_scheduler ***scheds)
180 if (fpriv->xcp_id == ~0) {
181 u32 least_ref_cnt = ~0;
184 for (i = 0; i < adev->xcp_mgr->num_xcps; i++) {
187 total_ref_cnt = atomic_read(&adev->xcp_mgr->xcp[i].ref_cnt);
188 if (total_ref_cnt < least_ref_cnt) {
190 least_ref_cnt = total_ref_cnt;
194 sel_xcp_id = fpriv->xcp_id;
196 if (adev->xcp_mgr->xcp[sel_xcp_id].gpu_sched[hw_ip][hw_prio].num_scheds) {
197 *num_scheds = adev->xcp_mgr->xcp[fpriv->xcp_id].gpu_sched[hw_ip][hw_prio].num_scheds;
198 *scheds = adev->xcp_mgr->xcp[fpriv->xcp_id].gpu_sched[hw_ip][hw_prio].sched;
199 atomic_inc(&adev->xcp_mgr->xcp[sel_xcp_id].ref_cnt);
200 DRM_DEBUG("Selected partition #%d", sel_xcp_id);
202 DRM_ERROR("Failed to schedule partition #%d.", sel_xcp_id);
209 static int8_t aqua_vanjaram_logical_to_dev_inst(struct amdgpu_device *adev,
210 enum amd_hw_ip_block_type block,
218 /* Both JPEG and VCN as JPEG is only alias of VCN */
220 dev_inst = adev->ip_map.dev_inst[block][inst];
223 /* For rest of the IPs, no look up required.
224 * Assume 'logical instance == physical instance' for all configs. */
232 static void aqua_vanjaram_populate_ip_map(struct amdgpu_device *adev,
233 enum amd_hw_ip_block_type ip_block,
239 i = ffs(inst_mask) - 1;
240 adev->ip_map.dev_inst[ip_block][l++] = i;
241 inst_mask &= ~(1 << i);
243 for (; l < HWIP_MAX_INSTANCE; l++)
244 adev->ip_map.dev_inst[ip_block][l] = -1;
247 void aqua_vanjaram_ip_map_init(struct amdgpu_device *adev)
250 { GC_HWIP, adev->gfx.xcc_mask },
251 { SDMA0_HWIP, adev->sdma.sdma_mask },
252 { VCN_HWIP, adev->vcn.inst_mask },
256 for (i = 0; i < ARRAY_SIZE(ip_map); ++i)
257 aqua_vanjaram_populate_ip_map(adev, ip_map[i][0], ip_map[i][1]);
259 adev->ip_map.logical_to_dev_inst = aqua_vanjaram_logical_to_dev_inst;
262 /* Fixed pattern for smn addressing on different AIDs:
263 * bit[34]: indicate cross AID access
264 * bit[33:32]: indicate target AID id
265 * AID id range is 0 ~ 3 as maximum AID number is 4.
267 u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id)
271 /* local routing and bit[34:32] will be zeros */
275 /* Initiated from host, accessing to all non-zero aids are cross traffic */
276 ext_offset = ((u64)(ext_id & 0x3) << 32) | (1ULL << 34);
281 static int aqua_vanjaram_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr)
283 enum amdgpu_gfx_partition mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE;
284 struct amdgpu_device *adev = xcp_mgr->adev;
286 if (adev->nbio.funcs->get_compute_partition_mode)
287 mode = adev->nbio.funcs->get_compute_partition_mode(adev);
292 int __aqua_vanjaram_get_xcc_per_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int mode)
294 int num_xcc, num_xcc_per_xcp = 0;
296 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask);
299 case AMDGPU_SPX_PARTITION_MODE:
300 num_xcc_per_xcp = num_xcc;
302 case AMDGPU_DPX_PARTITION_MODE:
303 num_xcc_per_xcp = num_xcc / 2;
305 case AMDGPU_TPX_PARTITION_MODE:
306 num_xcc_per_xcp = num_xcc / 3;
308 case AMDGPU_QPX_PARTITION_MODE:
309 num_xcc_per_xcp = num_xcc / 4;
311 case AMDGPU_CPX_PARTITION_MODE:
316 return num_xcc_per_xcp;
319 int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id,
320 enum AMDGPU_XCP_IP_BLOCK ip_id,
321 struct amdgpu_xcp_ip *ip)
323 struct amdgpu_device *adev = xcp_mgr->adev;
324 int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp;
325 int num_sdma, num_vcn;
327 num_sdma = adev->sdma.num_instances;
328 num_vcn = adev->vcn.num_vcn_inst;
330 switch (xcp_mgr->mode) {
331 case AMDGPU_SPX_PARTITION_MODE:
332 num_sdma_xcp = num_sdma;
333 num_vcn_xcp = num_vcn;
335 case AMDGPU_DPX_PARTITION_MODE:
336 num_sdma_xcp = num_sdma / 2;
337 num_vcn_xcp = num_vcn / 2;
339 case AMDGPU_TPX_PARTITION_MODE:
340 num_sdma_xcp = num_sdma / 3;
341 num_vcn_xcp = num_vcn / 3;
343 case AMDGPU_QPX_PARTITION_MODE:
344 num_sdma_xcp = num_sdma / 4;
345 num_vcn_xcp = num_vcn / 4;
347 case AMDGPU_CPX_PARTITION_MODE:
349 num_vcn_xcp = num_vcn ? 1 : 0;
355 num_xcc_xcp = adev->gfx.num_xcc_per_xcp;
358 case AMDGPU_XCP_GFXHUB:
359 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id);
360 ip->ip_funcs = &gfxhub_v1_2_xcp_funcs;
363 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id);
364 ip->ip_funcs = &gfx_v9_4_3_xcp_funcs;
366 case AMDGPU_XCP_SDMA:
367 ip->inst_mask = XCP_INST_MASK(num_sdma_xcp, xcp_id);
368 ip->ip_funcs = &sdma_v4_4_2_xcp_funcs;
371 ip->inst_mask = XCP_INST_MASK(num_vcn_xcp, xcp_id);
372 /* TODO : Assign IP funcs */
383 static enum amdgpu_gfx_partition
384 __aqua_vanjaram_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr)
386 struct amdgpu_device *adev = xcp_mgr->adev;
389 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask);
391 if (adev->gmc.num_mem_partitions == 1)
392 return AMDGPU_SPX_PARTITION_MODE;
394 if (adev->gmc.num_mem_partitions == num_xcc)
395 return AMDGPU_CPX_PARTITION_MODE;
397 if (adev->gmc.num_mem_partitions == num_xcc / 2)
398 return (adev->flags & AMD_IS_APU) ? AMDGPU_TPX_PARTITION_MODE :
399 AMDGPU_QPX_PARTITION_MODE;
401 if (adev->gmc.num_mem_partitions == 2 && !(adev->flags & AMD_IS_APU))
402 return AMDGPU_DPX_PARTITION_MODE;
404 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE;
407 static bool __aqua_vanjaram_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr,
408 enum amdgpu_gfx_partition mode)
410 struct amdgpu_device *adev = xcp_mgr->adev;
411 int num_xcc, num_xccs_per_xcp;
413 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
415 case AMDGPU_SPX_PARTITION_MODE:
416 return adev->gmc.num_mem_partitions == 1 && num_xcc > 0;
417 case AMDGPU_DPX_PARTITION_MODE:
418 return adev->gmc.num_mem_partitions != 8 && (num_xcc % 4) == 0;
419 case AMDGPU_TPX_PARTITION_MODE:
420 return (adev->gmc.num_mem_partitions == 1 ||
421 adev->gmc.num_mem_partitions == 3) &&
422 ((num_xcc % 3) == 0);
423 case AMDGPU_QPX_PARTITION_MODE:
424 num_xccs_per_xcp = num_xcc / 4;
425 return (adev->gmc.num_mem_partitions == 1 ||
426 adev->gmc.num_mem_partitions == 4) &&
427 (num_xccs_per_xcp >= 2);
428 case AMDGPU_CPX_PARTITION_MODE:
429 return ((num_xcc > 1) &&
430 (adev->gmc.num_mem_partitions == 1 || adev->gmc.num_mem_partitions == 4) &&
431 (num_xcc % adev->gmc.num_mem_partitions) == 0);
439 static int __aqua_vanjaram_pre_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags)
442 * Stop user queues and threads, and make sure GPU is empty of work.
445 if (flags & AMDGPU_XCP_OPS_KFD)
446 amdgpu_amdkfd_device_fini_sw(xcp_mgr->adev);
451 static int __aqua_vanjaram_post_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, u32 flags)
455 if (flags & AMDGPU_XCP_OPS_KFD) {
456 amdgpu_amdkfd_device_probe(xcp_mgr->adev);
457 amdgpu_amdkfd_device_init(xcp_mgr->adev);
458 /* If KFD init failed, return failure */
459 if (!xcp_mgr->adev->kfd.init_complete)
466 static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr,
467 int mode, int *num_xcps)
469 int num_xcc_per_xcp, num_xcc, ret;
470 struct amdgpu_device *adev;
473 adev = xcp_mgr->adev;
474 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
476 if (mode == AMDGPU_AUTO_COMPUTE_PARTITION_MODE) {
477 mode = __aqua_vanjaram_get_auto_mode(xcp_mgr);
478 } else if (!__aqua_vanjaram_is_valid_mode(xcp_mgr, mode)) {
480 "Invalid compute partition mode requested, requested: %s, available memory partitions: %d",
481 amdgpu_gfx_compute_mode_desc(mode), adev->gmc.num_mem_partitions);
485 if (adev->kfd.init_complete)
486 flags |= AMDGPU_XCP_OPS_KFD;
488 if (flags & AMDGPU_XCP_OPS_KFD) {
489 ret = amdgpu_amdkfd_check_and_lock_kfd(adev);
494 ret = __aqua_vanjaram_pre_partition_switch(xcp_mgr, flags);
498 num_xcc_per_xcp = __aqua_vanjaram_get_xcc_per_xcp(xcp_mgr, mode);
499 if (adev->gfx.funcs->switch_partition_mode)
500 adev->gfx.funcs->switch_partition_mode(xcp_mgr->adev,
503 if (adev->nbio.funcs->set_compute_partition_mode)
504 adev->nbio.funcs->set_compute_partition_mode(adev, mode);
506 /* Init info about new xcps */
507 *num_xcps = num_xcc / num_xcc_per_xcp;
508 amdgpu_xcp_init(xcp_mgr, *num_xcps, mode);
510 ret = __aqua_vanjaram_post_partition_switch(xcp_mgr, flags);
512 if (flags & AMDGPU_XCP_OPS_KFD)
513 amdgpu_amdkfd_unlock_kfd(adev);
518 static int __aqua_vanjaram_get_xcp_mem_id(struct amdgpu_device *adev,
519 int xcc_id, uint8_t *mem_id)
521 /* TODO: Check if any validation is required based on current
522 * memory/spatial modes
524 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp;
529 static int aqua_vanjaram_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr,
530 struct amdgpu_xcp *xcp, uint8_t *mem_id)
532 struct amdgpu_numa_info numa_info;
533 struct amdgpu_device *adev;
537 adev = xcp_mgr->adev;
538 /* TODO: BIOS is not returning the right info now
539 * Check on this later
542 if (adev->gmc.gmc_funcs->query_mem_partition_mode)
543 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
545 if (adev->gmc.num_mem_partitions == 1) {
551 r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask);
555 xcc_id = ffs(xcc_mask) - 1;
556 if (!adev->gmc.is_app_apu)
557 return __aqua_vanjaram_get_xcp_mem_id(adev, xcc_id, mem_id);
559 r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info);
565 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) {
566 if (adev->gmc.mem_partitions[i].numa.node == numa_info.nid) {
576 int aqua_vanjaram_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id,
577 enum AMDGPU_XCP_IP_BLOCK ip_id,
578 struct amdgpu_xcp_ip *ip)
583 return __aqua_vanjaram_get_xcp_ip_info(xcp_mgr, xcp_id, ip_id, ip);
586 struct amdgpu_xcp_mgr_funcs aqua_vanjaram_xcp_funcs = {
587 .switch_partition_mode = &aqua_vanjaram_switch_partition_mode,
588 .query_partition_mode = &aqua_vanjaram_query_partition_mode,
589 .get_ip_details = &aqua_vanjaram_get_xcp_ip_details,
590 .get_xcp_mem_id = &aqua_vanjaram_get_xcp_mem_id,
591 .select_scheds = &aqua_vanjaram_select_scheds,
592 .update_partition_sched_list = &aqua_vanjaram_update_partition_sched_list
595 static int aqua_vanjaram_xcp_mgr_init(struct amdgpu_device *adev)
599 ret = amdgpu_xcp_mgr_init(adev, AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE, 1,
600 &aqua_vanjaram_xcp_funcs);
604 /* TODO: Default memory node affinity init */
609 int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev)
611 u32 mask, inst_mask = adev->sdma.sdma_mask;
614 /* generally 1 AID supports 4 instances */
615 adev->sdma.num_inst_per_aid = 4;
616 adev->sdma.num_instances = NUM_SDMA(adev->sdma.sdma_mask);
618 adev->aid_mask = i = 1;
619 inst_mask >>= adev->sdma.num_inst_per_aid;
621 for (mask = (1 << adev->sdma.num_inst_per_aid) - 1; inst_mask;
622 inst_mask >>= adev->sdma.num_inst_per_aid, ++i) {
623 if ((inst_mask & mask) == mask)
624 adev->aid_mask |= (1 << i);
627 /* Harvest config is not used for aqua vanjaram. VCN and JPEGs will be
628 * addressed based on logical instance ids.
630 adev->vcn.harvest_config = 0;
631 adev->vcn.num_inst_per_aid = 1;
632 adev->vcn.num_vcn_inst = hweight32(adev->vcn.inst_mask);
633 adev->jpeg.harvest_config = 0;
634 adev->jpeg.num_inst_per_aid = 1;
635 adev->jpeg.num_jpeg_inst = hweight32(adev->jpeg.inst_mask);
637 ret = aqua_vanjaram_xcp_mgr_init(adev);
641 aqua_vanjaram_ip_map_init(adev);