2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/dma-fence-array.h>
30 #include <linux/interval_tree_generic.h>
31 #include <linux/idr.h>
32 #include <linux/dma-buf.h>
34 #include <drm/amdgpu_drm.h>
35 #include <drm/drm_drv.h>
36 #include <drm/ttm/ttm_tt.h>
37 #include <drm/drm_exec.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_amdkfd.h"
41 #include "amdgpu_gmc.h"
42 #include "amdgpu_xgmi.h"
43 #include "amdgpu_dma_buf.h"
44 #include "amdgpu_res_cursor.h"
50 * GPUVM is the MMU functionality provided on the GPU.
51 * GPUVM is similar to the legacy GART on older asics, however
52 * rather than there being a single global GART table
53 * for the entire GPU, there can be multiple GPUVM page tables active
54 * at any given time. The GPUVM page tables can contain a mix
55 * VRAM pages and system pages (both memory and MMIO) and system pages
56 * can be mapped as snooped (cached system pages) or unsnooped
57 * (uncached system pages).
59 * Each active GPUVM has an ID associated with it and there is a page table
60 * linked with each VMID. When executing a command buffer,
61 * the kernel tells the engine what VMID to use for that command
62 * buffer. VMIDs are allocated dynamically as commands are submitted.
63 * The userspace drivers maintain their own address space and the kernel
64 * sets up their pages tables accordingly when they submit their
65 * command buffers and a VMID is assigned.
66 * The hardware supports up to 16 active GPUVMs at any given time.
68 * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
69 * on the ASIC family. GPUVM supports RWX attributes on each page as well
70 * as other features such as encryption and caching attributes.
72 * VMID 0 is special. It is the GPUVM used for the kernel driver. In
73 * addition to an aperture managed by a page table, VMID 0 also has
74 * several other apertures. There is an aperture for direct access to VRAM
75 * and there is a legacy AGP aperture which just forwards accesses directly
76 * to the matching system physical addresses (or IOVAs when an IOMMU is
77 * present). These apertures provide direct access to these memories without
78 * incurring the overhead of a page table. VMID 0 is used by the kernel
79 * driver for tasks like memory management.
81 * GPU clients (i.e., engines on the GPU) use GPUVM VMIDs to access memory.
82 * For user applications, each application can have their own unique GPUVM
83 * address space. The application manages the address space and the kernel
84 * driver manages the GPUVM page tables for each process. If an GPU client
85 * accesses an invalid page, it will generate a GPU page fault, similar to
86 * accessing an invalid page on a CPU.
89 #define START(node) ((node)->start)
90 #define LAST(node) ((node)->last)
92 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
93 START, LAST, static, amdgpu_vm_it)
99 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
101 struct amdgpu_prt_cb {
104 * @adev: amdgpu device
106 struct amdgpu_device *adev;
111 struct dma_fence_cb cb;
115 * struct amdgpu_vm_tlb_seq_cb - Helper to increment the TLB flush sequence
117 struct amdgpu_vm_tlb_seq_cb {
119 * @vm: pointer to the amdgpu_vm structure to set the fence sequence on
121 struct amdgpu_vm *vm;
126 struct dma_fence_cb cb;
130 * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping
132 * @adev: amdgpu_device pointer
133 * @vm: amdgpu_vm pointer
134 * @pasid: the pasid the VM is using on this GPU
136 * Set the pasid this VM is using on this GPU, can also be used to remove the
137 * pasid by passing in zero.
140 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
145 if (vm->pasid == pasid)
149 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid));
157 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm,
170 * amdgpu_vm_bo_evicted - vm_bo is evicted
172 * @vm_bo: vm_bo which is evicted
174 * State for PDs/PTs and per VM BOs which are not at the location they should
177 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
179 struct amdgpu_vm *vm = vm_bo->vm;
180 struct amdgpu_bo *bo = vm_bo->bo;
183 spin_lock(&vm_bo->vm->status_lock);
184 if (bo->tbo.type == ttm_bo_type_kernel)
185 list_move(&vm_bo->vm_status, &vm->evicted);
187 list_move_tail(&vm_bo->vm_status, &vm->evicted);
188 spin_unlock(&vm_bo->vm->status_lock);
191 * amdgpu_vm_bo_moved - vm_bo is moved
193 * @vm_bo: vm_bo which is moved
195 * State for per VM BOs which are moved, but that change is not yet reflected
196 * in the page tables.
198 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
200 spin_lock(&vm_bo->vm->status_lock);
201 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
202 spin_unlock(&vm_bo->vm->status_lock);
206 * amdgpu_vm_bo_idle - vm_bo is idle
208 * @vm_bo: vm_bo which is now idle
210 * State for PDs/PTs and per VM BOs which have gone through the state machine
213 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
215 spin_lock(&vm_bo->vm->status_lock);
216 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
217 spin_unlock(&vm_bo->vm->status_lock);
218 vm_bo->moved = false;
222 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
224 * @vm_bo: vm_bo which is now invalidated
226 * State for normal BOs which are invalidated and that change not yet reflected
229 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
231 spin_lock(&vm_bo->vm->status_lock);
232 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
233 spin_unlock(&vm_bo->vm->status_lock);
237 * amdgpu_vm_bo_relocated - vm_bo is reloacted
239 * @vm_bo: vm_bo which is relocated
241 * State for PDs/PTs which needs to update their parent PD.
242 * For the root PD, just move to idle state.
244 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
246 if (vm_bo->bo->parent) {
247 spin_lock(&vm_bo->vm->status_lock);
248 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
249 spin_unlock(&vm_bo->vm->status_lock);
251 amdgpu_vm_bo_idle(vm_bo);
256 * amdgpu_vm_bo_done - vm_bo is done
258 * @vm_bo: vm_bo which is now done
260 * State for normal BOs which are invalidated and that change has been updated
263 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
265 spin_lock(&vm_bo->vm->status_lock);
266 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
267 spin_unlock(&vm_bo->vm->status_lock);
271 * amdgpu_vm_bo_reset_state_machine - reset the vm_bo state machine
272 * @vm: the VM which state machine to reset
274 * Move all vm_bo object in the VM into a state where they will be updated
275 * again during validation.
277 static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)
279 struct amdgpu_vm_bo_base *vm_bo, *tmp;
281 spin_lock(&vm->status_lock);
282 list_splice_init(&vm->done, &vm->invalidated);
283 list_for_each_entry(vm_bo, &vm->invalidated, vm_status)
285 list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
286 struct amdgpu_bo *bo = vm_bo->bo;
288 if (!bo || bo->tbo.type != ttm_bo_type_kernel)
289 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
291 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
293 spin_unlock(&vm->status_lock);
297 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
299 * @base: base structure for tracking BO usage in a VM
300 * @vm: vm to which bo is to be added
301 * @bo: amdgpu buffer object
303 * Initialize a bo_va_base structure and add it to the appropriate lists
306 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
307 struct amdgpu_vm *vm, struct amdgpu_bo *bo)
312 INIT_LIST_HEAD(&base->vm_status);
316 base->next = bo->vm_bo;
319 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
322 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
324 ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move);
325 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
326 amdgpu_vm_bo_relocated(base);
328 amdgpu_vm_bo_idle(base);
330 if (bo->preferred_domains &
331 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
335 * we checked all the prerequisites, but it looks like this per vm bo
336 * is currently evicted. add the bo to the evicted list to make sure it
337 * is validated on next vm use to avoid fault.
339 amdgpu_vm_bo_evicted(base);
343 * amdgpu_vm_lock_pd - lock PD in drm_exec
345 * @vm: vm providing the BOs
346 * @exec: drm execution context
347 * @num_fences: number of extra fences to reserve
349 * Lock the VM root PD in the DRM execution context.
351 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,
352 unsigned int num_fences)
354 /* We need at least two fences for the VM PD/PT updates */
355 return drm_exec_prepare_obj(exec, &vm->root.bo->tbo.base,
360 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
362 * @adev: amdgpu device pointer
363 * @vm: vm providing the BOs
365 * Move all BOs to the end of LRU and remember their positions to put them
368 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
369 struct amdgpu_vm *vm)
371 spin_lock(&adev->mman.bdev.lru_lock);
372 ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
373 spin_unlock(&adev->mman.bdev.lru_lock);
376 /* Create scheduler entities for page table updates */
377 static int amdgpu_vm_init_entities(struct amdgpu_device *adev,
378 struct amdgpu_vm *vm)
382 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
383 adev->vm_manager.vm_pte_scheds,
384 adev->vm_manager.vm_pte_num_scheds, NULL);
388 return drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
389 adev->vm_manager.vm_pte_scheds,
390 adev->vm_manager.vm_pte_num_scheds, NULL);
393 drm_sched_entity_destroy(&vm->immediate);
397 /* Destroy the entities for page table updates again */
398 static void amdgpu_vm_fini_entities(struct amdgpu_vm *vm)
400 drm_sched_entity_destroy(&vm->immediate);
401 drm_sched_entity_destroy(&vm->delayed);
405 * amdgpu_vm_generation - return the page table re-generation counter
406 * @adev: the amdgpu_device
407 * @vm: optional VM to check, might be NULL
409 * Returns a page table re-generation token to allow checking if submissions
410 * are still valid to use this VM. The VM parameter might be NULL in which case
411 * just the VRAM lost counter will be used.
413 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm)
415 uint64_t result = (u64)atomic_read(&adev->vram_lost_counter) << 32;
420 result += vm->generation;
421 /* Add one if the page tables will be re-generated on next CS */
422 if (drm_sched_entity_error(&vm->delayed))
429 * amdgpu_vm_validate_pt_bos - validate the page table BOs
431 * @adev: amdgpu device pointer
432 * @vm: vm providing the BOs
433 * @validate: callback to do the validation
434 * @param: parameter for the validation callback
436 * Validate the page table BOs on command submission if neccessary.
441 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
442 int (*validate)(void *p, struct amdgpu_bo *bo),
445 struct amdgpu_vm_bo_base *bo_base;
446 struct amdgpu_bo *shadow;
447 struct amdgpu_bo *bo;
450 if (drm_sched_entity_error(&vm->delayed)) {
452 amdgpu_vm_bo_reset_state_machine(vm);
453 amdgpu_vm_fini_entities(vm);
454 r = amdgpu_vm_init_entities(adev, vm);
459 spin_lock(&vm->status_lock);
460 while (!list_empty(&vm->evicted)) {
461 bo_base = list_first_entry(&vm->evicted,
462 struct amdgpu_vm_bo_base,
464 spin_unlock(&vm->status_lock);
467 shadow = amdgpu_bo_shadowed(bo);
469 r = validate(param, bo);
473 r = validate(param, shadow);
478 if (bo->tbo.type != ttm_bo_type_kernel) {
479 amdgpu_vm_bo_moved(bo_base);
481 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
482 amdgpu_vm_bo_relocated(bo_base);
484 spin_lock(&vm->status_lock);
486 spin_unlock(&vm->status_lock);
488 amdgpu_vm_eviction_lock(vm);
489 vm->evicting = false;
490 amdgpu_vm_eviction_unlock(vm);
496 * amdgpu_vm_ready - check VM is ready for updates
500 * Check if all VM PDs/PTs are ready for updates
503 * True if VM is not evicting.
505 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
510 amdgpu_vm_eviction_lock(vm);
512 amdgpu_vm_eviction_unlock(vm);
514 spin_lock(&vm->status_lock);
515 empty = list_empty(&vm->evicted);
516 spin_unlock(&vm->status_lock);
522 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
524 * @adev: amdgpu_device pointer
526 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
528 const struct amdgpu_ip_block *ip_block;
529 bool has_compute_vm_bug;
530 struct amdgpu_ring *ring;
533 has_compute_vm_bug = false;
535 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
537 /* Compute has a VM bug for GFX version < 7.
538 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
539 if (ip_block->version->major <= 7)
540 has_compute_vm_bug = true;
541 else if (ip_block->version->major == 8)
542 if (adev->gfx.mec_fw_version < 673)
543 has_compute_vm_bug = true;
546 for (i = 0; i < adev->num_rings; i++) {
547 ring = adev->rings[i];
548 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
549 /* only compute rings */
550 ring->has_compute_vm_bug = has_compute_vm_bug;
552 ring->has_compute_vm_bug = false;
557 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
559 * @ring: ring on which the job will be submitted
560 * @job: job to submit
563 * True if sync is needed.
565 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
566 struct amdgpu_job *job)
568 struct amdgpu_device *adev = ring->adev;
569 unsigned vmhub = ring->vm_hub;
570 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
575 if (job->vm_needs_flush || ring->has_compute_vm_bug)
578 if (ring->funcs->emit_gds_switch && job->gds_switch_needed)
581 if (amdgpu_vmid_had_gpu_reset(adev, &id_mgr->ids[job->vmid]))
588 * amdgpu_vm_flush - hardware flush the vm
590 * @ring: ring to use for flush
592 * @need_pipe_sync: is pipe sync needed
594 * Emit a VM flush when it is necessary.
597 * 0 on success, errno otherwise.
599 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
602 struct amdgpu_device *adev = ring->adev;
603 unsigned vmhub = ring->vm_hub;
604 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
605 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
606 bool spm_update_needed = job->spm_update_needed;
607 bool gds_switch_needed = ring->funcs->emit_gds_switch &&
608 job->gds_switch_needed;
609 bool vm_flush_needed = job->vm_needs_flush;
610 struct dma_fence *fence = NULL;
611 bool pasid_mapping_needed = false;
612 unsigned patch_offset = 0;
615 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
616 gds_switch_needed = true;
617 vm_flush_needed = true;
618 pasid_mapping_needed = true;
619 spm_update_needed = true;
622 mutex_lock(&id_mgr->lock);
623 if (id->pasid != job->pasid || !id->pasid_mapping ||
624 !dma_fence_is_signaled(id->pasid_mapping))
625 pasid_mapping_needed = true;
626 mutex_unlock(&id_mgr->lock);
628 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
629 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
630 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
631 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
632 ring->funcs->emit_wreg;
634 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
637 amdgpu_ring_ib_begin(ring);
638 if (ring->funcs->init_cond_exec)
639 patch_offset = amdgpu_ring_init_cond_exec(ring);
642 amdgpu_ring_emit_pipeline_sync(ring);
644 if (vm_flush_needed) {
645 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
646 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
649 if (pasid_mapping_needed)
650 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
652 if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
653 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
655 if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
657 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
658 job->gds_size, job->gws_base,
659 job->gws_size, job->oa_base,
663 if (vm_flush_needed || pasid_mapping_needed) {
664 r = amdgpu_fence_emit(ring, &fence, NULL, 0);
669 if (vm_flush_needed) {
670 mutex_lock(&id_mgr->lock);
671 dma_fence_put(id->last_flush);
672 id->last_flush = dma_fence_get(fence);
673 id->current_gpu_reset_count =
674 atomic_read(&adev->gpu_reset_counter);
675 mutex_unlock(&id_mgr->lock);
678 if (pasid_mapping_needed) {
679 mutex_lock(&id_mgr->lock);
680 id->pasid = job->pasid;
681 dma_fence_put(id->pasid_mapping);
682 id->pasid_mapping = dma_fence_get(fence);
683 mutex_unlock(&id_mgr->lock);
685 dma_fence_put(fence);
687 if (ring->funcs->patch_cond_exec)
688 amdgpu_ring_patch_cond_exec(ring, patch_offset);
690 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
691 if (ring->funcs->emit_switch_buffer) {
692 amdgpu_ring_emit_switch_buffer(ring);
693 amdgpu_ring_emit_switch_buffer(ring);
695 amdgpu_ring_ib_end(ring);
700 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
703 * @bo: requested buffer object
705 * Find @bo inside the requested vm.
706 * Search inside the @bos vm list for the requested vm
707 * Returns the found bo_va or NULL if none is found
709 * Object has to be reserved!
712 * Found bo_va or NULL.
714 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
715 struct amdgpu_bo *bo)
717 struct amdgpu_vm_bo_base *base;
719 for (base = bo->vm_bo; base; base = base->next) {
723 return container_of(base, struct amdgpu_bo_va, base);
729 * amdgpu_vm_map_gart - Resolve gart mapping of addr
731 * @pages_addr: optional DMA address to use for lookup
732 * @addr: the unmapped addr
734 * Look up the physical address of the page that the pte resolves
738 * The pointer for the page table entry.
740 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
744 /* page table offset */
745 result = pages_addr[addr >> PAGE_SHIFT];
747 /* in case cpu page size != gpu page size*/
748 result |= addr & (~PAGE_MASK);
750 result &= 0xFFFFFFFFFFFFF000ULL;
756 * amdgpu_vm_update_pdes - make sure that all directories are valid
758 * @adev: amdgpu_device pointer
760 * @immediate: submit immediately to the paging queue
762 * Makes sure all directories are up to date.
765 * 0 for success, error for failure.
767 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
768 struct amdgpu_vm *vm, bool immediate)
770 struct amdgpu_vm_update_params params;
771 struct amdgpu_vm_bo_base *entry;
772 bool flush_tlb_needed = false;
773 LIST_HEAD(relocated);
776 spin_lock(&vm->status_lock);
777 list_splice_init(&vm->relocated, &relocated);
778 spin_unlock(&vm->status_lock);
780 if (list_empty(&relocated))
783 if (!drm_dev_enter(adev_to_drm(adev), &idx))
786 memset(¶ms, 0, sizeof(params));
789 params.immediate = immediate;
791 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
795 list_for_each_entry(entry, &relocated, vm_status) {
796 /* vm_flush_needed after updating moved PDEs */
797 flush_tlb_needed |= entry->moved;
799 r = amdgpu_vm_pde_update(¶ms, entry);
804 r = vm->update_funcs->commit(¶ms, &vm->last_update);
808 if (flush_tlb_needed)
809 atomic64_inc(&vm->tlb_seq);
811 while (!list_empty(&relocated)) {
812 entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base,
814 amdgpu_vm_bo_idle(entry);
823 * amdgpu_vm_tlb_seq_cb - make sure to increment tlb sequence
825 * @cb: the callback structure
827 * Increments the tlb sequence to make sure that future CS execute a VM flush.
829 static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
830 struct dma_fence_cb *cb)
832 struct amdgpu_vm_tlb_seq_cb *tlb_cb;
834 tlb_cb = container_of(cb, typeof(*tlb_cb), cb);
835 atomic64_inc(&tlb_cb->vm->tlb_seq);
840 * amdgpu_vm_update_range - update a range in the vm page table
842 * @adev: amdgpu_device pointer to use for commands
843 * @vm: the VM to update the range
844 * @immediate: immediate submission in a page fault
845 * @unlocked: unlocked invalidation during MM callback
846 * @flush_tlb: trigger tlb invalidation after update completed
847 * @resv: fences we need to sync to
848 * @start: start of mapped range
849 * @last: last mapped entry
850 * @flags: flags for the entries
851 * @offset: offset into nodes and pages_addr
852 * @vram_base: base for vram mappings
853 * @res: ttm_resource to map
854 * @pages_addr: DMA addresses to use for mapping
855 * @fence: optional resulting fence
857 * Fill in the page table entries between @start and @last.
860 * 0 for success, negative erro code for failure.
862 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
863 bool immediate, bool unlocked, bool flush_tlb,
864 struct dma_resv *resv, uint64_t start, uint64_t last,
865 uint64_t flags, uint64_t offset, uint64_t vram_base,
866 struct ttm_resource *res, dma_addr_t *pages_addr,
867 struct dma_fence **fence)
869 struct amdgpu_vm_update_params params;
870 struct amdgpu_vm_tlb_seq_cb *tlb_cb;
871 struct amdgpu_res_cursor cursor;
872 enum amdgpu_sync_mode sync_mode;
875 if (!drm_dev_enter(adev_to_drm(adev), &idx))
878 tlb_cb = kmalloc(sizeof(*tlb_cb), GFP_KERNEL);
884 /* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,
885 * heavy-weight flush TLB unconditionally.
887 flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
888 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
891 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
893 flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
895 memset(¶ms, 0, sizeof(params));
898 params.immediate = immediate;
899 params.pages_addr = pages_addr;
900 params.unlocked = unlocked;
902 /* Implicitly sync to command submissions in the same VM before
903 * unmapping. Sync to moving fences before mapping.
905 if (!(flags & AMDGPU_PTE_VALID))
906 sync_mode = AMDGPU_SYNC_EQ_OWNER;
908 sync_mode = AMDGPU_SYNC_EXPLICIT;
910 amdgpu_vm_eviction_lock(vm);
916 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
917 struct dma_fence *tmp = dma_fence_get_stub();
919 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
920 swap(vm->last_unlocked, tmp);
924 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
928 amdgpu_res_first(pages_addr ? NULL : res, offset,
929 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
930 while (cursor.remaining) {
931 uint64_t tmp, num_entries, addr;
933 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
935 bool contiguous = true;
937 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
938 uint64_t pfn = cursor.start >> PAGE_SHIFT;
941 contiguous = pages_addr[pfn + 1] ==
942 pages_addr[pfn] + PAGE_SIZE;
945 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
946 for (count = 2; count < tmp; ++count) {
947 uint64_t idx = pfn + count;
949 if (contiguous != (pages_addr[idx] ==
950 pages_addr[idx - 1] + PAGE_SIZE))
955 num_entries = count *
956 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
961 params.pages_addr = pages_addr;
963 addr = pages_addr[cursor.start >> PAGE_SHIFT];
964 params.pages_addr = NULL;
967 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
968 addr = vram_base + cursor.start;
973 tmp = start + num_entries;
974 r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags);
978 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
982 r = vm->update_funcs->commit(¶ms, fence);
984 if (flush_tlb || params.table_freed) {
986 if (fence && *fence &&
987 !dma_fence_add_callback(*fence, &tlb_cb->cb,
988 amdgpu_vm_tlb_seq_cb)) {
989 dma_fence_put(vm->last_tlb_flush);
990 vm->last_tlb_flush = dma_fence_get(*fence);
992 amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
1001 amdgpu_vm_eviction_unlock(vm);
1006 static void amdgpu_vm_bo_get_memory(struct amdgpu_bo_va *bo_va,
1007 struct amdgpu_mem_stats *stats)
1009 struct amdgpu_vm *vm = bo_va->base.vm;
1010 struct amdgpu_bo *bo = bo_va->base.bo;
1016 * For now ignore BOs which are currently locked and potentially
1017 * changing their location.
1019 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv &&
1020 !dma_resv_trylock(bo->tbo.base.resv))
1023 amdgpu_bo_get_memory(bo, stats);
1024 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
1025 dma_resv_unlock(bo->tbo.base.resv);
1028 void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
1029 struct amdgpu_mem_stats *stats)
1031 struct amdgpu_bo_va *bo_va, *tmp;
1033 spin_lock(&vm->status_lock);
1034 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status)
1035 amdgpu_vm_bo_get_memory(bo_va, stats);
1037 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status)
1038 amdgpu_vm_bo_get_memory(bo_va, stats);
1040 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status)
1041 amdgpu_vm_bo_get_memory(bo_va, stats);
1043 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status)
1044 amdgpu_vm_bo_get_memory(bo_va, stats);
1046 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status)
1047 amdgpu_vm_bo_get_memory(bo_va, stats);
1049 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status)
1050 amdgpu_vm_bo_get_memory(bo_va, stats);
1051 spin_unlock(&vm->status_lock);
1055 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1057 * @adev: amdgpu_device pointer
1058 * @bo_va: requested BO and VM object
1059 * @clear: if true clear the entries
1061 * Fill in the page table entries for @bo_va.
1064 * 0 for success, -EINVAL for failure.
1066 int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1069 struct amdgpu_bo *bo = bo_va->base.bo;
1070 struct amdgpu_vm *vm = bo_va->base.vm;
1071 struct amdgpu_bo_va_mapping *mapping;
1072 dma_addr_t *pages_addr = NULL;
1073 struct ttm_resource *mem;
1074 struct dma_fence **last_update;
1075 bool flush_tlb = clear;
1076 struct dma_resv *resv;
1083 resv = vm->root.bo->tbo.base.resv;
1085 struct drm_gem_object *obj = &bo->tbo.base;
1087 resv = bo->tbo.base.resv;
1088 if (obj->import_attach && bo_va->is_xgmi) {
1089 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1090 struct drm_gem_object *gobj = dma_buf->priv;
1091 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1093 if (abo->tbo.resource->mem_type == TTM_PL_VRAM)
1094 bo = gem_to_amdgpu_bo(gobj);
1096 mem = bo->tbo.resource;
1097 if (mem->mem_type == TTM_PL_TT ||
1098 mem->mem_type == AMDGPU_PL_PREEMPT)
1099 pages_addr = bo->tbo.ttm->dma_address;
1103 struct amdgpu_device *bo_adev;
1105 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1107 if (amdgpu_bo_encrypted(bo))
1108 flags |= AMDGPU_PTE_TMZ;
1110 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1111 vram_base = bo_adev->vm_manager.vram_base_offset;
1117 if (clear || (bo && bo->tbo.base.resv ==
1118 vm->root.bo->tbo.base.resv))
1119 last_update = &vm->last_update;
1121 last_update = &bo_va->last_pt_update;
1123 if (!clear && bo_va->base.moved) {
1125 list_splice_init(&bo_va->valids, &bo_va->invalids);
1127 } else if (bo_va->cleared != clear) {
1128 list_splice_init(&bo_va->valids, &bo_va->invalids);
1131 list_for_each_entry(mapping, &bo_va->invalids, list) {
1132 uint64_t update_flags = flags;
1134 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1135 * but in case of something, we filter the flags in first place
1137 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1138 update_flags &= ~AMDGPU_PTE_READABLE;
1139 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1140 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1142 /* Apply ASIC specific mapping flags */
1143 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1145 trace_amdgpu_vm_bo_update(mapping);
1147 r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
1148 resv, mapping->start, mapping->last,
1149 update_flags, mapping->offset,
1150 vram_base, mem, pages_addr,
1156 /* If the BO is not in its preferred location add it back to
1157 * the evicted list so that it gets validated again on the
1158 * next command submission.
1160 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1161 uint32_t mem_type = bo->tbo.resource->mem_type;
1163 if (!(bo->preferred_domains &
1164 amdgpu_mem_type_to_domain(mem_type)))
1165 amdgpu_vm_bo_evicted(&bo_va->base);
1167 amdgpu_vm_bo_idle(&bo_va->base);
1169 amdgpu_vm_bo_done(&bo_va->base);
1172 list_splice_init(&bo_va->invalids, &bo_va->valids);
1173 bo_va->cleared = clear;
1174 bo_va->base.moved = false;
1176 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1177 list_for_each_entry(mapping, &bo_va->valids, list)
1178 trace_amdgpu_vm_bo_mapping(mapping);
1185 * amdgpu_vm_update_prt_state - update the global PRT state
1187 * @adev: amdgpu_device pointer
1189 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1191 unsigned long flags;
1194 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1195 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1196 adev->gmc.gmc_funcs->set_prt(adev, enable);
1197 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1201 * amdgpu_vm_prt_get - add a PRT user
1203 * @adev: amdgpu_device pointer
1205 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1207 if (!adev->gmc.gmc_funcs->set_prt)
1210 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1211 amdgpu_vm_update_prt_state(adev);
1215 * amdgpu_vm_prt_put - drop a PRT user
1217 * @adev: amdgpu_device pointer
1219 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1221 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1222 amdgpu_vm_update_prt_state(adev);
1226 * amdgpu_vm_prt_cb - callback for updating the PRT status
1228 * @fence: fence for the callback
1229 * @_cb: the callback function
1231 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1233 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1235 amdgpu_vm_prt_put(cb->adev);
1240 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1242 * @adev: amdgpu_device pointer
1243 * @fence: fence for the callback
1245 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1246 struct dma_fence *fence)
1248 struct amdgpu_prt_cb *cb;
1250 if (!adev->gmc.gmc_funcs->set_prt)
1253 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1255 /* Last resort when we are OOM */
1257 dma_fence_wait(fence, false);
1259 amdgpu_vm_prt_put(adev);
1262 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1264 amdgpu_vm_prt_cb(fence, &cb->cb);
1269 * amdgpu_vm_free_mapping - free a mapping
1271 * @adev: amdgpu_device pointer
1273 * @mapping: mapping to be freed
1274 * @fence: fence of the unmap operation
1276 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1278 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1279 struct amdgpu_vm *vm,
1280 struct amdgpu_bo_va_mapping *mapping,
1281 struct dma_fence *fence)
1283 if (mapping->flags & AMDGPU_PTE_PRT)
1284 amdgpu_vm_add_prt_cb(adev, fence);
1289 * amdgpu_vm_prt_fini - finish all prt mappings
1291 * @adev: amdgpu_device pointer
1294 * Register a cleanup callback to disable PRT support after VM dies.
1296 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1298 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1299 struct dma_resv_iter cursor;
1300 struct dma_fence *fence;
1302 dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {
1303 /* Add a callback for each fence in the reservation object */
1304 amdgpu_vm_prt_get(adev);
1305 amdgpu_vm_add_prt_cb(adev, fence);
1310 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1312 * @adev: amdgpu_device pointer
1314 * @fence: optional resulting fence (unchanged if no work needed to be done
1315 * or if an error occurred)
1317 * Make sure all freed BOs are cleared in the PT.
1318 * PTs have to be reserved and mutex must be locked!
1324 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1325 struct amdgpu_vm *vm,
1326 struct dma_fence **fence)
1328 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1329 struct amdgpu_bo_va_mapping *mapping;
1330 uint64_t init_pte_value = 0;
1331 struct dma_fence *f = NULL;
1334 while (!list_empty(&vm->freed)) {
1335 mapping = list_first_entry(&vm->freed,
1336 struct amdgpu_bo_va_mapping, list);
1337 list_del(&mapping->list);
1339 if (vm->pte_support_ats &&
1340 mapping->start < AMDGPU_GMC_HOLE_START)
1341 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
1343 r = amdgpu_vm_update_range(adev, vm, false, false, true, resv,
1344 mapping->start, mapping->last,
1345 init_pte_value, 0, 0, NULL, NULL,
1347 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1355 dma_fence_put(*fence);
1366 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1368 * @adev: amdgpu_device pointer
1371 * Make sure all BOs which are moved are updated in the PTs.
1376 * PTs have to be reserved!
1378 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1379 struct amdgpu_vm *vm)
1381 struct amdgpu_bo_va *bo_va;
1382 struct dma_resv *resv;
1386 spin_lock(&vm->status_lock);
1387 while (!list_empty(&vm->moved)) {
1388 bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va,
1390 spin_unlock(&vm->status_lock);
1392 /* Per VM BOs never need to bo cleared in the page tables */
1393 r = amdgpu_vm_bo_update(adev, bo_va, false);
1396 spin_lock(&vm->status_lock);
1399 while (!list_empty(&vm->invalidated)) {
1400 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1402 resv = bo_va->base.bo->tbo.base.resv;
1403 spin_unlock(&vm->status_lock);
1405 /* Try to reserve the BO to avoid clearing its ptes */
1406 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
1408 /* Somebody else is using the BO right now */
1412 r = amdgpu_vm_bo_update(adev, bo_va, clear);
1417 dma_resv_unlock(resv);
1418 spin_lock(&vm->status_lock);
1420 spin_unlock(&vm->status_lock);
1426 * amdgpu_vm_bo_add - add a bo to a specific vm
1428 * @adev: amdgpu_device pointer
1430 * @bo: amdgpu buffer object
1432 * Add @bo into the requested vm.
1433 * Add @bo to the list of bos associated with the vm
1436 * Newly added bo_va or NULL for failure
1438 * Object has to be reserved!
1440 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1441 struct amdgpu_vm *vm,
1442 struct amdgpu_bo *bo)
1444 struct amdgpu_bo_va *bo_va;
1446 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1447 if (bo_va == NULL) {
1450 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
1452 bo_va->ref_count = 1;
1453 bo_va->last_pt_update = dma_fence_get_stub();
1454 INIT_LIST_HEAD(&bo_va->valids);
1455 INIT_LIST_HEAD(&bo_va->invalids);
1460 dma_resv_assert_held(bo->tbo.base.resv);
1461 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
1462 bo_va->is_xgmi = true;
1463 /* Power up XGMI if it can be potentially used */
1464 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
1472 * amdgpu_vm_bo_insert_map - insert a new mapping
1474 * @adev: amdgpu_device pointer
1475 * @bo_va: bo_va to store the address
1476 * @mapping: the mapping to insert
1478 * Insert a new mapping into all structures.
1480 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
1481 struct amdgpu_bo_va *bo_va,
1482 struct amdgpu_bo_va_mapping *mapping)
1484 struct amdgpu_vm *vm = bo_va->base.vm;
1485 struct amdgpu_bo *bo = bo_va->base.bo;
1487 mapping->bo_va = bo_va;
1488 list_add(&mapping->list, &bo_va->invalids);
1489 amdgpu_vm_it_insert(mapping, &vm->va);
1491 if (mapping->flags & AMDGPU_PTE_PRT)
1492 amdgpu_vm_prt_get(adev);
1494 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1495 !bo_va->base.moved) {
1496 amdgpu_vm_bo_moved(&bo_va->base);
1498 trace_amdgpu_vm_bo_map(bo_va, mapping);
1502 * amdgpu_vm_bo_map - map bo inside a vm
1504 * @adev: amdgpu_device pointer
1505 * @bo_va: bo_va to store the address
1506 * @saddr: where to map the BO
1507 * @offset: requested offset in the BO
1508 * @size: BO size in bytes
1509 * @flags: attributes of pages (read/write/valid/etc.)
1511 * Add a mapping of the BO at the specefied addr into the VM.
1514 * 0 for success, error for failure.
1516 * Object has to be reserved and unreserved outside!
1518 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1519 struct amdgpu_bo_va *bo_va,
1520 uint64_t saddr, uint64_t offset,
1521 uint64_t size, uint64_t flags)
1523 struct amdgpu_bo_va_mapping *mapping, *tmp;
1524 struct amdgpu_bo *bo = bo_va->base.bo;
1525 struct amdgpu_vm *vm = bo_va->base.vm;
1528 /* validate the parameters */
1529 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK || size & ~PAGE_MASK)
1531 if (saddr + size <= saddr || offset + size <= offset)
1534 /* make sure object fit at this offset */
1535 eaddr = saddr + size - 1;
1536 if ((bo && offset + size > amdgpu_bo_size(bo)) ||
1537 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
1540 saddr /= AMDGPU_GPU_PAGE_SIZE;
1541 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1543 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1545 /* bo and tmp overlap, invalid addr */
1546 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1547 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
1548 tmp->start, tmp->last + 1);
1552 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1556 mapping->start = saddr;
1557 mapping->last = eaddr;
1558 mapping->offset = offset;
1559 mapping->flags = flags;
1561 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1567 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1569 * @adev: amdgpu_device pointer
1570 * @bo_va: bo_va to store the address
1571 * @saddr: where to map the BO
1572 * @offset: requested offset in the BO
1573 * @size: BO size in bytes
1574 * @flags: attributes of pages (read/write/valid/etc.)
1576 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1577 * mappings as we do so.
1580 * 0 for success, error for failure.
1582 * Object has to be reserved and unreserved outside!
1584 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1585 struct amdgpu_bo_va *bo_va,
1586 uint64_t saddr, uint64_t offset,
1587 uint64_t size, uint64_t flags)
1589 struct amdgpu_bo_va_mapping *mapping;
1590 struct amdgpu_bo *bo = bo_va->base.bo;
1594 /* validate the parameters */
1595 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK || size & ~PAGE_MASK)
1597 if (saddr + size <= saddr || offset + size <= offset)
1600 /* make sure object fit at this offset */
1601 eaddr = saddr + size - 1;
1602 if ((bo && offset + size > amdgpu_bo_size(bo)) ||
1603 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
1606 /* Allocate all the needed memory */
1607 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1611 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
1617 saddr /= AMDGPU_GPU_PAGE_SIZE;
1618 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1620 mapping->start = saddr;
1621 mapping->last = eaddr;
1622 mapping->offset = offset;
1623 mapping->flags = flags;
1625 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1631 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1633 * @adev: amdgpu_device pointer
1634 * @bo_va: bo_va to remove the address from
1635 * @saddr: where to the BO is mapped
1637 * Remove a mapping of the BO at the specefied addr from the VM.
1640 * 0 for success, error for failure.
1642 * Object has to be reserved and unreserved outside!
1644 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1645 struct amdgpu_bo_va *bo_va,
1648 struct amdgpu_bo_va_mapping *mapping;
1649 struct amdgpu_vm *vm = bo_va->base.vm;
1652 saddr /= AMDGPU_GPU_PAGE_SIZE;
1654 list_for_each_entry(mapping, &bo_va->valids, list) {
1655 if (mapping->start == saddr)
1659 if (&mapping->list == &bo_va->valids) {
1662 list_for_each_entry(mapping, &bo_va->invalids, list) {
1663 if (mapping->start == saddr)
1667 if (&mapping->list == &bo_va->invalids)
1671 list_del(&mapping->list);
1672 amdgpu_vm_it_remove(mapping, &vm->va);
1673 mapping->bo_va = NULL;
1674 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1677 list_add(&mapping->list, &vm->freed);
1679 amdgpu_vm_free_mapping(adev, vm, mapping,
1680 bo_va->last_pt_update);
1686 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1688 * @adev: amdgpu_device pointer
1689 * @vm: VM structure to use
1690 * @saddr: start of the range
1691 * @size: size of the range
1693 * Remove all mappings in a range, split them as appropriate.
1696 * 0 for success, error for failure.
1698 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1699 struct amdgpu_vm *vm,
1700 uint64_t saddr, uint64_t size)
1702 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1706 eaddr = saddr + size - 1;
1707 saddr /= AMDGPU_GPU_PAGE_SIZE;
1708 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1710 /* Allocate all the needed memory */
1711 before = kzalloc(sizeof(*before), GFP_KERNEL);
1714 INIT_LIST_HEAD(&before->list);
1716 after = kzalloc(sizeof(*after), GFP_KERNEL);
1721 INIT_LIST_HEAD(&after->list);
1723 /* Now gather all removed mappings */
1724 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1726 /* Remember mapping split at the start */
1727 if (tmp->start < saddr) {
1728 before->start = tmp->start;
1729 before->last = saddr - 1;
1730 before->offset = tmp->offset;
1731 before->flags = tmp->flags;
1732 before->bo_va = tmp->bo_va;
1733 list_add(&before->list, &tmp->bo_va->invalids);
1736 /* Remember mapping split at the end */
1737 if (tmp->last > eaddr) {
1738 after->start = eaddr + 1;
1739 after->last = tmp->last;
1740 after->offset = tmp->offset;
1741 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
1742 after->flags = tmp->flags;
1743 after->bo_va = tmp->bo_va;
1744 list_add(&after->list, &tmp->bo_va->invalids);
1747 list_del(&tmp->list);
1748 list_add(&tmp->list, &removed);
1750 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1753 /* And free them up */
1754 list_for_each_entry_safe(tmp, next, &removed, list) {
1755 amdgpu_vm_it_remove(tmp, &vm->va);
1756 list_del(&tmp->list);
1758 if (tmp->start < saddr)
1760 if (tmp->last > eaddr)
1764 list_add(&tmp->list, &vm->freed);
1765 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1768 /* Insert partial mapping before the range */
1769 if (!list_empty(&before->list)) {
1770 struct amdgpu_bo *bo = before->bo_va->base.bo;
1772 amdgpu_vm_it_insert(before, &vm->va);
1773 if (before->flags & AMDGPU_PTE_PRT)
1774 amdgpu_vm_prt_get(adev);
1776 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1777 !before->bo_va->base.moved)
1778 amdgpu_vm_bo_moved(&before->bo_va->base);
1783 /* Insert partial mapping after the range */
1784 if (!list_empty(&after->list)) {
1785 struct amdgpu_bo *bo = after->bo_va->base.bo;
1787 amdgpu_vm_it_insert(after, &vm->va);
1788 if (after->flags & AMDGPU_PTE_PRT)
1789 amdgpu_vm_prt_get(adev);
1791 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1792 !after->bo_va->base.moved)
1793 amdgpu_vm_bo_moved(&after->bo_va->base);
1802 * amdgpu_vm_bo_lookup_mapping - find mapping by address
1804 * @vm: the requested VM
1805 * @addr: the address
1807 * Find a mapping by it's address.
1810 * The amdgpu_bo_va_mapping matching for addr or NULL
1813 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
1816 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
1820 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
1822 * @vm: the requested vm
1823 * @ticket: CS ticket
1825 * Trace all mappings of BOs reserved during a command submission.
1827 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
1829 struct amdgpu_bo_va_mapping *mapping;
1831 if (!trace_amdgpu_vm_bo_cs_enabled())
1834 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
1835 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
1836 if (mapping->bo_va && mapping->bo_va->base.bo) {
1837 struct amdgpu_bo *bo;
1839 bo = mapping->bo_va->base.bo;
1840 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
1845 trace_amdgpu_vm_bo_cs(mapping);
1850 * amdgpu_vm_bo_del - remove a bo from a specific vm
1852 * @adev: amdgpu_device pointer
1853 * @bo_va: requested bo_va
1855 * Remove @bo_va->bo from the requested vm.
1857 * Object have to be reserved!
1859 void amdgpu_vm_bo_del(struct amdgpu_device *adev,
1860 struct amdgpu_bo_va *bo_va)
1862 struct amdgpu_bo_va_mapping *mapping, *next;
1863 struct amdgpu_bo *bo = bo_va->base.bo;
1864 struct amdgpu_vm *vm = bo_va->base.vm;
1865 struct amdgpu_vm_bo_base **base;
1867 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
1870 dma_resv_assert_held(bo->tbo.base.resv);
1871 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
1872 ttm_bo_set_bulk_move(&bo->tbo, NULL);
1874 for (base = &bo_va->base.bo->vm_bo; *base;
1875 base = &(*base)->next) {
1876 if (*base != &bo_va->base)
1879 *base = bo_va->base.next;
1884 spin_lock(&vm->status_lock);
1885 list_del(&bo_va->base.vm_status);
1886 spin_unlock(&vm->status_lock);
1888 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
1889 list_del(&mapping->list);
1890 amdgpu_vm_it_remove(mapping, &vm->va);
1891 mapping->bo_va = NULL;
1892 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1893 list_add(&mapping->list, &vm->freed);
1895 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1896 list_del(&mapping->list);
1897 amdgpu_vm_it_remove(mapping, &vm->va);
1898 amdgpu_vm_free_mapping(adev, vm, mapping,
1899 bo_va->last_pt_update);
1902 dma_fence_put(bo_va->last_pt_update);
1904 if (bo && bo_va->is_xgmi)
1905 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
1911 * amdgpu_vm_evictable - check if we can evict a VM
1913 * @bo: A page table of the VM.
1915 * Check if it is possible to evict a VM.
1917 bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
1919 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
1921 /* Page tables of a destroyed VM can go away immediately */
1922 if (!bo_base || !bo_base->vm)
1925 /* Don't evict VM page tables while they are busy */
1926 if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP))
1929 /* Try to block ongoing updates */
1930 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
1933 /* Don't evict VM page tables while they are updated */
1934 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
1935 amdgpu_vm_eviction_unlock(bo_base->vm);
1939 bo_base->vm->evicting = true;
1940 amdgpu_vm_eviction_unlock(bo_base->vm);
1945 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1947 * @adev: amdgpu_device pointer
1948 * @bo: amdgpu buffer object
1949 * @evicted: is the BO evicted
1951 * Mark @bo as invalid.
1953 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1954 struct amdgpu_bo *bo, bool evicted)
1956 struct amdgpu_vm_bo_base *bo_base;
1958 /* shadow bo doesn't have bo base, its validation needs its parent */
1959 if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
1962 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
1963 struct amdgpu_vm *vm = bo_base->vm;
1965 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1966 amdgpu_vm_bo_evicted(bo_base);
1972 bo_base->moved = true;
1974 if (bo->tbo.type == ttm_bo_type_kernel)
1975 amdgpu_vm_bo_relocated(bo_base);
1976 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
1977 amdgpu_vm_bo_moved(bo_base);
1979 amdgpu_vm_bo_invalidated(bo_base);
1984 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
1989 * VM page table as power of two
1991 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
1993 /* Total bits covered by PD + PTs */
1994 unsigned bits = ilog2(vm_size) + 18;
1996 /* Make sure the PD is 4K in size up to 8GB address space.
1997 Above that split equal between PD and PTs */
2001 return ((bits + 3) / 2);
2005 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2007 * @adev: amdgpu_device pointer
2008 * @min_vm_size: the minimum vm size in GB if it's set auto
2009 * @fragment_size_default: Default PTE fragment size
2010 * @max_level: max VMPT level
2011 * @max_bits: max address space size in bits
2014 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2015 uint32_t fragment_size_default, unsigned max_level,
2018 unsigned int max_size = 1 << (max_bits - 30);
2019 unsigned int vm_size;
2022 /* adjust vm size first */
2023 if (amdgpu_vm_size != -1) {
2024 vm_size = amdgpu_vm_size;
2025 if (vm_size > max_size) {
2026 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2027 amdgpu_vm_size, max_size);
2032 unsigned int phys_ram_gb;
2034 /* Optimal VM size depends on the amount of physical
2035 * RAM available. Underlying requirements and
2038 * - Need to map system memory and VRAM from all GPUs
2039 * - VRAM from other GPUs not known here
2040 * - Assume VRAM <= system memory
2041 * - On GFX8 and older, VM space can be segmented for
2043 * - Need to allow room for fragmentation, guard pages etc.
2045 * This adds up to a rough guess of system memory x3.
2046 * Round up to power of two to maximize the available
2047 * VM size with the given page table size.
2050 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2051 (1 << 30) - 1) >> 30;
2052 vm_size = roundup_pow_of_two(
2053 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2056 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2058 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2059 if (amdgpu_vm_block_size != -1)
2060 tmp >>= amdgpu_vm_block_size - 9;
2061 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2062 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2063 switch (adev->vm_manager.num_level) {
2065 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2068 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2071 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2074 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2076 /* block size depends on vm size and hw setup*/
2077 if (amdgpu_vm_block_size != -1)
2078 adev->vm_manager.block_size =
2079 min((unsigned)amdgpu_vm_block_size, max_bits
2080 - AMDGPU_GPU_PAGE_SHIFT
2081 - 9 * adev->vm_manager.num_level);
2082 else if (adev->vm_manager.num_level > 1)
2083 adev->vm_manager.block_size = 9;
2085 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2087 if (amdgpu_vm_fragment_size == -1)
2088 adev->vm_manager.fragment_size = fragment_size_default;
2090 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2092 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2093 vm_size, adev->vm_manager.num_level + 1,
2094 adev->vm_manager.block_size,
2095 adev->vm_manager.fragment_size);
2099 * amdgpu_vm_wait_idle - wait for the VM to become idle
2101 * @vm: VM object to wait for
2102 * @timeout: timeout to wait for VM to become idle
2104 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2106 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv,
2107 DMA_RESV_USAGE_BOOKKEEP,
2112 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2116 * amdgpu_vm_init - initialize a vm instance
2118 * @adev: amdgpu_device pointer
2124 * 0 for success, error for failure.
2126 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2128 struct amdgpu_bo *root_bo;
2129 struct amdgpu_bo_vm *root;
2132 vm->va = RB_ROOT_CACHED;
2133 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2134 vm->reserved_vmid[i] = NULL;
2135 INIT_LIST_HEAD(&vm->evicted);
2136 INIT_LIST_HEAD(&vm->relocated);
2137 INIT_LIST_HEAD(&vm->moved);
2138 INIT_LIST_HEAD(&vm->idle);
2139 INIT_LIST_HEAD(&vm->invalidated);
2140 spin_lock_init(&vm->status_lock);
2141 INIT_LIST_HEAD(&vm->freed);
2142 INIT_LIST_HEAD(&vm->done);
2143 INIT_LIST_HEAD(&vm->pt_freed);
2144 INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
2146 r = amdgpu_vm_init_entities(adev, vm);
2150 vm->pte_support_ats = false;
2151 vm->is_compute_context = false;
2153 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2154 AMDGPU_VM_USE_CPU_FOR_GFX);
2156 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2157 vm->use_cpu_for_update ? "CPU" : "SDMA");
2158 WARN_ONCE((vm->use_cpu_for_update &&
2159 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2160 "CPU update of VM recommended only for large BAR system\n");
2162 if (vm->use_cpu_for_update)
2163 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2165 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2167 vm->last_update = dma_fence_get_stub();
2168 vm->last_unlocked = dma_fence_get_stub();
2169 vm->last_tlb_flush = dma_fence_get_stub();
2172 mutex_init(&vm->eviction_lock);
2173 vm->evicting = false;
2175 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2178 goto error_free_delayed;
2179 root_bo = &root->bo;
2180 r = amdgpu_bo_reserve(root_bo, true);
2182 goto error_free_root;
2184 r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
2186 goto error_unreserve;
2188 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2190 r = amdgpu_vm_pt_clear(adev, vm, root, false);
2192 goto error_unreserve;
2194 amdgpu_bo_unreserve(vm->root.bo);
2196 INIT_KFIFO(vm->faults);
2201 amdgpu_bo_unreserve(vm->root.bo);
2204 amdgpu_bo_unref(&root->shadow);
2205 amdgpu_bo_unref(&root_bo);
2209 dma_fence_put(vm->last_tlb_flush);
2210 dma_fence_put(vm->last_unlocked);
2211 amdgpu_vm_fini_entities(vm);
2217 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2219 * @adev: amdgpu_device pointer
2222 * This only works on GFX VMs that don't have any BOs added and no
2223 * page tables allocated yet.
2225 * Changes the following VM parameters:
2226 * - use_cpu_for_update
2227 * - pte_supports_ats
2229 * Reinitializes the page directory to reflect the changed ATS
2233 * 0 for success, -errno for errors.
2235 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2237 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
2240 r = amdgpu_bo_reserve(vm->root.bo, true);
2244 /* Check if PD needs to be reinitialized and do it before
2245 * changing any other state, in case it fails.
2247 if (pte_support_ats != vm->pte_support_ats) {
2249 if (!amdgpu_vm_pt_is_root_clean(adev, vm)) {
2254 vm->pte_support_ats = pte_support_ats;
2255 r = amdgpu_vm_pt_clear(adev, vm, to_amdgpu_bo_vm(vm->root.bo),
2261 /* Update VM state */
2262 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2263 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2264 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2265 vm->use_cpu_for_update ? "CPU" : "SDMA");
2266 WARN_ONCE((vm->use_cpu_for_update &&
2267 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2268 "CPU update of VM recommended only for large BAR system\n");
2270 if (vm->use_cpu_for_update) {
2271 /* Sync with last SDMA update/clear before switching to CPU */
2272 r = amdgpu_bo_sync_wait(vm->root.bo,
2273 AMDGPU_FENCE_OWNER_UNDEFINED, true);
2277 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2279 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2282 * Make sure root PD gets mapped. As vm_update_mode could be changed
2283 * when turning a GFX VM into a compute VM.
2285 r = vm->update_funcs->map_table(to_amdgpu_bo_vm(vm->root.bo));
2289 dma_fence_put(vm->last_update);
2290 vm->last_update = dma_fence_get_stub();
2291 vm->is_compute_context = true;
2293 /* Free the shadow bo for compute VM */
2294 amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
2299 amdgpu_bo_unreserve(vm->root.bo);
2304 * amdgpu_vm_release_compute - release a compute vm
2305 * @adev: amdgpu_device pointer
2306 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2308 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2309 * pasid from vm. Compute should stop use of vm after this call.
2311 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2313 amdgpu_vm_set_pasid(adev, vm, 0);
2314 vm->is_compute_context = false;
2318 * amdgpu_vm_fini - tear down a vm instance
2320 * @adev: amdgpu_device pointer
2324 * Unbind the VM and remove all bos from the vm bo list
2326 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2328 struct amdgpu_bo_va_mapping *mapping, *tmp;
2329 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2330 struct amdgpu_bo *root;
2331 unsigned long flags;
2334 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2336 flush_work(&vm->pt_free_work);
2338 root = amdgpu_bo_ref(vm->root.bo);
2339 amdgpu_bo_reserve(root, true);
2340 amdgpu_vm_set_pasid(adev, vm, 0);
2341 dma_fence_wait(vm->last_unlocked, false);
2342 dma_fence_put(vm->last_unlocked);
2343 dma_fence_wait(vm->last_tlb_flush, false);
2344 /* Make sure that all fence callbacks have completed */
2345 spin_lock_irqsave(vm->last_tlb_flush->lock, flags);
2346 spin_unlock_irqrestore(vm->last_tlb_flush->lock, flags);
2347 dma_fence_put(vm->last_tlb_flush);
2349 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2350 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2351 amdgpu_vm_prt_fini(adev, vm);
2352 prt_fini_needed = false;
2355 list_del(&mapping->list);
2356 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2359 amdgpu_vm_pt_free_root(adev, vm);
2360 amdgpu_bo_unreserve(root);
2361 amdgpu_bo_unref(&root);
2362 WARN_ON(vm->root.bo);
2364 amdgpu_vm_fini_entities(vm);
2366 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2367 dev_err(adev->dev, "still active bo inside vm\n");
2369 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2370 &vm->va.rb_root, rb) {
2371 /* Don't remove the mapping here, we don't want to trigger a
2372 * rebalance and the tree is about to be destroyed anyway.
2374 list_del(&mapping->list);
2378 dma_fence_put(vm->last_update);
2380 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) {
2381 if (vm->reserved_vmid[i]) {
2382 amdgpu_vmid_free_reserved(adev, i);
2383 vm->reserved_vmid[i] = false;
2390 * amdgpu_vm_manager_init - init the VM manager
2392 * @adev: amdgpu_device pointer
2394 * Initialize the VM manager structures
2396 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2400 /* Concurrent flushes are only possible starting with Vega10 and
2401 * are broken on Navi10 and Navi14.
2403 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
2404 adev->asic_type == CHIP_NAVI10 ||
2405 adev->asic_type == CHIP_NAVI14);
2406 amdgpu_vmid_mgr_init(adev);
2408 adev->vm_manager.fence_context =
2409 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2410 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2411 adev->vm_manager.seqno[i] = 0;
2413 spin_lock_init(&adev->vm_manager.prt_lock);
2414 atomic_set(&adev->vm_manager.num_prt_users, 0);
2416 /* If not overridden by the user, by default, only in large BAR systems
2417 * Compute VM tables will be updated by CPU
2419 #ifdef CONFIG_X86_64
2420 if (amdgpu_vm_update_mode == -1) {
2421 /* For asic with VF MMIO access protection
2422 * avoid using CPU for VM table updates
2424 if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
2425 !amdgpu_sriov_vf_mmio_access_protection(adev))
2426 adev->vm_manager.vm_update_mode =
2427 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2429 adev->vm_manager.vm_update_mode = 0;
2431 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2433 adev->vm_manager.vm_update_mode = 0;
2436 xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ);
2440 * amdgpu_vm_manager_fini - cleanup VM manager
2442 * @adev: amdgpu_device pointer
2444 * Cleanup the VM manager and free resources.
2446 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2448 WARN_ON(!xa_empty(&adev->vm_manager.pasids));
2449 xa_destroy(&adev->vm_manager.pasids);
2451 amdgpu_vmid_mgr_fini(adev);
2455 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
2457 * @dev: drm device pointer
2458 * @data: drm_amdgpu_vm
2459 * @filp: drm file pointer
2462 * 0 for success, -errno for errors.
2464 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2466 union drm_amdgpu_vm *args = data;
2467 struct amdgpu_device *adev = drm_to_adev(dev);
2468 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2470 /* No valid flags defined yet */
2474 switch (args->in.op) {
2475 case AMDGPU_VM_OP_RESERVE_VMID:
2476 /* We only have requirement to reserve vmid from gfxhub */
2477 if (!fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2478 amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));
2479 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = true;
2483 case AMDGPU_VM_OP_UNRESERVE_VMID:
2484 if (fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2485 amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(0));
2486 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = false;
2497 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
2499 * @adev: drm device pointer
2500 * @pasid: PASID identifier for VM
2501 * @task_info: task_info to fill.
2503 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
2504 struct amdgpu_task_info *task_info)
2506 struct amdgpu_vm *vm;
2507 unsigned long flags;
2509 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2511 vm = xa_load(&adev->vm_manager.pasids, pasid);
2513 *task_info = vm->task_info;
2515 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2519 * amdgpu_vm_set_task_info - Sets VMs task info.
2521 * @vm: vm for which to set the info
2523 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
2525 if (vm->task_info.pid)
2528 vm->task_info.pid = current->pid;
2529 get_task_comm(vm->task_info.task_name, current);
2531 if (current->group_leader->mm != current->mm)
2534 vm->task_info.tgid = current->group_leader->pid;
2535 get_task_comm(vm->task_info.process_name, current->group_leader);
2539 * amdgpu_vm_handle_fault - graceful handling of VM faults.
2540 * @adev: amdgpu device pointer
2541 * @pasid: PASID of the VM
2542 * @vmid: VMID, only used for GFX 9.4.3.
2543 * @node_id: Node_id received in IH cookie. Only applicable for
2545 * @addr: Address of the fault
2546 * @write_fault: true is write fault, false is read fault
2548 * Try to gracefully handle a VM fault. Return true if the fault was handled and
2549 * shouldn't be reported any more.
2551 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
2552 u32 vmid, u32 node_id, uint64_t addr,
2555 bool is_compute_context = false;
2556 struct amdgpu_bo *root;
2557 unsigned long irqflags;
2558 uint64_t value, flags;
2559 struct amdgpu_vm *vm;
2562 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2563 vm = xa_load(&adev->vm_manager.pasids, pasid);
2565 root = amdgpu_bo_ref(vm->root.bo);
2566 is_compute_context = vm->is_compute_context;
2570 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2575 addr /= AMDGPU_GPU_PAGE_SIZE;
2577 if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid,
2578 node_id, addr, write_fault)) {
2579 amdgpu_bo_unref(&root);
2583 r = amdgpu_bo_reserve(root, true);
2587 /* Double check that the VM still exists */
2588 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2589 vm = xa_load(&adev->vm_manager.pasids, pasid);
2590 if (vm && vm->root.bo != root)
2592 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2596 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
2599 if (is_compute_context) {
2600 /* Intentionally setting invalid PTE flag
2601 * combination to force a no-retry-fault
2603 flags = AMDGPU_PTE_SNOOPED | AMDGPU_PTE_PRT;
2605 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
2606 /* Redirect the access to the dummy page */
2607 value = adev->dummy_page_addr;
2608 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
2609 AMDGPU_PTE_WRITEABLE;
2612 /* Let the hw retry silently on the PTE */
2616 r = dma_resv_reserve_fences(root->tbo.base.resv, 1);
2618 pr_debug("failed %d to reserve fence slot\n", r);
2622 r = amdgpu_vm_update_range(adev, vm, true, false, false, NULL, addr,
2623 addr, flags, value, 0, NULL, NULL, NULL);
2627 r = amdgpu_vm_update_pdes(adev, vm, true);
2630 amdgpu_bo_unreserve(root);
2632 DRM_ERROR("Can't handle page fault (%d)\n", r);
2635 amdgpu_bo_unref(&root);
2640 #if defined(CONFIG_DEBUG_FS)
2642 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
2644 * @vm: Requested VM for printing BO info
2647 * Print BO information in debugfs file for the VM
2649 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
2651 struct amdgpu_bo_va *bo_va, *tmp;
2653 u64 total_evicted = 0;
2654 u64 total_relocated = 0;
2655 u64 total_moved = 0;
2656 u64 total_invalidated = 0;
2658 unsigned int total_idle_objs = 0;
2659 unsigned int total_evicted_objs = 0;
2660 unsigned int total_relocated_objs = 0;
2661 unsigned int total_moved_objs = 0;
2662 unsigned int total_invalidated_objs = 0;
2663 unsigned int total_done_objs = 0;
2664 unsigned int id = 0;
2666 spin_lock(&vm->status_lock);
2667 seq_puts(m, "\tIdle BOs:\n");
2668 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
2669 if (!bo_va->base.bo)
2671 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2673 total_idle_objs = id;
2676 seq_puts(m, "\tEvicted BOs:\n");
2677 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
2678 if (!bo_va->base.bo)
2680 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2682 total_evicted_objs = id;
2685 seq_puts(m, "\tRelocated BOs:\n");
2686 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
2687 if (!bo_va->base.bo)
2689 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2691 total_relocated_objs = id;
2694 seq_puts(m, "\tMoved BOs:\n");
2695 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2696 if (!bo_va->base.bo)
2698 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2700 total_moved_objs = id;
2703 seq_puts(m, "\tInvalidated BOs:\n");
2704 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
2705 if (!bo_va->base.bo)
2707 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2709 total_invalidated_objs = id;
2712 seq_puts(m, "\tDone BOs:\n");
2713 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
2714 if (!bo_va->base.bo)
2716 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2718 spin_unlock(&vm->status_lock);
2719 total_done_objs = id;
2721 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
2723 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
2724 total_evicted_objs);
2725 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
2726 total_relocated_objs);
2727 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
2729 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
2730 total_invalidated_objs);
2731 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,