2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
30 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_trace.h"
36 * GPUVM is similar to the legacy gart on older asics, however
37 * rather than there being a single global gart table
38 * for the entire GPU, there are multiple VM page tables active
39 * at any given time. The VM page tables can contain a mix
40 * vram pages and system memory pages and system memory pages
41 * can be mapped as snooped (cached system pages) or unsnooped
42 * (uncached system pages).
43 * Each VM has an ID associated with it and there is a page table
44 * associated with each VMID. When execting a command buffer,
45 * the kernel tells the the ring what VMID to use for that command
46 * buffer. VMIDs are allocated dynamically as commands are submitted.
47 * The userspace drivers maintain their own address space and the kernel
48 * sets up their pages tables accordingly when they submit their
49 * command buffers and a VMID is assigned.
50 * Cayman/Trinity support up to 8 active VMs at any given time;
54 /* Local structure. Encapsulate some VM table update parameters to reduce
55 * the number of function parameters
57 struct amdgpu_pte_update_params {
58 /* amdgpu device we do this update for */
59 struct amdgpu_device *adev;
60 /* address where to copy page table entries from */
62 /* indirect buffer to fill with commands */
64 /* Function which actually does the update */
65 void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe,
66 uint64_t addr, unsigned count, uint32_t incr,
68 /* indicate update pt or its shadow */
72 /* Helper to disable partial resident texture feature from a fence callback */
73 struct amdgpu_prt_cb {
74 struct amdgpu_device *adev;
75 struct dma_fence_cb cb;
79 * amdgpu_vm_num_pde - return the number of page directory entries
81 * @adev: amdgpu_device pointer
83 * Calculate the number of page directory entries.
85 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
87 return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;
91 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
93 * @adev: amdgpu_device pointer
95 * Calculate the size of the page directory in bytes.
97 static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
99 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);
103 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
105 * @vm: vm providing the BOs
106 * @validated: head of validation list
107 * @entry: entry to add
109 * Add the page directory to the list of BOs to
110 * validate for command submission.
112 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
113 struct list_head *validated,
114 struct amdgpu_bo_list_entry *entry)
116 entry->robj = vm->page_directory;
118 entry->tv.bo = &vm->page_directory->tbo;
119 entry->tv.shared = true;
120 entry->user_pages = NULL;
121 list_add(&entry->tv.head, validated);
125 * amdgpu_vm_validate_pt_bos - validate the page table BOs
127 * @adev: amdgpu device pointer
128 * @vm: vm providing the BOs
129 * @validate: callback to do the validation
130 * @param: parameter for the validation callback
132 * Validate the page table BOs on command submission if neccessary.
134 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
135 int (*validate)(void *p, struct amdgpu_bo *bo),
138 uint64_t num_evictions;
142 /* We only need to validate the page tables
143 * if they aren't already valid.
145 num_evictions = atomic64_read(&adev->num_evictions);
146 if (num_evictions == vm->last_eviction_counter)
149 /* add the vm page table to the list */
150 for (i = 0; i <= vm->max_pde_used; ++i) {
151 struct amdgpu_bo *bo = vm->page_tables[i].bo;
156 r = validate(param, bo);
165 * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
167 * @adev: amdgpu device instance
168 * @vm: vm providing the BOs
170 * Move the PT BOs to the tail of the LRU.
172 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
173 struct amdgpu_vm *vm)
175 struct ttm_bo_global *glob = adev->mman.bdev.glob;
178 spin_lock(&glob->lru_lock);
179 for (i = 0; i <= vm->max_pde_used; ++i) {
180 struct amdgpu_bo *bo = vm->page_tables[i].bo;
185 ttm_bo_move_to_lru_tail(&bo->tbo);
187 spin_unlock(&glob->lru_lock);
191 * amdgpu_vm_alloc_pts - Allocate page tables.
193 * @adev: amdgpu_device pointer
194 * @vm: VM to allocate page tables for
195 * @saddr: Start address which needs to be allocated
196 * @size: Size from start address we need.
198 * Make sure the page tables are allocated.
200 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
201 struct amdgpu_vm *vm,
202 uint64_t saddr, uint64_t size)
204 unsigned last_pfn, pt_idx;
208 /* validate the parameters */
209 if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
212 eaddr = saddr + size - 1;
213 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
214 if (last_pfn >= adev->vm_manager.max_pfn) {
215 dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n",
216 last_pfn, adev->vm_manager.max_pfn);
220 saddr /= AMDGPU_GPU_PAGE_SIZE;
221 eaddr /= AMDGPU_GPU_PAGE_SIZE;
223 saddr >>= amdgpu_vm_block_size;
224 eaddr >>= amdgpu_vm_block_size;
226 BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
228 if (eaddr > vm->max_pde_used)
229 vm->max_pde_used = eaddr;
231 /* walk over the address space and allocate the page tables */
232 for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
233 struct reservation_object *resv = vm->page_directory->tbo.resv;
234 struct amdgpu_bo *pt;
236 if (vm->page_tables[pt_idx].bo)
239 r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
240 AMDGPU_GPU_PAGE_SIZE, true,
241 AMDGPU_GEM_DOMAIN_VRAM,
242 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
243 AMDGPU_GEM_CREATE_SHADOW |
244 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
245 AMDGPU_GEM_CREATE_VRAM_CLEARED,
250 /* Keep a reference to the page table to avoid freeing
251 * them up in the wrong order.
253 pt->parent = amdgpu_bo_ref(vm->page_directory);
255 vm->page_tables[pt_idx].bo = pt;
256 vm->page_tables[pt_idx].addr = 0;
262 static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device *adev,
263 struct amdgpu_vm_id *id)
265 return id->current_gpu_reset_count !=
266 atomic_read(&adev->gpu_reset_counter) ? true : false;
270 * amdgpu_vm_grab_id - allocate the next free VMID
272 * @vm: vm to allocate id for
273 * @ring: ring we want to submit job to
274 * @sync: sync object where we add dependencies
275 * @fence: fence protecting ID from reuse
277 * Allocate an id for the vm, adding fences to the sync obj as necessary.
279 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
280 struct amdgpu_sync *sync, struct dma_fence *fence,
281 struct amdgpu_job *job)
283 struct amdgpu_device *adev = ring->adev;
284 uint64_t fence_context = adev->fence_context + ring->idx;
285 struct dma_fence *updates = sync->last_vm_update;
286 struct amdgpu_vm_id *id, *idle;
287 struct dma_fence **fences;
291 fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids,
296 mutex_lock(&adev->vm_manager.lock);
298 /* Check if we have an idle VMID */
300 list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) {
301 fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
307 /* If we can't find a idle VMID to use, wait till one becomes available */
308 if (&idle->list == &adev->vm_manager.ids_lru) {
309 u64 fence_context = adev->vm_manager.fence_context + ring->idx;
310 unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
311 struct dma_fence_array *array;
314 for (j = 0; j < i; ++j)
315 dma_fence_get(fences[j]);
317 array = dma_fence_array_create(i, fences, fence_context,
320 for (j = 0; j < i; ++j)
321 dma_fence_put(fences[j]);
328 r = amdgpu_sync_fence(ring->adev, sync, &array->base);
329 dma_fence_put(&array->base);
333 mutex_unlock(&adev->vm_manager.lock);
339 job->vm_needs_flush = true;
340 /* Check if we can use a VMID already assigned to this VM */
343 struct dma_fence *flushed;
346 if (i == AMDGPU_MAX_RINGS)
349 /* Check all the prerequisites to using this VMID */
352 if (amdgpu_vm_is_gpu_reset(adev, id))
355 if (atomic64_read(&id->owner) != vm->client_id)
358 if (job->vm_pd_addr != id->pd_gpu_addr)
364 if (id->last_flush->context != fence_context &&
365 !dma_fence_is_signaled(id->last_flush))
368 flushed = id->flushed_updates;
370 (!flushed || dma_fence_is_later(updates, flushed)))
373 /* Good we can use this VMID. Remember this submission as
376 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
380 id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
381 list_move_tail(&id->list, &adev->vm_manager.ids_lru);
382 vm->ids[ring->idx] = id;
384 job->vm_id = id - adev->vm_manager.ids;
385 job->vm_needs_flush = false;
386 trace_amdgpu_vm_grab_id(vm, ring->idx, job);
388 mutex_unlock(&adev->vm_manager.lock);
391 } while (i != ring->idx);
393 /* Still no ID to use? Then use the idle one found earlier */
396 /* Remember this submission as user of the VMID */
397 r = amdgpu_sync_fence(ring->adev, &id->active, fence);
401 dma_fence_put(id->first);
402 id->first = dma_fence_get(fence);
404 dma_fence_put(id->last_flush);
405 id->last_flush = NULL;
407 dma_fence_put(id->flushed_updates);
408 id->flushed_updates = dma_fence_get(updates);
410 id->pd_gpu_addr = job->vm_pd_addr;
411 id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter);
412 list_move_tail(&id->list, &adev->vm_manager.ids_lru);
413 atomic64_set(&id->owner, vm->client_id);
414 vm->ids[ring->idx] = id;
416 job->vm_id = id - adev->vm_manager.ids;
417 trace_amdgpu_vm_grab_id(vm, ring->idx, job);
420 mutex_unlock(&adev->vm_manager.lock);
424 static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring)
426 struct amdgpu_device *adev = ring->adev;
427 const struct amdgpu_ip_block *ip_block;
429 if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
430 /* only compute rings */
433 ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
437 if (ip_block->version->major <= 7) {
438 /* gfx7 has no workaround */
440 } else if (ip_block->version->major == 8) {
441 if (adev->gfx.mec_fw_version >= 673)
442 /* gfx8 is fixed in MEC firmware 673 */
451 * amdgpu_vm_flush - hardware flush the vm
453 * @ring: ring to use for flush
454 * @vm_id: vmid number to use
455 * @pd_addr: address of the page directory
457 * Emit a VM flush when it is necessary.
459 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
461 struct amdgpu_device *adev = ring->adev;
462 struct amdgpu_vm_id *id = &adev->vm_manager.ids[job->vm_id];
463 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
464 id->gds_base != job->gds_base ||
465 id->gds_size != job->gds_size ||
466 id->gws_base != job->gws_base ||
467 id->gws_size != job->gws_size ||
468 id->oa_base != job->oa_base ||
469 id->oa_size != job->oa_size);
472 if (ring->funcs->emit_pipeline_sync && (
473 job->vm_needs_flush || gds_switch_needed ||
474 amdgpu_vm_ring_has_compute_vm_bug(ring)))
475 amdgpu_ring_emit_pipeline_sync(ring);
477 if (ring->funcs->emit_vm_flush && (job->vm_needs_flush ||
478 amdgpu_vm_is_gpu_reset(adev, id))) {
479 struct dma_fence *fence;
481 trace_amdgpu_vm_flush(job->vm_pd_addr, ring->idx, job->vm_id);
482 amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr);
484 r = amdgpu_fence_emit(ring, &fence);
488 mutex_lock(&adev->vm_manager.lock);
489 dma_fence_put(id->last_flush);
490 id->last_flush = fence;
491 mutex_unlock(&adev->vm_manager.lock);
494 if (gds_switch_needed) {
495 id->gds_base = job->gds_base;
496 id->gds_size = job->gds_size;
497 id->gws_base = job->gws_base;
498 id->gws_size = job->gws_size;
499 id->oa_base = job->oa_base;
500 id->oa_size = job->oa_size;
501 amdgpu_ring_emit_gds_switch(ring, job->vm_id,
502 job->gds_base, job->gds_size,
503 job->gws_base, job->gws_size,
504 job->oa_base, job->oa_size);
511 * amdgpu_vm_reset_id - reset VMID to zero
513 * @adev: amdgpu device structure
514 * @vm_id: vmid number to use
516 * Reset saved GDW, GWS and OA to force switch on next flush.
518 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id)
520 struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id];
531 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
534 * @bo: requested buffer object
536 * Find @bo inside the requested vm.
537 * Search inside the @bos vm list for the requested vm
538 * Returns the found bo_va or NULL if none is found
540 * Object has to be reserved!
542 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
543 struct amdgpu_bo *bo)
545 struct amdgpu_bo_va *bo_va;
547 list_for_each_entry(bo_va, &bo->va, bo_list) {
548 if (bo_va->vm == vm) {
556 * amdgpu_vm_do_set_ptes - helper to call the right asic function
558 * @params: see amdgpu_pte_update_params definition
559 * @pe: addr of the page entry
560 * @addr: dst addr to write into pe
561 * @count: number of page entries to update
562 * @incr: increase next addr by incr bytes
563 * @flags: hw access flags
565 * Traces the parameters and calls the right asic functions
566 * to setup the page table using the DMA.
568 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
569 uint64_t pe, uint64_t addr,
570 unsigned count, uint32_t incr,
573 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
576 amdgpu_vm_write_pte(params->adev, params->ib, pe,
577 addr | flags, count, incr);
580 amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
586 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
588 * @params: see amdgpu_pte_update_params definition
589 * @pe: addr of the page entry
590 * @addr: dst addr to write into pe
591 * @count: number of page entries to update
592 * @incr: increase next addr by incr bytes
593 * @flags: hw access flags
595 * Traces the parameters and calls the DMA function to copy the PTEs.
597 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
598 uint64_t pe, uint64_t addr,
599 unsigned count, uint32_t incr,
602 uint64_t src = (params->src + (addr >> 12) * 8);
605 trace_amdgpu_vm_copy_ptes(pe, src, count);
607 amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
611 * amdgpu_vm_map_gart - Resolve gart mapping of addr
613 * @pages_addr: optional DMA address to use for lookup
614 * @addr: the unmapped addr
616 * Look up the physical address of the page that the pte resolves
617 * to and return the pointer for the page table entry.
619 static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
623 /* page table offset */
624 result = pages_addr[addr >> PAGE_SHIFT];
626 /* in case cpu page size != gpu page size*/
627 result |= addr & (~PAGE_MASK);
629 result &= 0xFFFFFFFFFFFFF000ULL;
635 * amdgpu_vm_update_pdes - make sure that page directory is valid
637 * @adev: amdgpu_device pointer
639 * @start: start of GPU address range
640 * @end: end of GPU address range
642 * Allocates new page tables if necessary
643 * and updates the page directory.
644 * Returns 0 for success, error for failure.
646 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
647 struct amdgpu_vm *vm)
649 struct amdgpu_bo *shadow;
650 struct amdgpu_ring *ring;
651 uint64_t pd_addr, shadow_addr;
652 uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
653 uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0;
654 unsigned count = 0, pt_idx, ndw;
655 struct amdgpu_job *job;
656 struct amdgpu_pte_update_params params;
657 struct dma_fence *fence = NULL;
661 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
662 shadow = vm->page_directory->shadow;
667 /* assume the worst case */
668 ndw += vm->max_pde_used * 6;
670 pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
672 r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem);
675 shadow_addr = amdgpu_bo_gpu_offset(shadow);
681 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
685 memset(¶ms, 0, sizeof(params));
687 params.ib = &job->ibs[0];
689 /* walk over the address space and update the page directory */
690 for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
691 struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo;
698 struct amdgpu_bo *pt_shadow = bo->shadow;
700 r = amdgpu_ttm_bind(&pt_shadow->tbo,
701 &pt_shadow->tbo.mem);
706 pt = amdgpu_bo_gpu_offset(bo);
707 if (vm->page_tables[pt_idx].addr == pt)
710 vm->page_tables[pt_idx].addr = pt;
712 pde = pd_addr + pt_idx * 8;
713 if (((last_pde + 8 * count) != pde) ||
714 ((last_pt + incr * count) != pt) ||
715 (count == AMDGPU_VM_MAX_UPDATE_SIZE)) {
719 amdgpu_vm_do_set_ptes(¶ms,
725 amdgpu_vm_do_set_ptes(¶ms, last_pde,
726 last_pt, count, incr,
732 last_shadow = shadow_addr + pt_idx * 8;
740 if (vm->page_directory->shadow)
741 amdgpu_vm_do_set_ptes(¶ms, last_shadow, last_pt,
742 count, incr, AMDGPU_PTE_VALID);
744 amdgpu_vm_do_set_ptes(¶ms, last_pde, last_pt,
745 count, incr, AMDGPU_PTE_VALID);
748 if (params.ib->length_dw == 0) {
749 amdgpu_job_free(job);
753 amdgpu_ring_pad_ib(ring, params.ib);
754 amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv,
755 AMDGPU_FENCE_OWNER_VM);
757 amdgpu_sync_resv(adev, &job->sync, shadow->tbo.resv,
758 AMDGPU_FENCE_OWNER_VM);
760 WARN_ON(params.ib->length_dw > ndw);
761 r = amdgpu_job_submit(job, ring, &vm->entity,
762 AMDGPU_FENCE_OWNER_VM, &fence);
766 amdgpu_bo_fence(vm->page_directory, fence, true);
767 dma_fence_put(vm->page_directory_fence);
768 vm->page_directory_fence = dma_fence_get(fence);
769 dma_fence_put(fence);
774 amdgpu_job_free(job);
779 * amdgpu_vm_update_ptes - make sure that page tables are valid
781 * @params: see amdgpu_pte_update_params definition
783 * @start: start of GPU address range
784 * @end: end of GPU address range
785 * @dst: destination address to map to, the next dst inside the function
786 * @flags: mapping flags
788 * Update the page tables in the range @start - @end.
790 static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
791 struct amdgpu_vm *vm,
792 uint64_t start, uint64_t end,
793 uint64_t dst, uint64_t flags)
795 const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
797 uint64_t cur_pe_start, cur_nptes, cur_dst;
798 uint64_t addr; /* next GPU address to be updated */
800 struct amdgpu_bo *pt;
801 unsigned nptes; /* next number of ptes to be updated */
802 uint64_t next_pe_start;
804 /* initialize the variables */
806 pt_idx = addr >> amdgpu_vm_block_size;
807 pt = vm->page_tables[pt_idx].bo;
808 if (params->shadow) {
813 if ((addr & ~mask) == (end & ~mask))
816 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
818 cur_pe_start = amdgpu_bo_gpu_offset(pt);
819 cur_pe_start += (addr & mask) * 8;
825 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
827 /* walk over the address space and update the page tables */
829 pt_idx = addr >> amdgpu_vm_block_size;
830 pt = vm->page_tables[pt_idx].bo;
831 if (params->shadow) {
837 if ((addr & ~mask) == (end & ~mask))
840 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
842 next_pe_start = amdgpu_bo_gpu_offset(pt);
843 next_pe_start += (addr & mask) * 8;
845 if ((cur_pe_start + 8 * cur_nptes) == next_pe_start &&
846 ((cur_nptes + nptes) <= AMDGPU_VM_MAX_UPDATE_SIZE)) {
847 /* The next ptb is consecutive to current ptb.
848 * Don't call the update function now.
849 * Will update two ptbs together in future.
853 params->func(params, cur_pe_start, cur_dst, cur_nptes,
854 AMDGPU_GPU_PAGE_SIZE, flags);
856 cur_pe_start = next_pe_start;
863 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
866 params->func(params, cur_pe_start, cur_dst, cur_nptes,
867 AMDGPU_GPU_PAGE_SIZE, flags);
871 * amdgpu_vm_frag_ptes - add fragment information to PTEs
873 * @params: see amdgpu_pte_update_params definition
875 * @start: first PTE to handle
876 * @end: last PTE to handle
877 * @dst: addr those PTEs should point to
878 * @flags: hw mapping flags
880 static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
881 struct amdgpu_vm *vm,
882 uint64_t start, uint64_t end,
883 uint64_t dst, uint64_t flags)
886 * The MC L1 TLB supports variable sized pages, based on a fragment
887 * field in the PTE. When this field is set to a non-zero value, page
888 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
889 * flags are considered valid for all PTEs within the fragment range
890 * and corresponding mappings are assumed to be physically contiguous.
892 * The L1 TLB can store a single PTE for the whole fragment,
893 * significantly increasing the space available for translation
894 * caching. This leads to large improvements in throughput when the
895 * TLB is under pressure.
897 * The L2 TLB distributes small and large fragments into two
898 * asymmetric partitions. The large fragment cache is significantly
899 * larger. Thus, we try to use large fragments wherever possible.
900 * Userspace can support this by aligning virtual base address and
901 * allocation size to the fragment size.
904 /* SI and newer are optimized for 64KB */
905 uint64_t frag_flags = AMDGPU_PTE_FRAG(AMDGPU_LOG2_PAGES_PER_FRAG);
906 uint64_t frag_align = 1 << AMDGPU_LOG2_PAGES_PER_FRAG;
908 uint64_t frag_start = ALIGN(start, frag_align);
909 uint64_t frag_end = end & ~(frag_align - 1);
911 /* system pages are non continuously */
912 if (params->src || !(flags & AMDGPU_PTE_VALID) ||
913 (frag_start >= frag_end)) {
915 amdgpu_vm_update_ptes(params, vm, start, end, dst, flags);
919 /* handle the 4K area at the beginning */
920 if (start != frag_start) {
921 amdgpu_vm_update_ptes(params, vm, start, frag_start,
923 dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE;
926 /* handle the area in the middle */
927 amdgpu_vm_update_ptes(params, vm, frag_start, frag_end, dst,
930 /* handle the 4K area at the end */
931 if (frag_end != end) {
932 dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE;
933 amdgpu_vm_update_ptes(params, vm, frag_end, end, dst, flags);
938 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
940 * @adev: amdgpu_device pointer
941 * @exclusive: fence we need to sync to
942 * @src: address where to copy page table entries from
943 * @pages_addr: DMA addresses to use for mapping
945 * @start: start of mapped range
946 * @last: last mapped entry
947 * @flags: flags for the entries
948 * @addr: addr to set the area to
949 * @fence: optional resulting fence
951 * Fill in the page table entries between @start and @last.
952 * Returns 0 for success, -EINVAL for failure.
954 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
955 struct dma_fence *exclusive,
957 dma_addr_t *pages_addr,
958 struct amdgpu_vm *vm,
959 uint64_t start, uint64_t last,
960 uint64_t flags, uint64_t addr,
961 struct dma_fence **fence)
963 struct amdgpu_ring *ring;
964 void *owner = AMDGPU_FENCE_OWNER_VM;
965 unsigned nptes, ncmds, ndw;
966 struct amdgpu_job *job;
967 struct amdgpu_pte_update_params params;
968 struct dma_fence *f = NULL;
971 memset(¶ms, 0, sizeof(params));
975 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
977 /* sync to everything on unmapping */
978 if (!(flags & AMDGPU_PTE_VALID))
979 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
981 nptes = last - start + 1;
984 * reserve space for one command every (1 << BLOCK_SIZE)
985 * entries or 2k dwords (whatever is smaller)
987 ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1;
993 /* only copy commands needed */
996 params.func = amdgpu_vm_do_copy_ptes;
998 } else if (pages_addr) {
999 /* copy commands needed */
1005 params.func = amdgpu_vm_do_copy_ptes;
1008 /* set page commands needed */
1011 /* two extra commands for begin/end of fragment */
1014 params.func = amdgpu_vm_do_set_ptes;
1017 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1021 params.ib = &job->ibs[0];
1023 if (!src && pages_addr) {
1027 /* Put the PTEs at the end of the IB. */
1028 i = ndw - nptes * 2;
1029 pte= (uint64_t *)&(job->ibs->ptr[i]);
1030 params.src = job->ibs->gpu_addr + i * 4;
1032 for (i = 0; i < nptes; ++i) {
1033 pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
1034 AMDGPU_GPU_PAGE_SIZE);
1040 r = amdgpu_sync_fence(adev, &job->sync, exclusive);
1044 r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv,
1049 r = reservation_object_reserve_shared(vm->page_directory->tbo.resv);
1053 params.shadow = true;
1054 amdgpu_vm_frag_ptes(¶ms, vm, start, last + 1, addr, flags);
1055 params.shadow = false;
1056 amdgpu_vm_frag_ptes(¶ms, vm, start, last + 1, addr, flags);
1058 amdgpu_ring_pad_ib(ring, params.ib);
1059 WARN_ON(params.ib->length_dw > ndw);
1060 r = amdgpu_job_submit(job, ring, &vm->entity,
1061 AMDGPU_FENCE_OWNER_VM, &f);
1065 amdgpu_bo_fence(vm->page_directory, f, true);
1066 dma_fence_put(*fence);
1071 amdgpu_job_free(job);
1076 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1078 * @adev: amdgpu_device pointer
1079 * @exclusive: fence we need to sync to
1080 * @gtt_flags: flags as they are used for GTT
1081 * @pages_addr: DMA addresses to use for mapping
1083 * @mapping: mapped range and flags to use for the update
1084 * @flags: HW flags for the mapping
1085 * @nodes: array of drm_mm_nodes with the MC addresses
1086 * @fence: optional resulting fence
1088 * Split the mapping into smaller chunks so that each update fits
1090 * Returns 0 for success, -EINVAL for failure.
1092 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1093 struct dma_fence *exclusive,
1095 dma_addr_t *pages_addr,
1096 struct amdgpu_vm *vm,
1097 struct amdgpu_bo_va_mapping *mapping,
1099 struct drm_mm_node *nodes,
1100 struct dma_fence **fence)
1102 uint64_t pfn, src = 0, start = mapping->it.start;
1105 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1106 * but in case of something, we filter the flags in first place
1108 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1109 flags &= ~AMDGPU_PTE_READABLE;
1110 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1111 flags &= ~AMDGPU_PTE_WRITEABLE;
1113 trace_amdgpu_vm_bo_update(mapping);
1115 pfn = mapping->offset >> PAGE_SHIFT;
1117 while (pfn >= nodes->size) {
1124 uint64_t max_entries;
1125 uint64_t addr, last;
1128 addr = nodes->start << PAGE_SHIFT;
1129 max_entries = (nodes->size - pfn) *
1130 (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
1133 max_entries = S64_MAX;
1137 if (flags == gtt_flags)
1138 src = adev->gart.table_addr +
1139 (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8;
1141 max_entries = min(max_entries, 16ull * 1024ull);
1143 } else if (flags & AMDGPU_PTE_VALID) {
1144 addr += adev->vm_manager.vram_base_offset;
1146 addr += pfn << PAGE_SHIFT;
1148 last = min((uint64_t)mapping->it.last, start + max_entries - 1);
1149 r = amdgpu_vm_bo_update_mapping(adev, exclusive,
1150 src, pages_addr, vm,
1151 start, last, flags, addr,
1156 pfn += last - start + 1;
1157 if (nodes && nodes->size == pfn) {
1163 } while (unlikely(start != mapping->it.last + 1));
1169 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1171 * @adev: amdgpu_device pointer
1172 * @bo_va: requested BO and VM object
1173 * @clear: if true clear the entries
1175 * Fill in the page table entries for @bo_va.
1176 * Returns 0 for success, -EINVAL for failure.
1178 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1179 struct amdgpu_bo_va *bo_va,
1182 struct amdgpu_vm *vm = bo_va->vm;
1183 struct amdgpu_bo_va_mapping *mapping;
1184 dma_addr_t *pages_addr = NULL;
1185 uint64_t gtt_flags, flags;
1186 struct ttm_mem_reg *mem;
1187 struct drm_mm_node *nodes;
1188 struct dma_fence *exclusive;
1191 if (clear || !bo_va->bo) {
1196 struct ttm_dma_tt *ttm;
1198 mem = &bo_va->bo->tbo.mem;
1199 nodes = mem->mm_node;
1200 if (mem->mem_type == TTM_PL_TT) {
1201 ttm = container_of(bo_va->bo->tbo.ttm, struct
1203 pages_addr = ttm->dma_address;
1205 exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv);
1209 flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
1210 gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
1211 adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ?
1218 spin_lock(&vm->status_lock);
1219 if (!list_empty(&bo_va->vm_status))
1220 list_splice_init(&bo_va->valids, &bo_va->invalids);
1221 spin_unlock(&vm->status_lock);
1223 list_for_each_entry(mapping, &bo_va->invalids, list) {
1224 r = amdgpu_vm_bo_split_mapping(adev, exclusive,
1225 gtt_flags, pages_addr, vm,
1226 mapping, flags, nodes,
1227 &bo_va->last_pt_update);
1232 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1233 list_for_each_entry(mapping, &bo_va->valids, list)
1234 trace_amdgpu_vm_bo_mapping(mapping);
1236 list_for_each_entry(mapping, &bo_va->invalids, list)
1237 trace_amdgpu_vm_bo_mapping(mapping);
1240 spin_lock(&vm->status_lock);
1241 list_splice_init(&bo_va->invalids, &bo_va->valids);
1242 list_del_init(&bo_va->vm_status);
1244 list_add(&bo_va->vm_status, &vm->cleared);
1245 spin_unlock(&vm->status_lock);
1251 * amdgpu_vm_update_prt_state - update the global PRT state
1253 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1255 unsigned long flags;
1258 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1259 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1260 adev->gart.gart_funcs->set_prt(adev, enable);
1261 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1265 * amdgpu_vm_prt_get - add a PRT user
1267 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1269 if (!adev->gart.gart_funcs->set_prt)
1272 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1273 amdgpu_vm_update_prt_state(adev);
1277 * amdgpu_vm_prt_put - drop a PRT user
1279 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1281 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1282 amdgpu_vm_update_prt_state(adev);
1286 * amdgpu_vm_prt_cb - callback for updating the PRT status
1288 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1290 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1292 amdgpu_vm_prt_put(cb->adev);
1297 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1299 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1300 struct dma_fence *fence)
1302 struct amdgpu_prt_cb *cb;
1304 if (!adev->gart.gart_funcs->set_prt)
1307 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1309 /* Last resort when we are OOM */
1311 dma_fence_wait(fence, false);
1313 amdgpu_vm_prt_put(cb->adev);
1316 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1318 amdgpu_vm_prt_cb(fence, &cb->cb);
1323 * amdgpu_vm_free_mapping - free a mapping
1325 * @adev: amdgpu_device pointer
1327 * @mapping: mapping to be freed
1328 * @fence: fence of the unmap operation
1330 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1332 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1333 struct amdgpu_vm *vm,
1334 struct amdgpu_bo_va_mapping *mapping,
1335 struct dma_fence *fence)
1337 if (mapping->flags & AMDGPU_PTE_PRT)
1338 amdgpu_vm_add_prt_cb(adev, fence);
1343 * amdgpu_vm_prt_fini - finish all prt mappings
1345 * @adev: amdgpu_device pointer
1348 * Register a cleanup callback to disable PRT support after VM dies.
1350 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1352 struct reservation_object *resv = vm->page_directory->tbo.resv;
1353 struct dma_fence *excl, **shared;
1354 unsigned i, shared_count;
1357 r = reservation_object_get_fences_rcu(resv, &excl,
1358 &shared_count, &shared);
1360 /* Not enough memory to grab the fence list, as last resort
1361 * block for all the fences to complete.
1363 reservation_object_wait_timeout_rcu(resv, true, false,
1364 MAX_SCHEDULE_TIMEOUT);
1368 /* Add a callback for each fence in the reservation object */
1369 amdgpu_vm_prt_get(adev);
1370 amdgpu_vm_add_prt_cb(adev, excl);
1372 for (i = 0; i < shared_count; ++i) {
1373 amdgpu_vm_prt_get(adev);
1374 amdgpu_vm_add_prt_cb(adev, shared[i]);
1381 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1383 * @adev: amdgpu_device pointer
1385 * @fence: optional resulting fence (unchanged if no work needed to be done
1386 * or if an error occurred)
1388 * Make sure all freed BOs are cleared in the PT.
1389 * Returns 0 for success.
1391 * PTs have to be reserved and mutex must be locked!
1393 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1394 struct amdgpu_vm *vm,
1395 struct dma_fence **fence)
1397 struct amdgpu_bo_va_mapping *mapping;
1398 struct dma_fence *f = NULL;
1401 while (!list_empty(&vm->freed)) {
1402 mapping = list_first_entry(&vm->freed,
1403 struct amdgpu_bo_va_mapping, list);
1404 list_del(&mapping->list);
1406 r = amdgpu_vm_bo_split_mapping(adev, NULL, 0, NULL, vm, mapping,
1408 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1416 dma_fence_put(*fence);
1427 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1429 * @adev: amdgpu_device pointer
1432 * Make sure all invalidated BOs are cleared in the PT.
1433 * Returns 0 for success.
1435 * PTs have to be reserved and mutex must be locked!
1437 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
1438 struct amdgpu_vm *vm, struct amdgpu_sync *sync)
1440 struct amdgpu_bo_va *bo_va = NULL;
1443 spin_lock(&vm->status_lock);
1444 while (!list_empty(&vm->invalidated)) {
1445 bo_va = list_first_entry(&vm->invalidated,
1446 struct amdgpu_bo_va, vm_status);
1447 spin_unlock(&vm->status_lock);
1449 r = amdgpu_vm_bo_update(adev, bo_va, true);
1453 spin_lock(&vm->status_lock);
1455 spin_unlock(&vm->status_lock);
1458 r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
1464 * amdgpu_vm_bo_add - add a bo to a specific vm
1466 * @adev: amdgpu_device pointer
1468 * @bo: amdgpu buffer object
1470 * Add @bo into the requested vm.
1471 * Add @bo to the list of bos associated with the vm
1472 * Returns newly added bo_va or NULL for failure
1474 * Object has to be reserved!
1476 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1477 struct amdgpu_vm *vm,
1478 struct amdgpu_bo *bo)
1480 struct amdgpu_bo_va *bo_va;
1482 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1483 if (bo_va == NULL) {
1488 bo_va->ref_count = 1;
1489 INIT_LIST_HEAD(&bo_va->bo_list);
1490 INIT_LIST_HEAD(&bo_va->valids);
1491 INIT_LIST_HEAD(&bo_va->invalids);
1492 INIT_LIST_HEAD(&bo_va->vm_status);
1495 list_add_tail(&bo_va->bo_list, &bo->va);
1501 * amdgpu_vm_bo_map - map bo inside a vm
1503 * @adev: amdgpu_device pointer
1504 * @bo_va: bo_va to store the address
1505 * @saddr: where to map the BO
1506 * @offset: requested offset in the BO
1507 * @flags: attributes of pages (read/write/valid/etc.)
1509 * Add a mapping of the BO at the specefied addr into the VM.
1510 * Returns 0 for success, error for failure.
1512 * Object has to be reserved and unreserved outside!
1514 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1515 struct amdgpu_bo_va *bo_va,
1516 uint64_t saddr, uint64_t offset,
1517 uint64_t size, uint64_t flags)
1519 struct amdgpu_bo_va_mapping *mapping;
1520 struct amdgpu_vm *vm = bo_va->vm;
1521 struct interval_tree_node *it;
1524 /* validate the parameters */
1525 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1526 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1529 /* make sure object fit at this offset */
1530 eaddr = saddr + size - 1;
1531 if (saddr >= eaddr ||
1532 (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo)))
1535 saddr /= AMDGPU_GPU_PAGE_SIZE;
1536 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1538 it = interval_tree_iter_first(&vm->va, saddr, eaddr);
1540 struct amdgpu_bo_va_mapping *tmp;
1541 tmp = container_of(it, struct amdgpu_bo_va_mapping, it);
1542 /* bo and tmp overlap, invalid addr */
1543 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1544 "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr,
1545 tmp->it.start, tmp->it.last + 1);
1549 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1553 INIT_LIST_HEAD(&mapping->list);
1554 mapping->it.start = saddr;
1555 mapping->it.last = eaddr;
1556 mapping->offset = offset;
1557 mapping->flags = flags;
1559 list_add(&mapping->list, &bo_va->invalids);
1560 interval_tree_insert(&mapping->it, &vm->va);
1562 if (flags & AMDGPU_PTE_PRT)
1563 amdgpu_vm_prt_get(adev);
1569 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1571 * @adev: amdgpu_device pointer
1572 * @bo_va: bo_va to store the address
1573 * @saddr: where to map the BO
1574 * @offset: requested offset in the BO
1575 * @flags: attributes of pages (read/write/valid/etc.)
1577 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1578 * mappings as we do so.
1579 * Returns 0 for success, error for failure.
1581 * Object has to be reserved and unreserved outside!
1583 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1584 struct amdgpu_bo_va *bo_va,
1585 uint64_t saddr, uint64_t offset,
1586 uint64_t size, uint64_t flags)
1588 struct amdgpu_bo_va_mapping *mapping;
1589 struct amdgpu_vm *vm = bo_va->vm;
1593 /* validate the parameters */
1594 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1595 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1598 /* make sure object fit at this offset */
1599 eaddr = saddr + size - 1;
1600 if (saddr >= eaddr ||
1601 (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo)))
1604 /* Allocate all the needed memory */
1605 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1609 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size);
1615 saddr /= AMDGPU_GPU_PAGE_SIZE;
1616 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1618 mapping->it.start = saddr;
1619 mapping->it.last = eaddr;
1620 mapping->offset = offset;
1621 mapping->flags = flags;
1623 list_add(&mapping->list, &bo_va->invalids);
1624 interval_tree_insert(&mapping->it, &vm->va);
1626 if (flags & AMDGPU_PTE_PRT)
1627 amdgpu_vm_prt_get(adev);
1633 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1635 * @adev: amdgpu_device pointer
1636 * @bo_va: bo_va to remove the address from
1637 * @saddr: where to the BO is mapped
1639 * Remove a mapping of the BO at the specefied addr from the VM.
1640 * Returns 0 for success, error for failure.
1642 * Object has to be reserved and unreserved outside!
1644 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1645 struct amdgpu_bo_va *bo_va,
1648 struct amdgpu_bo_va_mapping *mapping;
1649 struct amdgpu_vm *vm = bo_va->vm;
1652 saddr /= AMDGPU_GPU_PAGE_SIZE;
1654 list_for_each_entry(mapping, &bo_va->valids, list) {
1655 if (mapping->it.start == saddr)
1659 if (&mapping->list == &bo_va->valids) {
1662 list_for_each_entry(mapping, &bo_va->invalids, list) {
1663 if (mapping->it.start == saddr)
1667 if (&mapping->list == &bo_va->invalids)
1671 list_del(&mapping->list);
1672 interval_tree_remove(&mapping->it, &vm->va);
1673 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1676 list_add(&mapping->list, &vm->freed);
1678 amdgpu_vm_free_mapping(adev, vm, mapping,
1679 bo_va->last_pt_update);
1685 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1687 * @adev: amdgpu_device pointer
1688 * @vm: VM structure to use
1689 * @saddr: start of the range
1690 * @size: size of the range
1692 * Remove all mappings in a range, split them as appropriate.
1693 * Returns 0 for success, error for failure.
1695 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1696 struct amdgpu_vm *vm,
1697 uint64_t saddr, uint64_t size)
1699 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1700 struct interval_tree_node *it;
1704 eaddr = saddr + size - 1;
1705 saddr /= AMDGPU_GPU_PAGE_SIZE;
1706 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1708 /* Allocate all the needed memory */
1709 before = kzalloc(sizeof(*before), GFP_KERNEL);
1712 INIT_LIST_HEAD(&before->list);
1714 after = kzalloc(sizeof(*after), GFP_KERNEL);
1719 INIT_LIST_HEAD(&after->list);
1721 /* Now gather all removed mappings */
1722 it = interval_tree_iter_first(&vm->va, saddr, eaddr);
1724 tmp = container_of(it, struct amdgpu_bo_va_mapping, it);
1725 it = interval_tree_iter_next(it, saddr, eaddr);
1727 /* Remember mapping split at the start */
1728 if (tmp->it.start < saddr) {
1729 before->it.start = tmp->it.start;
1730 before->it.last = saddr - 1;
1731 before->offset = tmp->offset;
1732 before->flags = tmp->flags;
1733 list_add(&before->list, &tmp->list);
1736 /* Remember mapping split at the end */
1737 if (tmp->it.last > eaddr) {
1738 after->it.start = eaddr + 1;
1739 after->it.last = tmp->it.last;
1740 after->offset = tmp->offset;
1741 after->offset += after->it.start - tmp->it.start;
1742 after->flags = tmp->flags;
1743 list_add(&after->list, &tmp->list);
1746 list_del(&tmp->list);
1747 list_add(&tmp->list, &removed);
1750 /* And free them up */
1751 list_for_each_entry_safe(tmp, next, &removed, list) {
1752 interval_tree_remove(&tmp->it, &vm->va);
1753 list_del(&tmp->list);
1755 if (tmp->it.start < saddr)
1756 tmp->it.start = saddr;
1757 if (tmp->it.last > eaddr)
1758 tmp->it.last = eaddr;
1760 list_add(&tmp->list, &vm->freed);
1761 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1764 /* Insert partial mapping before the range */
1765 if (!list_empty(&before->list)) {
1766 interval_tree_insert(&before->it, &vm->va);
1767 if (before->flags & AMDGPU_PTE_PRT)
1768 amdgpu_vm_prt_get(adev);
1773 /* Insert partial mapping after the range */
1774 if (!list_empty(&after->list)) {
1775 interval_tree_insert(&after->it, &vm->va);
1776 if (after->flags & AMDGPU_PTE_PRT)
1777 amdgpu_vm_prt_get(adev);
1786 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1788 * @adev: amdgpu_device pointer
1789 * @bo_va: requested bo_va
1791 * Remove @bo_va->bo from the requested vm.
1793 * Object have to be reserved!
1795 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1796 struct amdgpu_bo_va *bo_va)
1798 struct amdgpu_bo_va_mapping *mapping, *next;
1799 struct amdgpu_vm *vm = bo_va->vm;
1801 list_del(&bo_va->bo_list);
1803 spin_lock(&vm->status_lock);
1804 list_del(&bo_va->vm_status);
1805 spin_unlock(&vm->status_lock);
1807 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
1808 list_del(&mapping->list);
1809 interval_tree_remove(&mapping->it, &vm->va);
1810 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1811 list_add(&mapping->list, &vm->freed);
1813 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1814 list_del(&mapping->list);
1815 interval_tree_remove(&mapping->it, &vm->va);
1816 amdgpu_vm_free_mapping(adev, vm, mapping,
1817 bo_va->last_pt_update);
1820 dma_fence_put(bo_va->last_pt_update);
1825 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1827 * @adev: amdgpu_device pointer
1829 * @bo: amdgpu buffer object
1831 * Mark @bo as invalid.
1833 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1834 struct amdgpu_bo *bo)
1836 struct amdgpu_bo_va *bo_va;
1838 list_for_each_entry(bo_va, &bo->va, bo_list) {
1839 spin_lock(&bo_va->vm->status_lock);
1840 if (list_empty(&bo_va->vm_status))
1841 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
1842 spin_unlock(&bo_va->vm->status_lock);
1847 * amdgpu_vm_init - initialize a vm instance
1849 * @adev: amdgpu_device pointer
1854 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1856 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
1857 AMDGPU_VM_PTE_COUNT * 8);
1858 unsigned pd_size, pd_entries;
1859 unsigned ring_instance;
1860 struct amdgpu_ring *ring;
1861 struct amd_sched_rq *rq;
1864 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
1867 vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
1868 spin_lock_init(&vm->status_lock);
1869 INIT_LIST_HEAD(&vm->invalidated);
1870 INIT_LIST_HEAD(&vm->cleared);
1871 INIT_LIST_HEAD(&vm->freed);
1873 pd_size = amdgpu_vm_directory_size(adev);
1874 pd_entries = amdgpu_vm_num_pdes(adev);
1876 /* allocate page table array */
1877 vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt));
1878 if (vm->page_tables == NULL) {
1879 DRM_ERROR("Cannot allocate memory for page table array\n");
1883 /* create scheduler entity for page table updates */
1885 ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
1886 ring_instance %= adev->vm_manager.vm_pte_num_rings;
1887 ring = adev->vm_manager.vm_pte_rings[ring_instance];
1888 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
1889 r = amd_sched_entity_init(&ring->sched, &vm->entity,
1890 rq, amdgpu_sched_jobs);
1894 vm->page_directory_fence = NULL;
1896 r = amdgpu_bo_create(adev, pd_size, align, true,
1897 AMDGPU_GEM_DOMAIN_VRAM,
1898 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
1899 AMDGPU_GEM_CREATE_SHADOW |
1900 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
1901 AMDGPU_GEM_CREATE_VRAM_CLEARED,
1902 NULL, NULL, &vm->page_directory);
1904 goto error_free_sched_entity;
1906 r = amdgpu_bo_reserve(vm->page_directory, false);
1908 goto error_free_page_directory;
1910 vm->last_eviction_counter = atomic64_read(&adev->num_evictions);
1911 amdgpu_bo_unreserve(vm->page_directory);
1915 error_free_page_directory:
1916 amdgpu_bo_unref(&vm->page_directory->shadow);
1917 amdgpu_bo_unref(&vm->page_directory);
1918 vm->page_directory = NULL;
1920 error_free_sched_entity:
1921 amd_sched_entity_fini(&ring->sched, &vm->entity);
1924 drm_free_large(vm->page_tables);
1930 * amdgpu_vm_fini - tear down a vm instance
1932 * @adev: amdgpu_device pointer
1936 * Unbind the VM and remove all bos from the vm bo list
1938 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1940 struct amdgpu_bo_va_mapping *mapping, *tmp;
1941 bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt;
1944 amd_sched_entity_fini(vm->entity.sched, &vm->entity);
1946 if (!RB_EMPTY_ROOT(&vm->va)) {
1947 dev_err(adev->dev, "still active bo inside vm\n");
1949 rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) {
1950 list_del(&mapping->list);
1951 interval_tree_remove(&mapping->it, &vm->va);
1954 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
1955 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
1956 amdgpu_vm_prt_fini(adev, vm);
1957 prt_fini_needed = false;
1960 list_del(&mapping->list);
1961 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
1964 for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) {
1965 struct amdgpu_bo *pt = vm->page_tables[i].bo;
1970 amdgpu_bo_unref(&pt->shadow);
1971 amdgpu_bo_unref(&pt);
1973 drm_free_large(vm->page_tables);
1975 amdgpu_bo_unref(&vm->page_directory->shadow);
1976 amdgpu_bo_unref(&vm->page_directory);
1977 dma_fence_put(vm->page_directory_fence);
1981 * amdgpu_vm_manager_init - init the VM manager
1983 * @adev: amdgpu_device pointer
1985 * Initialize the VM manager structures
1987 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
1991 INIT_LIST_HEAD(&adev->vm_manager.ids_lru);
1993 /* skip over VMID 0, since it is the system VM */
1994 for (i = 1; i < adev->vm_manager.num_ids; ++i) {
1995 amdgpu_vm_reset_id(adev, i);
1996 amdgpu_sync_create(&adev->vm_manager.ids[i].active);
1997 list_add_tail(&adev->vm_manager.ids[i].list,
1998 &adev->vm_manager.ids_lru);
2001 adev->vm_manager.fence_context =
2002 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2003 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2004 adev->vm_manager.seqno[i] = 0;
2006 atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
2007 atomic64_set(&adev->vm_manager.client_counter, 0);
2008 spin_lock_init(&adev->vm_manager.prt_lock);
2009 atomic_set(&adev->vm_manager.num_prt_users, 0);
2013 * amdgpu_vm_manager_fini - cleanup VM manager
2015 * @adev: amdgpu_device pointer
2017 * Cleanup the VM manager and free resources.
2019 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2023 for (i = 0; i < AMDGPU_NUM_VM; ++i) {
2024 struct amdgpu_vm_id *id = &adev->vm_manager.ids[i];
2026 dma_fence_put(adev->vm_manager.ids[i].first);
2027 amdgpu_sync_free(&adev->vm_manager.ids[i].active);
2028 dma_fence_put(id->flushed_updates);
2029 dma_fence_put(id->last_flush);