2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/module.h>
27 #include <asm/hypervisor.h>
30 #include <drm/drm_drv.h>
34 #include "amdgpu_ras.h"
39 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \
41 vf2pf_info->ucode_info[ucode].id = ucode; \
42 vf2pf_info->ucode_info[ucode].version = ver; \
45 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
47 /* By now all MMIO pages except mailbox are blocked */
48 /* if blocking is enabled in hypervisor. Choose the */
49 /* SCRATCH_REG0 to test. */
50 return RREG32_NO_KIQ(0xc040) == 0xffffffff;
53 void amdgpu_virt_init_setting(struct amdgpu_device *adev)
55 struct drm_device *ddev = adev_to_drm(adev);
57 /* enable virtual display */
58 if (adev->asic_type != CHIP_ALDEBARAN &&
59 adev->asic_type != CHIP_ARCTURUS) {
60 if (adev->mode_info.num_crtc == 0)
61 adev->mode_info.num_crtc = 1;
62 adev->enable_virtual_display = true;
64 ddev->driver_features &= ~DRIVER_ATOMIC;
68 /* enable mcbp for sriov asic_type before soc21 */
69 amdgpu_mcbp = (adev->asic_type < CHIP_IP_DISCOVERY) ? 1 : 0;
73 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
74 uint32_t reg0, uint32_t reg1,
75 uint32_t ref, uint32_t mask)
77 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
78 struct amdgpu_ring *ring = &kiq->ring;
79 signed long r, cnt = 0;
83 if (adev->mes.ring.sched.ready) {
84 amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1,
89 spin_lock_irqsave(&kiq->ring_lock, flags);
90 amdgpu_ring_alloc(ring, 32);
91 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
93 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
97 amdgpu_ring_commit(ring);
98 spin_unlock_irqrestore(&kiq->ring_lock, flags);
100 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
102 /* don't wait anymore for IRQ context */
103 if (r < 1 && in_interrupt())
107 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
109 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
110 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
113 if (cnt > MAX_KIQ_REG_TRY)
119 amdgpu_ring_undo(ring);
120 spin_unlock_irqrestore(&kiq->ring_lock, flags);
122 dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1);
126 * amdgpu_virt_request_full_gpu() - request full gpu access
127 * @adev: amdgpu device.
128 * @init: is driver init time.
129 * When start to init/fini driver, first need to request full gpu access.
130 * Return: Zero if request success, otherwise will return error.
132 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
134 struct amdgpu_virt *virt = &adev->virt;
137 if (virt->ops && virt->ops->req_full_gpu) {
138 r = virt->ops->req_full_gpu(adev, init);
142 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
149 * amdgpu_virt_release_full_gpu() - release full gpu access
150 * @adev: amdgpu device.
151 * @init: is driver init time.
152 * When finishing driver init/fini, need to release full gpu access.
153 * Return: Zero if release success, otherwise will returen error.
155 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
157 struct amdgpu_virt *virt = &adev->virt;
160 if (virt->ops && virt->ops->rel_full_gpu) {
161 r = virt->ops->rel_full_gpu(adev, init);
165 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
171 * amdgpu_virt_reset_gpu() - reset gpu
172 * @adev: amdgpu device.
173 * Send reset command to GPU hypervisor to reset GPU that VM is using
174 * Return: Zero if reset success, otherwise will return error.
176 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
178 struct amdgpu_virt *virt = &adev->virt;
181 if (virt->ops && virt->ops->reset_gpu) {
182 r = virt->ops->reset_gpu(adev);
186 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
192 void amdgpu_virt_request_init_data(struct amdgpu_device *adev)
194 struct amdgpu_virt *virt = &adev->virt;
196 if (virt->ops && virt->ops->req_init_data)
197 virt->ops->req_init_data(adev);
199 if (adev->virt.req_init_data_ver > 0)
200 DRM_INFO("host supports REQ_INIT_DATA handshake\n");
202 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n");
206 * amdgpu_virt_wait_reset() - wait for reset gpu completed
207 * @adev: amdgpu device.
208 * Wait for GPU reset completed.
209 * Return: Zero if reset success, otherwise will return error.
211 int amdgpu_virt_wait_reset(struct amdgpu_device *adev)
213 struct amdgpu_virt *virt = &adev->virt;
215 if (!virt->ops || !virt->ops->wait_reset)
218 return virt->ops->wait_reset(adev);
222 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table
223 * @adev: amdgpu device.
224 * MM table is used by UVD and VCE for its initialization
225 * Return: Zero if allocate success.
227 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
231 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)
234 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
235 AMDGPU_GEM_DOMAIN_VRAM |
236 AMDGPU_GEM_DOMAIN_GTT,
237 &adev->virt.mm_table.bo,
238 &adev->virt.mm_table.gpu_addr,
239 (void *)&adev->virt.mm_table.cpu_addr);
241 DRM_ERROR("failed to alloc mm table and error = %d.\n", r);
245 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);
246 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n",
247 adev->virt.mm_table.gpu_addr,
248 adev->virt.mm_table.cpu_addr);
253 * amdgpu_virt_free_mm_table() - free mm table memory
254 * @adev: amdgpu device.
255 * Free MM table memory
257 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
259 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)
262 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
263 &adev->virt.mm_table.gpu_addr,
264 (void *)&adev->virt.mm_table.cpu_addr);
265 adev->virt.mm_table.gpu_addr = 0;
269 unsigned int amd_sriov_msg_checksum(void *obj,
270 unsigned long obj_size,
272 unsigned int checksum)
274 unsigned int ret = key;
279 /* calculate checksum */
280 for (i = 0; i < obj_size; ++i)
282 /* minus the checksum itself */
283 pos = (char *)&checksum;
284 for (i = 0; i < sizeof(checksum); ++i)
289 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev)
291 struct amdgpu_virt *virt = &adev->virt;
292 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data;
293 /* GPU will be marked bad on host if bp count more then 10,
294 * so alloc 512 is enough.
296 unsigned int align_space = 512;
298 struct amdgpu_bo **bps_bo = NULL;
300 *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL);
304 bps = kmalloc_array(align_space, sizeof((*data)->bps), GFP_KERNEL);
308 bps_bo = kmalloc_array(align_space, sizeof((*data)->bps_bo), GFP_KERNEL);
313 (*data)->bps_bo = bps_bo;
315 (*data)->last_reserved = 0;
317 virt->ras_init_done = true;
329 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev)
331 struct amdgpu_virt *virt = &adev->virt;
332 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
333 struct amdgpu_bo *bo;
339 for (i = data->last_reserved - 1; i >= 0; i--) {
340 bo = data->bps_bo[i];
341 amdgpu_bo_free_kernel(&bo, NULL, NULL);
342 data->bps_bo[i] = bo;
343 data->last_reserved = i;
347 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev)
349 struct amdgpu_virt *virt = &adev->virt;
350 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
352 virt->ras_init_done = false;
357 amdgpu_virt_ras_release_bp(adev);
362 virt->virt_eh_data = NULL;
365 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev,
366 struct eeprom_table_record *bps, int pages)
368 struct amdgpu_virt *virt = &adev->virt;
369 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
374 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps));
375 data->count += pages;
378 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev)
380 struct amdgpu_virt *virt = &adev->virt;
381 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
382 struct amdgpu_bo *bo = NULL;
389 for (i = data->last_reserved; i < data->count; i++) {
390 bp = data->bps[i].retired_page;
392 /* There are two cases of reserve error should be ignored:
393 * 1) a ras bad page has been allocated (used by someone);
394 * 2) a ras bad page has been reserved (duplicate error injection
397 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,
398 AMDGPU_GPU_PAGE_SIZE,
400 DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp);
402 data->bps_bo[i] = bo;
403 data->last_reserved = i + 1;
408 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev,
409 uint64_t retired_page)
411 struct amdgpu_virt *virt = &adev->virt;
412 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data;
418 for (i = 0; i < data->count; i++)
419 if (retired_page == data->bps[i].retired_page)
425 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev,
426 uint64_t bp_block_offset, uint32_t bp_block_size)
428 struct eeprom_table_record bp;
429 uint64_t retired_page;
430 uint32_t bp_idx, bp_cnt;
431 void *vram_usage_va = NULL;
433 if (adev->mman.fw_vram_usage_va)
434 vram_usage_va = adev->mman.fw_vram_usage_va;
436 vram_usage_va = adev->mman.drv_vram_usage_va;
439 bp_cnt = bp_block_size / sizeof(uint64_t);
440 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) {
441 retired_page = *(uint64_t *)(vram_usage_va +
442 bp_block_offset + bp_idx * sizeof(uint64_t));
443 bp.retired_page = retired_page;
445 if (amdgpu_virt_ras_check_bad_page(adev, retired_page))
448 amdgpu_virt_ras_add_bps(adev, &bp, 1);
450 amdgpu_virt_ras_reserve_bps(adev);
455 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)
457 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf;
464 if (adev->virt.fw_reserve.p_pf2vf == NULL)
467 if (pf2vf_info->size > 1024) {
468 DRM_ERROR("invalid pf2vf message size\n");
472 switch (pf2vf_info->version) {
474 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum;
475 checkval = amd_sriov_msg_checksum(
476 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
477 adev->virt.fw_reserve.checksum_key, checksum);
478 if (checksum != checkval) {
479 DRM_ERROR("invalid pf2vf message\n");
483 adev->virt.gim_feature =
484 ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags;
487 /* TODO: missing key, need to add it later */
488 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum;
489 checkval = amd_sriov_msg_checksum(
490 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,
492 if (checksum != checkval) {
493 DRM_ERROR("invalid pf2vf message\n");
497 adev->virt.vf2pf_update_interval_ms =
498 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms;
499 adev->virt.gim_feature =
500 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all;
501 adev->virt.reg_access =
502 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all;
504 adev->virt.decode_max_dimension_pixels = 0;
505 adev->virt.decode_max_frame_pixels = 0;
506 adev->virt.encode_max_dimension_pixels = 0;
507 adev->virt.encode_max_frame_pixels = 0;
508 adev->virt.is_mm_bw_enabled = false;
509 for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) {
510 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels;
511 adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels);
513 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels;
514 adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels);
516 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels;
517 adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels);
519 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels;
520 adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels);
522 if((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0))
523 adev->virt.is_mm_bw_enabled = true;
526 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid;
529 DRM_ERROR("invalid pf2vf version\n");
533 /* correct too large or too little interval value */
534 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000)
535 adev->virt.vf2pf_update_interval_ms = 2000;
540 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev)
542 struct amd_sriov_msg_vf2pf_info *vf2pf_info;
543 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;
545 if (adev->virt.fw_reserve.p_vf2pf == NULL)
548 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version);
549 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version);
550 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version);
551 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version);
552 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version);
553 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version);
554 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version);
555 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version);
556 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version);
557 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);
558 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version);
559 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version);
560 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_IMU, adev->gfx.imu_fw_version);
561 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version);
562 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD,
563 adev->psp.asd_context.bin_desc.fw_version);
564 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS,
565 adev->psp.ras_context.context.bin_desc.fw_version);
566 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI,
567 adev->psp.xgmi_context.context.bin_desc.fw_version);
568 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version);
569 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version);
570 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version);
571 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version);
572 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version);
575 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev)
577 struct amd_sriov_msg_vf2pf_info *vf2pf_info;
579 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;
581 if (adev->virt.fw_reserve.p_vf2pf == NULL)
584 memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info));
586 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info);
587 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER;
590 if (THIS_MODULE->version != NULL)
591 strcpy(vf2pf_info->driver_version, THIS_MODULE->version);
594 strcpy(vf2pf_info->driver_version, "N/A");
596 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all
597 vf2pf_info->driver_cert = 0;
598 vf2pf_info->os_info.all = 0;
600 vf2pf_info->fb_usage =
601 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20;
602 vf2pf_info->fb_vis_usage =
603 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20;
604 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20;
605 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20;
607 amdgpu_virt_populate_vf2pf_ucode_info(adev);
609 /* TODO: read dynamic info */
610 vf2pf_info->gfx_usage = 0;
611 vf2pf_info->compute_usage = 0;
612 vf2pf_info->encode_usage = 0;
613 vf2pf_info->decode_usage = 0;
615 vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr;
616 vf2pf_info->checksum =
617 amd_sriov_msg_checksum(
618 vf2pf_info, vf2pf_info->header.size, 0, 0);
623 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work)
625 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work);
628 ret = amdgpu_virt_read_pf2vf_data(adev);
631 amdgpu_virt_write_vf2pf_data(adev);
634 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);
637 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev)
639 if (adev->virt.vf2pf_update_interval_ms != 0) {
640 DRM_INFO("clean up the vf2pf work item\n");
641 cancel_delayed_work_sync(&adev->virt.vf2pf_work);
642 adev->virt.vf2pf_update_interval_ms = 0;
646 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
648 adev->virt.fw_reserve.p_pf2vf = NULL;
649 adev->virt.fw_reserve.p_vf2pf = NULL;
650 adev->virt.vf2pf_update_interval_ms = 0;
652 if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) {
653 DRM_WARN("Currently fw_vram and drv_vram should not have values at the same time!");
654 } else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) {
655 /* go through this logic in ip_init and reset to init workqueue*/
656 amdgpu_virt_exchange_data(adev);
658 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);
659 schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms));
660 } else if (adev->bios != NULL) {
661 /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/
662 adev->virt.fw_reserve.p_pf2vf =
663 (struct amd_sriov_msg_pf2vf_info_header *)
664 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
666 amdgpu_virt_read_pf2vf_data(adev);
671 void amdgpu_virt_exchange_data(struct amdgpu_device *adev)
673 uint64_t bp_block_offset = 0;
674 uint32_t bp_block_size = 0;
675 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL;
677 if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) {
678 if (adev->mman.fw_vram_usage_va) {
679 adev->virt.fw_reserve.p_pf2vf =
680 (struct amd_sriov_msg_pf2vf_info_header *)
681 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
682 adev->virt.fw_reserve.p_vf2pf =
683 (struct amd_sriov_msg_vf2pf_info_header *)
684 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
685 } else if (adev->mman.drv_vram_usage_va) {
686 adev->virt.fw_reserve.p_pf2vf =
687 (struct amd_sriov_msg_pf2vf_info_header *)
688 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
689 adev->virt.fw_reserve.p_vf2pf =
690 (struct amd_sriov_msg_vf2pf_info_header *)
691 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));
694 amdgpu_virt_read_pf2vf_data(adev);
695 amdgpu_virt_write_vf2pf_data(adev);
697 /* bad page handling for version 2 */
698 if (adev->virt.fw_reserve.p_pf2vf->version == 2) {
699 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf;
701 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) |
702 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000);
703 bp_block_size = pf2vf_v2->bp_block_size;
705 if (bp_block_size && !adev->virt.ras_init_done)
706 amdgpu_virt_init_ras_err_handler_data(adev);
708 if (adev->virt.ras_init_done)
709 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);
714 void amdgpu_detect_virtualization(struct amdgpu_device *adev)
718 switch (adev->asic_type) {
721 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
727 case CHIP_SIENNA_CICHLID:
730 case CHIP_IP_DISCOVERY:
731 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);
733 default: /* other chip doesn't support SRIOV */
739 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
741 if (reg & 0x80000000)
742 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
745 /* passthrough mode exclus sriov mod */
746 if (is_virtual_machine() && !xen_initial_domain())
747 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
750 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
751 /* VF MMIO access (except mailbox range) from CPU
752 * will be blocked during sriov runtime
754 adev->virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT;
756 /* we have the ability to check now */
757 if (amdgpu_sriov_vf(adev)) {
758 switch (adev->asic_type) {
761 vi_set_virt_ops(adev);
764 soc15_set_virt_ops(adev);
766 /* not send GPU_INIT_DATA with MS_HYPERV*/
767 if (!hypervisor_is_type(X86_HYPER_MS_HYPERV))
769 /* send a dummy GPU_INIT_DATA request to host on vega10 */
770 amdgpu_virt_request_init_data(adev);
775 soc15_set_virt_ops(adev);
779 case CHIP_SIENNA_CICHLID:
780 case CHIP_IP_DISCOVERY:
781 nv_set_virt_ops(adev);
782 /* try send GPU_INIT_DATA request to host */
783 amdgpu_virt_request_init_data(adev);
785 default: /* other chip doesn't support SRIOV */
786 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type);
792 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
794 return amdgpu_sriov_is_debug(adev) ? true : false;
797 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
799 return amdgpu_sriov_is_normal(adev) ? true : false;
802 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev)
804 if (!amdgpu_sriov_vf(adev) ||
805 amdgpu_virt_access_debugfs_is_kiq(adev))
808 if (amdgpu_virt_access_debugfs_is_mmio(adev))
809 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
816 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev)
818 if (amdgpu_sriov_vf(adev))
819 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
822 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev)
824 enum amdgpu_sriov_vf_mode mode;
826 if (amdgpu_sriov_vf(adev)) {
827 if (amdgpu_sriov_is_pp_one_vf(adev))
828 mode = SRIOV_VF_MODE_ONE_VF;
830 mode = SRIOV_VF_MODE_MULTI_VF;
832 mode = SRIOV_VF_MODE_BARE_METAL;
838 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)
840 switch (adev->ip_versions[MP0_HWIP][0]) {
841 case IP_VERSION(13, 0, 0):
842 /* no vf autoload, white list */
843 if (ucode_id == AMDGPU_UCODE_ID_VCN1 ||
844 ucode_id == AMDGPU_UCODE_ID_VCN)
848 case IP_VERSION(13, 0, 10):
850 if (ucode_id == AMDGPU_UCODE_ID_CAP
851 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP
852 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME
853 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC
854 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK
855 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK
856 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK
857 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK
858 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK
859 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK
860 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK
861 || ucode_id == AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK
862 || ucode_id == AMDGPU_UCODE_ID_CP_MES
863 || ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA
864 || ucode_id == AMDGPU_UCODE_ID_CP_MES1
865 || ucode_id == AMDGPU_UCODE_ID_CP_MES1_DATA
866 || ucode_id == AMDGPU_UCODE_ID_VCN1
867 || ucode_id == AMDGPU_UCODE_ID_VCN)
872 /* lagacy black list */
873 if (ucode_id == AMDGPU_UCODE_ID_SDMA0
874 || ucode_id == AMDGPU_UCODE_ID_SDMA1
875 || ucode_id == AMDGPU_UCODE_ID_SDMA2
876 || ucode_id == AMDGPU_UCODE_ID_SDMA3
877 || ucode_id == AMDGPU_UCODE_ID_SDMA4
878 || ucode_id == AMDGPU_UCODE_ID_SDMA5
879 || ucode_id == AMDGPU_UCODE_ID_SDMA6
880 || ucode_id == AMDGPU_UCODE_ID_SDMA7
881 || ucode_id == AMDGPU_UCODE_ID_RLC_G
882 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
883 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
884 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
885 || ucode_id == AMDGPU_UCODE_ID_SMC)
892 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
893 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
894 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size)
898 if (!adev->virt.is_mm_bw_enabled)
902 for (i = 0; i < encode_array_size; i++) {
903 encode[i].max_width = adev->virt.encode_max_dimension_pixels;
904 encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels;
905 if (encode[i].max_width > 0)
906 encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width;
908 encode[i].max_height = 0;
913 for (i = 0; i < decode_array_size; i++) {
914 decode[i].max_width = adev->virt.decode_max_dimension_pixels;
915 decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels;
916 if (decode[i].max_width > 0)
917 decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width;
919 decode[i].max_height = 0;
924 static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
925 u32 acc_flags, u32 hwip,
926 bool write, u32 *rlcg_flag)
932 if (amdgpu_sriov_reg_indirect_gc(adev)) {
934 write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ;
936 /* only in new version, AMDGPU_REGS_NO_KIQ and
937 * AMDGPU_REGS_RLC are enabled simultaneously */
938 } else if ((acc_flags & AMDGPU_REGS_RLC) &&
939 !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) {
940 *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY;
945 if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
946 (acc_flags & AMDGPU_REGS_RLC) && write) {
947 *rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE;
957 static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
959 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
960 uint32_t timeout = 50000;
969 if (!adev->gfx.rlc.rlcg_reg_access_supported) {
971 "indirect registers access through rlcg is not available\n");
975 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
976 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0;
977 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1;
978 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2;
979 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3;
980 if (reg_access_ctrl->spare_int)
981 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int;
983 if (offset == reg_access_ctrl->grbm_cntl) {
984 /* if the target reg offset is grbm_cntl, write to scratch_reg2 */
985 writel(v, scratch_reg2);
986 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY)
987 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
988 } else if (offset == reg_access_ctrl->grbm_idx) {
989 /* if the target reg offset is grbm_idx, write to scratch_reg3 */
990 writel(v, scratch_reg3);
991 if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY)
992 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
995 * SCRATCH_REG0 = read/write value
996 * SCRATCH_REG1[30:28] = command
997 * SCRATCH_REG1[19:0] = address in dword
998 * SCRATCH_REG1[26:24] = Error reporting
1000 writel(v, scratch_reg0);
1001 writel((offset | flag), scratch_reg1);
1002 if (reg_access_ctrl->spare_int)
1003 writel(1, spare_int);
1005 for (i = 0; i < timeout; i++) {
1006 tmp = readl(scratch_reg1);
1007 if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK))
1013 if (amdgpu_sriov_rlcg_error_report_enabled(adev)) {
1014 if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) {
1016 "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset);
1017 } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) {
1019 "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset);
1020 } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) {
1022 "register is not in range, rlcg failed to program reg: 0x%05x\n", offset);
1025 "unknown error type, rlcg failed to program reg: 0x%05x\n", offset);
1029 "timeout: rlcg faled to program reg: 0x%05x\n", offset);
1034 ret = readl(scratch_reg0);
1038 void amdgpu_sriov_wreg(struct amdgpu_device *adev,
1039 u32 offset, u32 value,
1040 u32 acc_flags, u32 hwip)
1044 if (!amdgpu_sriov_runtime(adev) &&
1045 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) {
1046 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag);
1050 if (acc_flags & AMDGPU_REGS_NO_KIQ)
1051 WREG32_NO_KIQ(offset, value);
1053 WREG32(offset, value);
1056 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
1057 u32 offset, u32 acc_flags, u32 hwip)
1061 if (!amdgpu_sriov_runtime(adev) &&
1062 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag))
1063 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag);
1065 if (acc_flags & AMDGPU_REGS_NO_KIQ)
1066 return RREG32_NO_KIQ(offset);
1068 return RREG32(offset);