drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26
  27 #include <linux/firmware.h>
  28 #include <linux/module.h>
  29 #include <linux/dmi.h>
  30 #include <linux/pci.h>
  31 #include <linux/debugfs.h>
  32 #include <drm/drm_drv.h>
  33
  34 #include "amdgpu.h"
  35 #include "amdgpu_pm.h"
  36 #include "amdgpu_vcn.h"
  37 #include "soc15d.h"
  38
  39 /* Firmware Names */
  40 #define FIRMWARE_RAVEN                  "amdgpu/raven_vcn.bin"
  41 #define FIRMWARE_PICASSO                "amdgpu/picasso_vcn.bin"
  42 #define FIRMWARE_RAVEN2                 "amdgpu/raven2_vcn.bin"
  43 #define FIRMWARE_ARCTURUS               "amdgpu/arcturus_vcn.bin"
  44 #define FIRMWARE_RENOIR                 "amdgpu/renoir_vcn.bin"
  45 #define FIRMWARE_GREEN_SARDINE          "amdgpu/green_sardine_vcn.bin"
  46 #define FIRMWARE_NAVI10                 "amdgpu/navi10_vcn.bin"
  47 #define FIRMWARE_NAVI14                 "amdgpu/navi14_vcn.bin"
  48 #define FIRMWARE_NAVI12                 "amdgpu/navi12_vcn.bin"
  49 #define FIRMWARE_SIENNA_CICHLID         "amdgpu/sienna_cichlid_vcn.bin"
  50 #define FIRMWARE_NAVY_FLOUNDER          "amdgpu/navy_flounder_vcn.bin"
  51 #define FIRMWARE_VANGOGH                "amdgpu/vangogh_vcn.bin"
  52 #define FIRMWARE_DIMGREY_CAVEFISH       "amdgpu/dimgrey_cavefish_vcn.bin"
  53 #define FIRMWARE_ALDEBARAN              "amdgpu/aldebaran_vcn.bin"
  54 #define FIRMWARE_BEIGE_GOBY             "amdgpu/beige_goby_vcn.bin"
  55 #define FIRMWARE_YELLOW_CARP            "amdgpu/yellow_carp_vcn.bin"
  56 #define FIRMWARE_VCN_3_1_2              "amdgpu/vcn_3_1_2.bin"
  57 #define FIRMWARE_VCN4_0_0               "amdgpu/vcn_4_0_0.bin"
  58 #define FIRMWARE_VCN4_0_2               "amdgpu/vcn_4_0_2.bin"
  59 #define FIRMWARE_VCN4_0_3               "amdgpu/vcn_4_0_3.bin"
  60 #define FIRMWARE_VCN4_0_4               "amdgpu/vcn_4_0_4.bin"
  61
  62 MODULE_FIRMWARE(FIRMWARE_RAVEN);
  63 MODULE_FIRMWARE(FIRMWARE_PICASSO);
  64 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
  65 MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
  66 MODULE_FIRMWARE(FIRMWARE_RENOIR);
  67 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
  68 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN);
  69 MODULE_FIRMWARE(FIRMWARE_NAVI10);
  70 MODULE_FIRMWARE(FIRMWARE_NAVI14);
  71 MODULE_FIRMWARE(FIRMWARE_NAVI12);
  72 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
  73 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
  74 MODULE_FIRMWARE(FIRMWARE_VANGOGH);
  75 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
  76 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
  77 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
  78 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2);
  79 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0);
  80 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2);
  81 MODULE_FIRMWARE(FIRMWARE_VCN4_0_3);
  82 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4);
  83
  84 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
  85
  86 int amdgpu_vcn_early_init(struct amdgpu_device *adev)
  87 {
  88         char ucode_prefix[30];
  89         char fw_name[40];
  90         int r;
  91
  92         amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));
  93         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
  94         r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name);
  95         if (r)
  96                 amdgpu_ucode_release(&adev->vcn.fw);
  97
  98         return r;
  99 }
 100
 101 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 102 {
 103         unsigned long bo_size;
 104         const struct common_firmware_header *hdr;
 105         unsigned char fw_check;
 106         unsigned int fw_shared_size, log_offset;
 107         int i, r;
 108
 109         INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
 110         mutex_init(&adev->vcn.vcn_pg_lock);
 111         mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
 112         atomic_set(&adev->vcn.total_submission_cnt, 0);
 113         for (i = 0; i < adev->vcn.num_vcn_inst; i++)
 114                 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
 115
 116         switch (adev->ip_versions[UVD_HWIP][0]) {
 117         case IP_VERSION(4, 0, 3):
 118                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 119                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 120                         adev->vcn.indirect_sram = false;
 121                 break;
 122         default:
 123                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 124                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 125                         adev->vcn.indirect_sram = true;
 126                 break;
 127         }
 128
 129         /*
 130          * Some Steam Deck's BIOS versions are incompatible with the
 131          * indirect SRAM mode, leading to amdgpu being unable to get
 132          * properly probed (and even potentially crashing the kernel).
 133          * Hence, check for these versions here - notice this is
 134          * restricted to Vangogh (Deck's APU).
 135          */
 136         if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 2)) {
 137                 const char *bios_ver = dmi_get_system_info(DMI_BIOS_VERSION);
 138
 139                 if (bios_ver && (!strncmp("F7A0113", bios_ver, 7) ||
 140                      !strncmp("F7A0114", bios_ver, 7))) {
 141                         adev->vcn.indirect_sram = false;
 142                         dev_info(adev->dev,
 143                                 "Steam Deck quirk: indirect SRAM disabled on BIOS %s\n", bios_ver);
 144                 }
 145         }
 146
 147         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 148         adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
 149
 150         /* Bit 20-23, it is encode major and non-zero for new naming convention.
 151          * This field is part of version minor and DRM_DISABLED_FLAG in old naming
 152          * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
 153          * is zero in old naming convention, this field is always zero so far.
 154          * These four bits are used to tell which naming convention is present.
 155          */
 156         fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
 157         if (fw_check) {
 158                 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
 159
 160                 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
 161                 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
 162                 enc_major = fw_check;
 163                 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
 164                 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
 165                 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n",
 166                         enc_major, enc_minor, dec_ver, vep, fw_rev);
 167         } else {
 168                 unsigned int version_major, version_minor, family_id;
 169
 170                 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 171                 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 172                 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 173                 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n",
 174                         version_major, version_minor, family_id);
 175         }
 176
 177         bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
 178         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 179                 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 180
 181         if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)){
 182                 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared));
 183                 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log);
 184         } else {
 185                 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
 186                 log_offset = offsetof(struct amdgpu_fw_shared, fw_log);
 187         }
 188
 189         bo_size += fw_shared_size;
 190
 191         if (amdgpu_vcnfw_log)
 192                 bo_size += AMDGPU_VCNFW_LOG_SIZE;
 193
 194         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 195                 if (adev->vcn.harvest_config & (1 << i))
 196                         continue;
 197
 198                 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 199                                             AMDGPU_GEM_DOMAIN_VRAM |
 200                                             AMDGPU_GEM_DOMAIN_GTT,
 201                                             &adev->vcn.inst[i].vcpu_bo,
 202                                             &adev->vcn.inst[i].gpu_addr,
 203                                             &adev->vcn.inst[i].cpu_addr);
 204                 if (r) {
 205                         dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
 206                         return r;
 207                 }
 208
 209                 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +
 210                                 bo_size - fw_shared_size;
 211                 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +
 212                                 bo_size - fw_shared_size;
 213
 214                 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;
 215
 216                 if (amdgpu_vcnfw_log) {
 217                         adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
 218                         adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
 219                         adev->vcn.inst[i].fw_shared.log_offset = log_offset;
 220                 }
 221
 222                 if (adev->vcn.indirect_sram) {
 223                         r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
 224                                         AMDGPU_GEM_DOMAIN_VRAM |
 225                                         AMDGPU_GEM_DOMAIN_GTT,
 226                                         &adev->vcn.inst[i].dpg_sram_bo,
 227                                         &adev->vcn.inst[i].dpg_sram_gpu_addr,
 228                                         &adev->vcn.inst[i].dpg_sram_cpu_addr);
 229                         if (r) {
 230                                 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
 231                                 return r;
 232                         }
 233                 }
 234         }
 235
 236         return 0;
 237 }
 238
 239 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 240 {
 241         int i, j;
 242
 243         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 244                 if (adev->vcn.harvest_config & (1 << j))
 245                         continue;
 246
 247                 if (adev->vcn.indirect_sram) {
 248                         amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo,
 249                                                   &adev->vcn.inst[j].dpg_sram_gpu_addr,
 250                                                   (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
 251                 }
 252                 kvfree(adev->vcn.inst[j].saved_bo);
 253
 254                 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
 255                                           &adev->vcn.inst[j].gpu_addr,
 256                                           (void **)&adev->vcn.inst[j].cpu_addr);
 257
 258                 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
 259
 260                 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 261                         amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
 262         }
 263
 264         amdgpu_ucode_release(&adev->vcn.fw);
 265         mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
 266         mutex_destroy(&adev->vcn.vcn_pg_lock);
 267
 268         return 0;
 269 }
 270
 271 /* from vcn4 and above, only unified queue is used */
 272 static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring)
 273 {
 274         struct amdgpu_device *adev = ring->adev;
 275         bool ret = false;
 276
 277         if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0))
 278                 ret = true;
 279
 280         return ret;
 281 }
 282
 283 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
 284 {
 285         bool ret = false;
 286         int vcn_config = adev->vcn.vcn_config[vcn_instance];
 287
 288         if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) {
 289                 ret = true;
 290         } else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) {
 291                 ret = true;
 292         } else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) {
 293                 ret = true;
 294         }
 295
 296         return ret;
 297 }
 298
 299 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 300 {
 301         unsigned size;
 302         void *ptr;
 303         int i, idx;
 304
 305         cancel_delayed_work_sync(&adev->vcn.idle_work);
 306
 307         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 308                 if (adev->vcn.harvest_config & (1 << i))
 309                         continue;
 310                 if (adev->vcn.inst[i].vcpu_bo == NULL)
 311                         return 0;
 312
 313                 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
 314                 ptr = adev->vcn.inst[i].cpu_addr;
 315
 316                 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
 317                 if (!adev->vcn.inst[i].saved_bo)
 318                         return -ENOMEM;
 319
 320                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 321                         memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
 322                         drm_dev_exit(idx);
 323                 }
 324         }
 325         return 0;
 326 }
 327
 328 int amdgpu_vcn_resume(struct amdgpu_device *adev)
 329 {
 330         unsigned size;
 331         void *ptr;
 332         int i, idx;
 333
 334         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 335                 if (adev->vcn.harvest_config & (1 << i))
 336                         continue;
 337                 if (adev->vcn.inst[i].vcpu_bo == NULL)
 338                         return -EINVAL;
 339
 340                 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
 341                 ptr = adev->vcn.inst[i].cpu_addr;
 342
 343                 if (adev->vcn.inst[i].saved_bo != NULL) {
 344                         if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 345                                 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
 346                                 drm_dev_exit(idx);
 347                         }
 348                         kvfree(adev->vcn.inst[i].saved_bo);
 349                         adev->vcn.inst[i].saved_bo = NULL;
 350                 } else {
 351                         const struct common_firmware_header *hdr;
 352                         unsigned offset;
 353
 354                         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 355                         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 356                                 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 357                                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 358                                         memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
 359                                                     le32_to_cpu(hdr->ucode_size_bytes));
 360                                         drm_dev_exit(idx);
 361                                 }
 362                                 size -= le32_to_cpu(hdr->ucode_size_bytes);
 363                                 ptr += le32_to_cpu(hdr->ucode_size_bytes);
 364                         }
 365                         memset_io(ptr, 0, size);
 366                 }
 367         }
 368         return 0;
 369 }
 370
 371 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 372 {
 373         struct amdgpu_device *adev =
 374                 container_of(work, struct amdgpu_device, vcn.idle_work.work);
 375         unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
 376         unsigned int i, j;
 377         int r = 0;
 378
 379         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 380                 if (adev->vcn.harvest_config & (1 << j))
 381                         continue;
 382
 383                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 384                         fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
 385                 }
 386
 387                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
 388                         struct dpg_pause_state new_state;
 389
 390                         if (fence[j] ||
 391                                 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
 392                                 new_state.fw_based = VCN_DPG_STATE__PAUSE;
 393                         else
 394                                 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 395
 396                         adev->vcn.pause_dpg_mode(adev, j, &new_state);
 397                 }
 398
 399                 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
 400                 fences += fence[j];
 401         }
 402
 403         if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
 404                 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 405                        AMD_PG_STATE_GATE);
 406                 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
 407                                 false);
 408                 if (r)
 409                         dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
 410         } else {
 411                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 412         }
 413 }
 414
 415 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 416 {
 417         struct amdgpu_device *adev = ring->adev;
 418         int r = 0;
 419
 420         atomic_inc(&adev->vcn.total_submission_cnt);
 421
 422         if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
 423                 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
 424                                 true);
 425                 if (r)
 426                         dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r);
 427         }
 428
 429         mutex_lock(&adev->vcn.vcn_pg_lock);
 430         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 431                AMD_PG_STATE_UNGATE);
 432
 433         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
 434                 struct dpg_pause_state new_state;
 435
 436                 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {
 437                         atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
 438                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
 439                 } else {
 440                         unsigned int fences = 0;
 441                         unsigned int i;
 442
 443                         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 444                                 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
 445
 446                         if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt))
 447                                 new_state.fw_based = VCN_DPG_STATE__PAUSE;
 448                         else
 449                                 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 450                 }
 451
 452                 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
 453         }
 454         mutex_unlock(&adev->vcn.vcn_pg_lock);
 455 }
 456
 457 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
 458 {
 459         if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
 460                 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
 461                 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
 462
 463         atomic_dec(&ring->adev->vcn.total_submission_cnt);
 464
 465         schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 466 }
 467
 468 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
 469 {
 470         struct amdgpu_device *adev = ring->adev;
 471         uint32_t tmp = 0;
 472         unsigned i;
 473         int r;
 474
 475         /* VCN in SRIOV does not support direct register read/write */
 476         if (amdgpu_sriov_vf(adev))
 477                 return 0;
 478
 479         WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
 480         r = amdgpu_ring_alloc(ring, 3);
 481         if (r)
 482                 return r;
 483         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
 484         amdgpu_ring_write(ring, 0xDEADBEEF);
 485         amdgpu_ring_commit(ring);
 486         for (i = 0; i < adev->usec_timeout; i++) {
 487                 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
 488                 if (tmp == 0xDEADBEEF)
 489                         break;
 490                 udelay(1);
 491         }
 492
 493         if (i >= adev->usec_timeout)
 494                 r = -ETIMEDOUT;
 495
 496         return r;
 497 }
 498
 499 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
 500 {
 501         struct amdgpu_device *adev = ring->adev;
 502         uint32_t rptr;
 503         unsigned int i;
 504         int r;
 505
 506         if (amdgpu_sriov_vf(adev))
 507                 return 0;
 508
 509         r = amdgpu_ring_alloc(ring, 16);
 510         if (r)
 511                 return r;
 512
 513         rptr = amdgpu_ring_get_rptr(ring);
 514
 515         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
 516         amdgpu_ring_commit(ring);
 517
 518         for (i = 0; i < adev->usec_timeout; i++) {
 519                 if (amdgpu_ring_get_rptr(ring) != rptr)
 520                         break;
 521                 udelay(1);
 522         }
 523
 524         if (i >= adev->usec_timeout)
 525                 r = -ETIMEDOUT;
 526
 527         return r;
 528 }
 529
 530 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
 531                                    struct amdgpu_ib *ib_msg,
 532                                    struct dma_fence **fence)
 533 {
 534         u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 535         struct amdgpu_device *adev = ring->adev;
 536         struct dma_fence *f = NULL;
 537         struct amdgpu_job *job;
 538         struct amdgpu_ib *ib;
 539         int i, r;
 540
 541         r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 542                                      64, AMDGPU_IB_POOL_DIRECT,
 543                                      &job);
 544         if (r)
 545                 goto err;
 546
 547         ib = &job->ibs[0];
 548         ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
 549         ib->ptr[1] = addr;
 550         ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
 551         ib->ptr[3] = addr >> 32;
 552         ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
 553         ib->ptr[5] = 0;
 554         for (i = 6; i < 16; i += 2) {
 555                 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
 556                 ib->ptr[i+1] = 0;
 557         }
 558         ib->length_dw = 16;
 559
 560         r = amdgpu_job_submit_direct(job, ring, &f);
 561         if (r)
 562                 goto err_free;
 563
 564         amdgpu_ib_free(adev, ib_msg, f);
 565
 566         if (fence)
 567                 *fence = dma_fence_get(f);
 568         dma_fence_put(f);
 569
 570         return 0;
 571
 572 err_free:
 573         amdgpu_job_free(job);
 574 err:
 575         amdgpu_ib_free(adev, ib_msg, f);
 576         return r;
 577 }
 578
 579 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 580                 struct amdgpu_ib *ib)
 581 {
 582         struct amdgpu_device *adev = ring->adev;
 583         uint32_t *msg;
 584         int r, i;
 585
 586         memset(ib, 0, sizeof(*ib));
 587         r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
 588                         AMDGPU_IB_POOL_DIRECT,
 589                         ib);
 590         if (r)
 591                 return r;
 592
 593         msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
 594         msg[0] = cpu_to_le32(0x00000028);
 595         msg[1] = cpu_to_le32(0x00000038);
 596         msg[2] = cpu_to_le32(0x00000001);
 597         msg[3] = cpu_to_le32(0x00000000);
 598         msg[4] = cpu_to_le32(handle);
 599         msg[5] = cpu_to_le32(0x00000000);
 600         msg[6] = cpu_to_le32(0x00000001);
 601         msg[7] = cpu_to_le32(0x00000028);
 602         msg[8] = cpu_to_le32(0x00000010);
 603         msg[9] = cpu_to_le32(0x00000000);
 604         msg[10] = cpu_to_le32(0x00000007);
 605         msg[11] = cpu_to_le32(0x00000000);
 606         msg[12] = cpu_to_le32(0x00000780);
 607         msg[13] = cpu_to_le32(0x00000440);
 608         for (i = 14; i < 1024; ++i)
 609                 msg[i] = cpu_to_le32(0x0);
 610
 611         return 0;
 612 }
 613
 614 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 615                                           struct amdgpu_ib *ib)
 616 {
 617         struct amdgpu_device *adev = ring->adev;
 618         uint32_t *msg;
 619         int r, i;
 620
 621         memset(ib, 0, sizeof(*ib));
 622         r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
 623                         AMDGPU_IB_POOL_DIRECT,
 624                         ib);
 625         if (r)
 626                 return r;
 627
 628         msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
 629         msg[0] = cpu_to_le32(0x00000028);
 630         msg[1] = cpu_to_le32(0x00000018);
 631         msg[2] = cpu_to_le32(0x00000000);
 632         msg[3] = cpu_to_le32(0x00000002);
 633         msg[4] = cpu_to_le32(handle);
 634         msg[5] = cpu_to_le32(0x00000000);
 635         for (i = 6; i < 1024; ++i)
 636                 msg[i] = cpu_to_le32(0x0);
 637
 638         return 0;
 639 }
 640
 641 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 642 {
 643         struct dma_fence *fence = NULL;
 644         struct amdgpu_ib ib;
 645         long r;
 646
 647         r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
 648         if (r)
 649                 goto error;
 650
 651         r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL);
 652         if (r)
 653                 goto error;
 654         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
 655         if (r)
 656                 goto error;
 657
 658         r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence);
 659         if (r)
 660                 goto error;
 661
 662         r = dma_fence_wait_timeout(fence, false, timeout);
 663         if (r == 0)
 664                 r = -ETIMEDOUT;
 665         else if (r > 0)
 666                 r = 0;
 667
 668         dma_fence_put(fence);
 669 error:
 670         return r;
 671 }
 672
 673 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
 674                                                 uint32_t ib_pack_in_dw, bool enc)
 675 {
 676         uint32_t *ib_checksum;
 677
 678         ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */
 679         ib->ptr[ib->length_dw++] = 0x30000002;
 680         ib_checksum = &ib->ptr[ib->length_dw++];
 681         ib->ptr[ib->length_dw++] = ib_pack_in_dw;
 682
 683         ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */
 684         ib->ptr[ib->length_dw++] = 0x30000001;
 685         ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3;
 686         ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t);
 687
 688         return ib_checksum;
 689 }
 690
 691 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum,
 692                                                 uint32_t ib_pack_in_dw)
 693 {
 694         uint32_t i;
 695         uint32_t checksum = 0;
 696
 697         for (i = 0; i < ib_pack_in_dw; i++)
 698                 checksum += *(*ib_checksum + 2 + i);
 699
 700         **ib_checksum = checksum;
 701 }
 702
 703 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
 704                                       struct amdgpu_ib *ib_msg,
 705                                       struct dma_fence **fence)
 706 {
 707         struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
 708         unsigned int ib_size_dw = 64;
 709         struct amdgpu_device *adev = ring->adev;
 710         struct dma_fence *f = NULL;
 711         struct amdgpu_job *job;
 712         struct amdgpu_ib *ib;
 713         uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 714         bool sq = amdgpu_vcn_using_unified_queue(ring);
 715         uint32_t *ib_checksum;
 716         uint32_t ib_pack_in_dw;
 717         int i, r;
 718
 719         if (sq)
 720                 ib_size_dw += 8;
 721
 722         r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 723                                      ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
 724                                      &job);
 725         if (r)
 726                 goto err;
 727
 728         ib = &job->ibs[0];
 729         ib->length_dw = 0;
 730
 731         /* single queue headers */
 732         if (sq) {
 733                 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)
 734                                                 + 4 + 2; /* engine info + decoding ib in dw */
 735                 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);
 736         }
 737
 738         ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
 739         ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
 740         decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
 741         ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
 742         memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
 743
 744         decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
 745         decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
 746         decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
 747
 748         for (i = ib->length_dw; i < ib_size_dw; ++i)
 749                 ib->ptr[i] = 0x0;
 750
 751         if (sq)
 752                 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw);
 753
 754         r = amdgpu_job_submit_direct(job, ring, &f);
 755         if (r)
 756                 goto err_free;
 757
 758         amdgpu_ib_free(adev, ib_msg, f);
 759
 760         if (fence)
 761                 *fence = dma_fence_get(f);
 762         dma_fence_put(f);
 763
 764         return 0;
 765
 766 err_free:
 767         amdgpu_job_free(job);
 768 err:
 769         amdgpu_ib_free(adev, ib_msg, f);
 770         return r;
 771 }
 772
 773 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 774 {
 775         struct dma_fence *fence = NULL;
 776         struct amdgpu_ib ib;
 777         long r;
 778
 779         r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
 780         if (r)
 781                 goto error;
 782
 783         r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL);
 784         if (r)
 785                 goto error;
 786         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
 787         if (r)
 788                 goto error;
 789
 790         r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence);
 791         if (r)
 792                 goto error;
 793
 794         r = dma_fence_wait_timeout(fence, false, timeout);
 795         if (r == 0)
 796                 r = -ETIMEDOUT;
 797         else if (r > 0)
 798                 r = 0;
 799
 800         dma_fence_put(fence);
 801 error:
 802         return r;
 803 }
 804
 805 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
 806 {
 807         struct amdgpu_device *adev = ring->adev;
 808         uint32_t rptr;
 809         unsigned i;
 810         int r;
 811
 812         if (amdgpu_sriov_vf(adev))
 813                 return 0;
 814
 815         r = amdgpu_ring_alloc(ring, 16);
 816         if (r)
 817                 return r;
 818
 819         rptr = amdgpu_ring_get_rptr(ring);
 820
 821         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
 822         amdgpu_ring_commit(ring);
 823
 824         for (i = 0; i < adev->usec_timeout; i++) {
 825                 if (amdgpu_ring_get_rptr(ring) != rptr)
 826                         break;
 827                 udelay(1);
 828         }
 829
 830         if (i >= adev->usec_timeout)
 831                 r = -ETIMEDOUT;
 832
 833         return r;
 834 }
 835
 836 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 837                                          struct amdgpu_ib *ib_msg,
 838                                          struct dma_fence **fence)
 839 {
 840         unsigned int ib_size_dw = 16;
 841         struct amdgpu_job *job;
 842         struct amdgpu_ib *ib;
 843         struct dma_fence *f = NULL;
 844         uint32_t *ib_checksum = NULL;
 845         uint64_t addr;
 846         bool sq = amdgpu_vcn_using_unified_queue(ring);
 847         int i, r;
 848
 849         if (sq)
 850                 ib_size_dw += 8;
 851
 852         r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 853                                      ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
 854                                      &job);
 855         if (r)
 856                 return r;
 857
 858         ib = &job->ibs[0];
 859         addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 860
 861         ib->length_dw = 0;
 862
 863         if (sq)
 864                 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
 865
 866         ib->ptr[ib->length_dw++] = 0x00000018;
 867         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 868         ib->ptr[ib->length_dw++] = handle;
 869         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 870         ib->ptr[ib->length_dw++] = addr;
 871         ib->ptr[ib->length_dw++] = 0x0000000b;
 872
 873         ib->ptr[ib->length_dw++] = 0x00000014;
 874         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 875         ib->ptr[ib->length_dw++] = 0x0000001c;
 876         ib->ptr[ib->length_dw++] = 0x00000000;
 877         ib->ptr[ib->length_dw++] = 0x00000000;
 878
 879         ib->ptr[ib->length_dw++] = 0x00000008;
 880         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 881
 882         for (i = ib->length_dw; i < ib_size_dw; ++i)
 883                 ib->ptr[i] = 0x0;
 884
 885         if (sq)
 886                 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
 887
 888         r = amdgpu_job_submit_direct(job, ring, &f);
 889         if (r)
 890                 goto err;
 891
 892         if (fence)
 893                 *fence = dma_fence_get(f);
 894         dma_fence_put(f);
 895
 896         return 0;
 897
 898 err:
 899         amdgpu_job_free(job);
 900         return r;
 901 }
 902
 903 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 904                                           struct amdgpu_ib *ib_msg,
 905                                           struct dma_fence **fence)
 906 {
 907         unsigned int ib_size_dw = 16;
 908         struct amdgpu_job *job;
 909         struct amdgpu_ib *ib;
 910         struct dma_fence *f = NULL;
 911         uint32_t *ib_checksum = NULL;
 912         uint64_t addr;
 913         bool sq = amdgpu_vcn_using_unified_queue(ring);
 914         int i, r;
 915
 916         if (sq)
 917                 ib_size_dw += 8;
 918
 919         r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
 920                                      ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
 921                                      &job);
 922         if (r)
 923                 return r;
 924
 925         ib = &job->ibs[0];
 926         addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
 927
 928         ib->length_dw = 0;
 929
 930         if (sq)
 931                 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
 932
 933         ib->ptr[ib->length_dw++] = 0x00000018;
 934         ib->ptr[ib->length_dw++] = 0x00000001;
 935         ib->ptr[ib->length_dw++] = handle;
 936         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 937         ib->ptr[ib->length_dw++] = addr;
 938         ib->ptr[ib->length_dw++] = 0x0000000b;
 939
 940         ib->ptr[ib->length_dw++] = 0x00000014;
 941         ib->ptr[ib->length_dw++] = 0x00000002;
 942         ib->ptr[ib->length_dw++] = 0x0000001c;
 943         ib->ptr[ib->length_dw++] = 0x00000000;
 944         ib->ptr[ib->length_dw++] = 0x00000000;
 945
 946         ib->ptr[ib->length_dw++] = 0x00000008;
 947         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 948
 949         for (i = ib->length_dw; i < ib_size_dw; ++i)
 950                 ib->ptr[i] = 0x0;
 951
 952         if (sq)
 953                 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
 954
 955         r = amdgpu_job_submit_direct(job, ring, &f);
 956         if (r)
 957                 goto err;
 958
 959         if (fence)
 960                 *fence = dma_fence_get(f);
 961         dma_fence_put(f);
 962
 963         return 0;
 964
 965 err:
 966         amdgpu_job_free(job);
 967         return r;
 968 }
 969
 970 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 971 {
 972         struct amdgpu_device *adev = ring->adev;
 973         struct dma_fence *fence = NULL;
 974         struct amdgpu_ib ib;
 975         long r;
 976
 977         memset(&ib, 0, sizeof(ib));
 978         r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE,
 979                         AMDGPU_IB_POOL_DIRECT,
 980                         &ib);
 981         if (r)
 982                 return r;
 983
 984         r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL);
 985         if (r)
 986                 goto error;
 987
 988         r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence);
 989         if (r)
 990                 goto error;
 991
 992         r = dma_fence_wait_timeout(fence, false, timeout);
 993         if (r == 0)
 994                 r = -ETIMEDOUT;
 995         else if (r > 0)
 996                 r = 0;
 997
 998 error:
 999         amdgpu_ib_free(adev, &ib, fence);
1000         dma_fence_put(fence);
1001
1002         return r;
1003 }
1004
1005 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1006 {
1007         long r;
1008
1009         r = amdgpu_vcn_enc_ring_test_ib(ring, timeout);
1010         if (r)
1011                 goto error;
1012
1013         r =  amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout);
1014
1015 error:
1016         return r;
1017 }
1018
1019 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)
1020 {
1021         switch(ring) {
1022         case 0:
1023                 return AMDGPU_RING_PRIO_0;
1024         case 1:
1025                 return AMDGPU_RING_PRIO_1;
1026         case 2:
1027                 return AMDGPU_RING_PRIO_2;
1028         default:
1029                 return AMDGPU_RING_PRIO_0;
1030         }
1031 }
1032
1033 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
1034 {
1035         int i;
1036         unsigned int idx;
1037
1038         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1039                 const struct common_firmware_header *hdr;
1040                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
1041
1042                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1043                         if (adev->vcn.harvest_config & (1 << i))
1044                                 continue;
1045                         /* currently only support 2 FW instances */
1046                         if (i >= 2) {
1047                                 dev_info(adev->dev, "More then 2 VCN FW instances!\n");
1048                                 break;
1049                         }
1050                         idx = AMDGPU_UCODE_ID_VCN + i;
1051                         adev->firmware.ucode[idx].ucode_id = idx;
1052                         adev->firmware.ucode[idx].fw = adev->vcn.fw;
1053                         adev->firmware.fw_size +=
1054                                 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
1055                 }
1056                 dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
1057         }
1058 }
1059
1060 /*
1061  * debugfs for mapping vcn firmware log buffer.
1062  */
1063 #if defined(CONFIG_DEBUG_FS)
1064 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf,
1065                                              size_t size, loff_t *pos)
1066 {
1067         struct amdgpu_vcn_inst *vcn;
1068         void *log_buf;
1069         volatile struct amdgpu_vcn_fwlog *plog;
1070         unsigned int read_pos, write_pos, available, i, read_bytes = 0;
1071         unsigned int read_num[2] = {0};
1072
1073         vcn = file_inode(f)->i_private;
1074         if (!vcn)
1075                 return -ENODEV;
1076
1077         if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log)
1078                 return -EFAULT;
1079
1080         log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1081
1082         plog = (volatile struct amdgpu_vcn_fwlog *)log_buf;
1083         read_pos = plog->rptr;
1084         write_pos = plog->wptr;
1085
1086         if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE)
1087                 return -EFAULT;
1088
1089         if (!size || (read_pos == write_pos))
1090                 return 0;
1091
1092         if (write_pos > read_pos) {
1093                 available = write_pos - read_pos;
1094                 read_num[0] = min(size, (size_t)available);
1095         } else {
1096                 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos;
1097                 available = read_num[0] + write_pos - plog->header_size;
1098                 if (size > available)
1099                         read_num[1] = write_pos - plog->header_size;
1100                 else if (size > read_num[0])
1101                         read_num[1] = size - read_num[0];
1102                 else
1103                         read_num[0] = size;
1104         }
1105
1106         for (i = 0; i < 2; i++) {
1107                 if (read_num[i]) {
1108                         if (read_pos == AMDGPU_VCNFW_LOG_SIZE)
1109                                 read_pos = plog->header_size;
1110                         if (read_num[i] == copy_to_user((buf + read_bytes),
1111                                                         (log_buf + read_pos), read_num[i]))
1112                                 return -EFAULT;
1113
1114                         read_bytes += read_num[i];
1115                         read_pos += read_num[i];
1116                 }
1117         }
1118
1119         plog->rptr = read_pos;
1120         *pos += read_bytes;
1121         return read_bytes;
1122 }
1123
1124 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = {
1125         .owner = THIS_MODULE,
1126         .read = amdgpu_debugfs_vcn_fwlog_read,
1127         .llseek = default_llseek
1128 };
1129 #endif
1130
1131 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i,
1132                                    struct amdgpu_vcn_inst *vcn)
1133 {
1134 #if defined(CONFIG_DEBUG_FS)
1135         struct drm_minor *minor = adev_to_drm(adev)->primary;
1136         struct dentry *root = minor->debugfs_root;
1137         char name[32];
1138
1139         sprintf(name, "amdgpu_vcn_%d_fwlog", i);
1140         debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, vcn,
1141                                  &amdgpu_debugfs_vcnfwlog_fops,
1142                                  AMDGPU_VCNFW_LOG_SIZE);
1143 #endif
1144 }
1145
1146 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn)
1147 {
1148 #if defined(CONFIG_DEBUG_FS)
1149         volatile uint32_t *flag = vcn->fw_shared.cpu_addr;
1150         void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1151         uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size;
1152         volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr;
1153         volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr
1154                                                          + vcn->fw_shared.log_offset;
1155         *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG);
1156         fw_log->is_enabled = 1;
1157         fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF);
1158         fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32);
1159         fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE);
1160
1161         log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog);
1162         log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE;
1163         log_buf->rptr = log_buf->header_size;
1164         log_buf->wptr = log_buf->header_size;
1165         log_buf->wrapped = 0;
1166 #endif
1167 }
1168
1169 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev,
1170                                 struct amdgpu_irq_src *source,
1171                                 struct amdgpu_iv_entry *entry)
1172 {
1173         struct ras_common_if *ras_if = adev->vcn.ras_if;
1174         struct ras_dispatch_if ih_data = {
1175                 .entry = entry,
1176         };
1177
1178         if (!ras_if)
1179                 return 0;
1180
1181         if (!amdgpu_sriov_vf(adev)) {
1182                 ih_data.head = *ras_if;
1183                 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
1184         } else {
1185                 if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
1186                         adev->virt.ops->ras_poison_handler(adev);
1187                 else
1188                         dev_warn(adev->dev,
1189                                 "No ras_poison_handler interface in SRIOV for VCN!\n");
1190         }
1191
1192         return 0;
1193 }
1194
1195 int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev)
1196 {
1197         int err;
1198         struct amdgpu_vcn_ras *ras;
1199
1200         if (!adev->vcn.ras)
1201                 return 0;
1202
1203         ras = adev->vcn.ras;
1204         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
1205         if (err) {
1206                 dev_err(adev->dev, "Failed to register vcn ras block!\n");
1207                 return err;
1208         }
1209
1210         strcpy(ras->ras_block.ras_comm.name, "vcn");
1211         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN;
1212         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
1213         adev->vcn.ras_if = &ras->ras_block.ras_comm;
1214
1215         if (!ras->ras_block.ras_late_init)
1216                 ras->ras_block.ras_late_init = amdgpu_ras_block_late_init;
1217
1218         return 0;
1219 }