2 * Copyright 2011 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Christian König <deathsimple@vodafone.de>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
35 #include <drm/drm_drv.h>
38 #include "amdgpu_pm.h"
39 #include "amdgpu_uvd.h"
40 #include "amdgpu_cs.h"
42 #include "uvd/uvd_4_2_d.h"
44 #include "amdgpu_ras.h"
46 /* 1 second timeout */
47 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
49 /* Firmware versions for VI */
50 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8))
51 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8))
52 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8))
53 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8))
55 /* Polaris10/11 firmware version */
56 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
59 #ifdef CONFIG_DRM_AMDGPU_SI
60 #define FIRMWARE_TAHITI "amdgpu/tahiti_uvd.bin"
61 #define FIRMWARE_VERDE "amdgpu/verde_uvd.bin"
62 #define FIRMWARE_PITCAIRN "amdgpu/pitcairn_uvd.bin"
63 #define FIRMWARE_OLAND "amdgpu/oland_uvd.bin"
65 #ifdef CONFIG_DRM_AMDGPU_CIK
66 #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin"
67 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin"
68 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin"
69 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin"
70 #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin"
72 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
73 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
74 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin"
75 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
76 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin"
77 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin"
78 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin"
79 #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin"
81 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin"
82 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin"
83 #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin"
85 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */
86 #define UVD_GPCOM_VCPU_CMD 0x03c3
87 #define UVD_GPCOM_VCPU_DATA0 0x03c4
88 #define UVD_GPCOM_VCPU_DATA1 0x03c5
89 #define UVD_NO_OP 0x03ff
90 #define UVD_BASE_SI 0x3800
93 * amdgpu_uvd_cs_ctx - Command submission parser context
95 * Used for emulating virtual memory support on UVD 4.2.
97 struct amdgpu_uvd_cs_ctx {
98 struct amdgpu_cs_parser *parser;
100 unsigned data0, data1;
102 struct amdgpu_ib *ib;
104 /* does the IB has a msg command */
107 /* minimum buffer sizes */
111 #ifdef CONFIG_DRM_AMDGPU_SI
112 MODULE_FIRMWARE(FIRMWARE_TAHITI);
113 MODULE_FIRMWARE(FIRMWARE_VERDE);
114 MODULE_FIRMWARE(FIRMWARE_PITCAIRN);
115 MODULE_FIRMWARE(FIRMWARE_OLAND);
117 #ifdef CONFIG_DRM_AMDGPU_CIK
118 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
119 MODULE_FIRMWARE(FIRMWARE_KABINI);
120 MODULE_FIRMWARE(FIRMWARE_KAVERI);
121 MODULE_FIRMWARE(FIRMWARE_HAWAII);
122 MODULE_FIRMWARE(FIRMWARE_MULLINS);
124 MODULE_FIRMWARE(FIRMWARE_TONGA);
125 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
126 MODULE_FIRMWARE(FIRMWARE_FIJI);
127 MODULE_FIRMWARE(FIRMWARE_STONEY);
128 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
129 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
130 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
131 MODULE_FIRMWARE(FIRMWARE_VEGAM);
133 MODULE_FIRMWARE(FIRMWARE_VEGA10);
134 MODULE_FIRMWARE(FIRMWARE_VEGA12);
135 MODULE_FIRMWARE(FIRMWARE_VEGA20);
137 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
138 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo);
140 static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev,
142 struct amdgpu_bo **bo_ptr)
144 struct ttm_operation_ctx ctx = { true, false };
145 struct amdgpu_bo *bo = NULL;
149 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,
150 AMDGPU_GEM_DOMAIN_GTT,
155 if (adev->uvd.address_64_bit)
158 amdgpu_bo_kunmap(bo);
160 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
161 amdgpu_uvd_force_into_uvd_segment(bo);
162 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
165 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM);
168 r = amdgpu_bo_kmap(bo, &addr);
172 amdgpu_bo_unreserve(bo);
179 amdgpu_bo_unreserve(bo);
180 amdgpu_bo_unref(&bo);
184 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
186 unsigned long bo_size;
188 const struct common_firmware_header *hdr;
192 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
194 switch (adev->asic_type) {
195 #ifdef CONFIG_DRM_AMDGPU_SI
197 fw_name = FIRMWARE_TAHITI;
200 fw_name = FIRMWARE_VERDE;
203 fw_name = FIRMWARE_PITCAIRN;
206 fw_name = FIRMWARE_OLAND;
209 #ifdef CONFIG_DRM_AMDGPU_CIK
211 fw_name = FIRMWARE_BONAIRE;
214 fw_name = FIRMWARE_KABINI;
217 fw_name = FIRMWARE_KAVERI;
220 fw_name = FIRMWARE_HAWAII;
223 fw_name = FIRMWARE_MULLINS;
227 fw_name = FIRMWARE_TONGA;
230 fw_name = FIRMWARE_FIJI;
233 fw_name = FIRMWARE_CARRIZO;
236 fw_name = FIRMWARE_STONEY;
239 fw_name = FIRMWARE_POLARIS10;
242 fw_name = FIRMWARE_POLARIS11;
245 fw_name = FIRMWARE_POLARIS12;
248 fw_name = FIRMWARE_VEGA10;
251 fw_name = FIRMWARE_VEGA12;
254 fw_name = FIRMWARE_VEGAM;
257 fw_name = FIRMWARE_VEGA20;
263 r = amdgpu_ucode_request(adev, &adev->uvd.fw, fw_name);
265 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
267 amdgpu_ucode_release(&adev->uvd.fw);
271 /* Set the default UVD handles that the firmware can handle */
272 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
274 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
275 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
277 if (adev->asic_type < CHIP_VEGA20) {
278 unsigned version_major, version_minor;
280 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
281 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
282 DRM_INFO("Found UVD firmware Version: %u.%u Family ID: %u\n",
283 version_major, version_minor, family_id);
286 * Limit the number of UVD handles depending on microcode major
287 * and minor versions. The firmware version which has 40 UVD
288 * instances support is 1.80. So all subsequent versions should
289 * also have the same support.
291 if ((version_major > 0x01) ||
292 ((version_major == 0x01) && (version_minor >= 0x50)))
293 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
295 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
298 if ((adev->asic_type == CHIP_POLARIS10 ||
299 adev->asic_type == CHIP_POLARIS11) &&
300 (adev->uvd.fw_version < FW_1_66_16))
301 DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n",
302 version_major, version_minor);
304 unsigned int enc_major, enc_minor, dec_minor;
306 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
307 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f;
308 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3;
309 DRM_INFO("Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n",
310 enc_major, enc_minor, dec_minor, family_id);
312 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
314 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version);
317 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
318 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
319 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
320 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
322 for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
323 if (adev->uvd.harvest_config & (1 << j))
325 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
326 AMDGPU_GEM_DOMAIN_VRAM |
327 AMDGPU_GEM_DOMAIN_GTT,
328 &adev->uvd.inst[j].vcpu_bo,
329 &adev->uvd.inst[j].gpu_addr,
330 &adev->uvd.inst[j].cpu_addr);
332 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
337 for (i = 0; i < adev->uvd.max_handles; ++i) {
338 atomic_set(&adev->uvd.handles[i], 0);
339 adev->uvd.filp[i] = NULL;
342 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
343 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
344 adev->uvd.address_64_bit = true;
346 r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo);
350 switch (adev->asic_type) {
352 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
355 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
358 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
361 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
364 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
370 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
372 void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo);
375 drm_sched_entity_destroy(&adev->uvd.entity);
377 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
378 if (adev->uvd.harvest_config & (1 << j))
380 kvfree(adev->uvd.inst[j].saved_bo);
382 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,
383 &adev->uvd.inst[j].gpu_addr,
384 (void **)&adev->uvd.inst[j].cpu_addr);
386 amdgpu_ring_fini(&adev->uvd.inst[j].ring);
388 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
389 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
391 amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr);
392 amdgpu_ucode_release(&adev->uvd.fw);
398 * amdgpu_uvd_entity_init - init entity
400 * @adev: amdgpu_device pointer
403 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
405 struct amdgpu_ring *ring;
406 struct drm_gpu_scheduler *sched;
409 ring = &adev->uvd.inst[0].ring;
410 sched = &ring->sched;
411 r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
414 DRM_ERROR("Failed setting up UVD kernel entity.\n");
421 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
426 bool in_ras_intr = amdgpu_ras_intr_triggered();
428 cancel_delayed_work_sync(&adev->uvd.idle_work);
430 /* only valid for physical mode */
431 if (adev->asic_type < CHIP_POLARIS10) {
432 for (i = 0; i < adev->uvd.max_handles; ++i)
433 if (atomic_read(&adev->uvd.handles[i]))
436 if (i == adev->uvd.max_handles)
440 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
441 if (adev->uvd.harvest_config & (1 << j))
443 if (adev->uvd.inst[j].vcpu_bo == NULL)
446 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);
447 ptr = adev->uvd.inst[j].cpu_addr;
449 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL);
450 if (!adev->uvd.inst[j].saved_bo)
453 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
454 /* re-write 0 since err_event_athub will corrupt VCPU buffer */
456 memset(adev->uvd.inst[j].saved_bo, 0, size);
458 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
465 DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n");
470 int amdgpu_uvd_resume(struct amdgpu_device *adev)
476 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
477 if (adev->uvd.harvest_config & (1 << i))
479 if (adev->uvd.inst[i].vcpu_bo == NULL)
482 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);
483 ptr = adev->uvd.inst[i].cpu_addr;
485 if (adev->uvd.inst[i].saved_bo != NULL) {
486 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
487 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);
490 kvfree(adev->uvd.inst[i].saved_bo);
491 adev->uvd.inst[i].saved_bo = NULL;
493 const struct common_firmware_header *hdr;
496 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
497 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
498 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
499 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
500 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,
501 le32_to_cpu(hdr->ucode_size_bytes));
504 size -= le32_to_cpu(hdr->ucode_size_bytes);
505 ptr += le32_to_cpu(hdr->ucode_size_bytes);
507 memset_io(ptr, 0, size);
508 /* to restore uvd fence seq */
509 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
515 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
517 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;
520 for (i = 0; i < adev->uvd.max_handles; ++i) {
521 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
523 if (handle != 0 && adev->uvd.filp[i] == filp) {
524 struct dma_fence *fence;
526 r = amdgpu_uvd_get_destroy_msg(ring, handle, false,
529 DRM_ERROR("Error destroying UVD %d!\n", r);
533 dma_fence_wait(fence, false);
534 dma_fence_put(fence);
536 adev->uvd.filp[i] = NULL;
537 atomic_set(&adev->uvd.handles[i], 0);
542 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
545 for (i = 0; i < abo->placement.num_placement; ++i) {
546 abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
547 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
551 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
556 lo = amdgpu_ib_get_value(ctx->ib, ctx->data0);
557 hi = amdgpu_ib_get_value(ctx->ib, ctx->data1);
558 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
564 * amdgpu_uvd_cs_pass1 - first parsing round
566 * @ctx: UVD parser context
568 * Make sure UVD message and feedback buffers are in VRAM and
569 * nobody is violating an 256MB boundary.
571 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
573 struct ttm_operation_ctx tctx = { false, false };
574 struct amdgpu_bo_va_mapping *mapping;
575 struct amdgpu_bo *bo;
577 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
580 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
582 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
586 if (!ctx->parser->adev->uvd.address_64_bit) {
587 /* check if it's a message or feedback command */
588 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1;
589 if (cmd == 0x0 || cmd == 0x3) {
590 /* yes, force it into VRAM */
591 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
592 amdgpu_bo_placement_from_domain(bo, domain);
594 amdgpu_uvd_force_into_uvd_segment(bo);
596 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx);
603 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
605 * @adev: amdgpu_device pointer
606 * @msg: pointer to message structure
607 * @buf_sizes: placeholder to put the different buffer lengths
609 * Peek into the decode message and calculate the necessary buffer sizes.
611 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
612 unsigned buf_sizes[])
614 unsigned stream_type = msg[4];
615 unsigned width = msg[6];
616 unsigned height = msg[7];
617 unsigned dpb_size = msg[9];
618 unsigned pitch = msg[28];
619 unsigned level = msg[57];
621 unsigned width_in_mb = width / 16;
622 unsigned height_in_mb = ALIGN(height / 16, 2);
623 unsigned fs_in_mb = width_in_mb * height_in_mb;
625 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
626 unsigned min_ctx_size = ~0;
628 image_size = width * height;
629 image_size += image_size / 2;
630 image_size = ALIGN(image_size, 1024);
632 switch (stream_type) {
636 num_dpb_buffer = 8100 / fs_in_mb;
639 num_dpb_buffer = 18000 / fs_in_mb;
642 num_dpb_buffer = 20480 / fs_in_mb;
645 num_dpb_buffer = 32768 / fs_in_mb;
648 num_dpb_buffer = 34816 / fs_in_mb;
651 num_dpb_buffer = 110400 / fs_in_mb;
654 num_dpb_buffer = 184320 / fs_in_mb;
657 num_dpb_buffer = 184320 / fs_in_mb;
661 if (num_dpb_buffer > 17)
664 /* reference picture buffer */
665 min_dpb_size = image_size * num_dpb_buffer;
667 /* macroblock context buffer */
668 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
670 /* IT surface buffer */
671 min_dpb_size += width_in_mb * height_in_mb * 32;
676 /* reference picture buffer */
677 min_dpb_size = image_size * 3;
680 min_dpb_size += width_in_mb * height_in_mb * 128;
682 /* IT surface buffer */
683 min_dpb_size += width_in_mb * 64;
685 /* DB surface buffer */
686 min_dpb_size += width_in_mb * 128;
689 tmp = max(width_in_mb, height_in_mb);
690 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
695 /* reference picture buffer */
696 min_dpb_size = image_size * 3;
701 /* reference picture buffer */
702 min_dpb_size = image_size * 3;
705 min_dpb_size += width_in_mb * height_in_mb * 64;
707 /* IT surface buffer */
708 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
711 case 7: /* H264 Perf */
714 num_dpb_buffer = 8100 / fs_in_mb;
717 num_dpb_buffer = 18000 / fs_in_mb;
720 num_dpb_buffer = 20480 / fs_in_mb;
723 num_dpb_buffer = 32768 / fs_in_mb;
726 num_dpb_buffer = 34816 / fs_in_mb;
729 num_dpb_buffer = 110400 / fs_in_mb;
732 num_dpb_buffer = 184320 / fs_in_mb;
735 num_dpb_buffer = 184320 / fs_in_mb;
739 if (num_dpb_buffer > 17)
742 /* reference picture buffer */
743 min_dpb_size = image_size * num_dpb_buffer;
745 if (!adev->uvd.use_ctx_buf){
746 /* macroblock context buffer */
748 width_in_mb * height_in_mb * num_dpb_buffer * 192;
750 /* IT surface buffer */
751 min_dpb_size += width_in_mb * height_in_mb * 32;
753 /* macroblock context buffer */
755 width_in_mb * height_in_mb * num_dpb_buffer * 192;
764 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
765 image_size = ALIGN(image_size, 256);
767 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
768 min_dpb_size = image_size * num_dpb_buffer;
769 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
770 * 16 * num_dpb_buffer + 52 * 1024;
774 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
779 DRM_ERROR("Invalid UVD decoding target pitch!\n");
783 if (dpb_size < min_dpb_size) {
784 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
785 dpb_size, min_dpb_size);
789 buf_sizes[0x1] = dpb_size;
790 buf_sizes[0x2] = image_size;
791 buf_sizes[0x4] = min_ctx_size;
792 /* store image width to adjust nb memory pstate */
793 adev->uvd.decode_image_width = width;
798 * amdgpu_uvd_cs_msg - handle UVD message
800 * @ctx: UVD parser context
801 * @bo: buffer object containing the message
802 * @offset: offset into the buffer object
804 * Peek into the UVD message and extract the session id.
805 * Make sure that we don't open up to many sessions.
807 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
808 struct amdgpu_bo *bo, unsigned offset)
810 struct amdgpu_device *adev = ctx->parser->adev;
811 int32_t *msg, msg_type, handle;
817 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
821 r = amdgpu_bo_kmap(bo, &ptr);
823 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r);
833 amdgpu_bo_kunmap(bo);
834 DRM_ERROR("Invalid UVD handle!\n");
840 /* it's a create msg, calc image size (width * height) */
841 amdgpu_bo_kunmap(bo);
843 /* try to alloc a new handle */
844 for (i = 0; i < adev->uvd.max_handles; ++i) {
845 if (atomic_read(&adev->uvd.handles[i]) == handle) {
846 DRM_ERROR(")Handle 0x%x already in use!\n",
851 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
852 adev->uvd.filp[i] = ctx->parser->filp;
857 DRM_ERROR("No more free UVD handles!\n");
861 /* it's a decode msg, calc buffer sizes */
862 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
863 amdgpu_bo_kunmap(bo);
867 /* validate the handle */
868 for (i = 0; i < adev->uvd.max_handles; ++i) {
869 if (atomic_read(&adev->uvd.handles[i]) == handle) {
870 if (adev->uvd.filp[i] != ctx->parser->filp) {
871 DRM_ERROR("UVD handle collision detected!\n");
878 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
882 /* it's a destroy msg, free the handle */
883 for (i = 0; i < adev->uvd.max_handles; ++i)
884 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
885 amdgpu_bo_kunmap(bo);
889 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
892 amdgpu_bo_kunmap(bo);
897 * amdgpu_uvd_cs_pass2 - second parsing round
899 * @ctx: UVD parser context
901 * Patch buffer addresses, make sure buffer sizes are correct.
903 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
905 struct amdgpu_bo_va_mapping *mapping;
906 struct amdgpu_bo *bo;
909 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
912 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
914 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
918 start = amdgpu_bo_gpu_offset(bo);
920 end = (mapping->last + 1 - mapping->start);
921 end = end * AMDGPU_GPU_PAGE_SIZE + start;
923 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
926 amdgpu_ib_set_value(ctx->ib, ctx->data0, lower_32_bits(start));
927 amdgpu_ib_set_value(ctx->ib, ctx->data1, upper_32_bits(start));
929 cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1;
931 if ((end - start) < ctx->buf_sizes[cmd]) {
932 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
933 (unsigned)(end - start),
934 ctx->buf_sizes[cmd]);
938 } else if (cmd == 0x206) {
939 if ((end - start) < ctx->buf_sizes[4]) {
940 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
941 (unsigned)(end - start),
945 } else if ((cmd != 0x100) && (cmd != 0x204)) {
946 DRM_ERROR("invalid UVD command %X!\n", cmd);
950 if (!ctx->parser->adev->uvd.address_64_bit) {
951 if ((start >> 28) != ((end - 1) >> 28)) {
952 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
957 if ((cmd == 0 || cmd == 0x3) &&
958 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {
959 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
966 ctx->has_msg_cmd = true;
967 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
970 } else if (!ctx->has_msg_cmd) {
971 DRM_ERROR("Message needed before other commands are send!\n");
979 * amdgpu_uvd_cs_reg - parse register writes
981 * @ctx: UVD parser context
982 * @cb: callback function
984 * Parse the register writes, call cb on each complete command.
986 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
987 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
992 for (i = 0; i <= ctx->count; ++i) {
993 unsigned reg = ctx->reg + i;
995 if (ctx->idx >= ctx->ib->length_dw) {
996 DRM_ERROR("Register command after end of CS!\n");
1001 case mmUVD_GPCOM_VCPU_DATA0:
1002 ctx->data0 = ctx->idx;
1004 case mmUVD_GPCOM_VCPU_DATA1:
1005 ctx->data1 = ctx->idx;
1007 case mmUVD_GPCOM_VCPU_CMD:
1012 case mmUVD_ENGINE_CNTL:
1016 DRM_ERROR("Invalid reg 0x%X!\n", reg);
1025 * amdgpu_uvd_cs_packets - parse UVD packets
1027 * @ctx: UVD parser context
1028 * @cb: callback function
1030 * Parse the command stream packets.
1032 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
1033 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
1037 for (ctx->idx = 0 ; ctx->idx < ctx->ib->length_dw; ) {
1038 uint32_t cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx);
1039 unsigned type = CP_PACKET_GET_TYPE(cmd);
1042 ctx->reg = CP_PACKET0_GET_REG(cmd);
1043 ctx->count = CP_PACKET_GET_COUNT(cmd);
1044 r = amdgpu_uvd_cs_reg(ctx, cb);
1052 DRM_ERROR("Unknown packet type %d !\n", type);
1060 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
1062 * @parser: Command submission parser context
1063 * @job: the job to parse
1064 * @ib: the IB to patch
1066 * Parse the command stream, patch in addresses as necessary.
1068 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser,
1069 struct amdgpu_job *job,
1070 struct amdgpu_ib *ib)
1072 struct amdgpu_uvd_cs_ctx ctx = {};
1073 unsigned buf_sizes[] = {
1074 [0x00000000] = 2048,
1075 [0x00000001] = 0xFFFFFFFF,
1076 [0x00000002] = 0xFFFFFFFF,
1077 [0x00000003] = 2048,
1078 [0x00000004] = 0xFFFFFFFF,
1083 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
1085 if (ib->length_dw % 16) {
1086 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
1091 ctx.parser = parser;
1092 ctx.buf_sizes = buf_sizes;
1095 /* first round only required on chips without UVD 64 bit address support */
1096 if (!parser->adev->uvd.address_64_bit) {
1097 /* first round, make sure the buffers are actually in the UVD segment */
1098 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
1103 /* second round, patch buffer addresses into the command stream */
1104 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
1108 if (!ctx.has_msg_cmd) {
1109 DRM_ERROR("UVD-IBs need a msg command!\n");
1116 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
1117 bool direct, struct dma_fence **fence)
1119 struct amdgpu_device *adev = ring->adev;
1120 struct dma_fence *f = NULL;
1121 struct amdgpu_job *job;
1122 struct amdgpu_ib *ib;
1126 unsigned offset_idx = 0;
1127 unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
1129 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity,
1130 AMDGPU_FENCE_OWNER_UNDEFINED,
1131 64, direct ? AMDGPU_IB_POOL_DIRECT :
1132 AMDGPU_IB_POOL_DELAYED, &job);
1136 if (adev->asic_type >= CHIP_VEGA10) {
1137 offset_idx = 1 + ring->me;
1138 offset[1] = adev->reg_offset[UVD_HWIP][0][1];
1139 offset[2] = adev->reg_offset[UVD_HWIP][1][1];
1142 data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0);
1143 data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0);
1144 data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0);
1145 data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0);
1148 addr = amdgpu_bo_gpu_offset(bo);
1149 ib->ptr[0] = data[0];
1151 ib->ptr[2] = data[1];
1152 ib->ptr[3] = addr >> 32;
1153 ib->ptr[4] = data[2];
1155 for (i = 6; i < 16; i += 2) {
1156 ib->ptr[i] = data[3];
1162 r = amdgpu_job_submit_direct(job, ring, &f);
1166 r = drm_sched_job_add_resv_dependencies(&job->base,
1168 DMA_RESV_USAGE_KERNEL);
1172 f = amdgpu_job_submit(job);
1175 amdgpu_bo_reserve(bo, true);
1176 amdgpu_bo_fence(bo, f, false);
1177 amdgpu_bo_unreserve(bo);
1180 *fence = dma_fence_get(f);
1186 amdgpu_job_free(job);
1190 /* multiple fence commands without any stream commands in between can
1191 crash the vcpu so just try to emmit a dummy create/destroy msg to
1193 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
1194 struct dma_fence **fence)
1196 struct amdgpu_device *adev = ring->adev;
1197 struct amdgpu_bo *bo = adev->uvd.ib_bo;
1201 msg = amdgpu_bo_kptr(bo);
1202 /* stitch together an UVD create msg */
1203 msg[0] = cpu_to_le32(0x00000de4);
1204 msg[1] = cpu_to_le32(0x00000000);
1205 msg[2] = cpu_to_le32(handle);
1206 msg[3] = cpu_to_le32(0x00000000);
1207 msg[4] = cpu_to_le32(0x00000000);
1208 msg[5] = cpu_to_le32(0x00000000);
1209 msg[6] = cpu_to_le32(0x00000000);
1210 msg[7] = cpu_to_le32(0x00000780);
1211 msg[8] = cpu_to_le32(0x00000440);
1212 msg[9] = cpu_to_le32(0x00000000);
1213 msg[10] = cpu_to_le32(0x01b37000);
1214 for (i = 11; i < 1024; ++i)
1215 msg[i] = cpu_to_le32(0x0);
1217 return amdgpu_uvd_send_msg(ring, bo, true, fence);
1221 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1222 bool direct, struct dma_fence **fence)
1224 struct amdgpu_device *adev = ring->adev;
1225 struct amdgpu_bo *bo = NULL;
1230 bo = adev->uvd.ib_bo;
1232 r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo);
1237 msg = amdgpu_bo_kptr(bo);
1238 /* stitch together an UVD destroy msg */
1239 msg[0] = cpu_to_le32(0x00000de4);
1240 msg[1] = cpu_to_le32(0x00000002);
1241 msg[2] = cpu_to_le32(handle);
1242 msg[3] = cpu_to_le32(0x00000000);
1243 for (i = 4; i < 1024; ++i)
1244 msg[i] = cpu_to_le32(0x0);
1246 r = amdgpu_uvd_send_msg(ring, bo, direct, fence);
1249 amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
1254 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1256 struct amdgpu_device *adev =
1257 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1258 unsigned fences = 0, i, j;
1260 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1261 if (adev->uvd.harvest_config & (1 << i))
1263 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);
1264 for (j = 0; j < adev->uvd.num_enc_rings; ++j) {
1265 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);
1270 if (adev->pm.dpm_enabled) {
1271 amdgpu_dpm_enable_uvd(adev, false);
1273 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1274 /* shutdown the UVD block */
1275 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1277 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1281 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1285 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1287 struct amdgpu_device *adev = ring->adev;
1290 if (amdgpu_sriov_vf(adev))
1293 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1295 if (adev->pm.dpm_enabled) {
1296 amdgpu_dpm_enable_uvd(adev, true);
1298 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1299 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1300 AMD_CG_STATE_UNGATE);
1301 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1302 AMD_PG_STATE_UNGATE);
1307 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1309 if (!amdgpu_sriov_vf(ring->adev))
1310 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1314 * amdgpu_uvd_ring_test_ib - test ib execution
1316 * @ring: amdgpu_ring pointer
1317 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1319 * Test if we can successfully execute an IB
1321 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1323 struct dma_fence *fence;
1326 r = amdgpu_uvd_get_create_msg(ring, 1, &fence);
1330 r = dma_fence_wait_timeout(fence, false, timeout);
1331 dma_fence_put(fence);
1337 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1341 r = dma_fence_wait_timeout(fence, false, timeout);
1347 dma_fence_put(fence);
1354 * amdgpu_uvd_used_handles - returns used UVD handles
1356 * @adev: amdgpu_device pointer
1358 * Returns the number of UVD handles in use
1360 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)
1363 uint32_t used_handles = 0;
1365 for (i = 0; i < adev->uvd.max_handles; ++i) {
1367 * Handles can be freed in any order, and not
1368 * necessarily linear. So we need to count
1369 * all non-zero handles.
1371 if (atomic_read(&adev->uvd.handles[i]))
1375 return used_handles;