drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50 #include <drm/ttm/ttm_page_alloc.h>
  51
  52 #include <drm/drm_debugfs.h>
  53 #include <drm/amdgpu_drm.h>
  54
  55 #include "amdgpu.h"
  56 #include "amdgpu_object.h"
  57 #include "amdgpu_trace.h"
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_sdma.h"
  60 #include "amdgpu_ras.h"
  61 #include "bif/bif_4_1_d.h"
  62
  63 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  64
  65
  66 /**
  67  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  68  * memory request.
  69  *
  70  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
  71  * @type: The type of memory requested
  72  * @man: The memory type manager for each domain
  73  *
  74  * This is called by ttm_bo_init_mm() when a buffer object is being
  75  * initialized.
  76  */
  77 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  78                                 struct ttm_mem_type_manager *man)
  79 {
  80         struct amdgpu_device *adev;
  81
  82         adev = amdgpu_ttm_adev(bdev);
  83
  84         switch (type) {
  85         case TTM_PL_SYSTEM:
  86                 /* System memory */
  87                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  88                 man->available_caching = TTM_PL_MASK_CACHING;
  89                 man->default_caching = TTM_PL_FLAG_CACHED;
  90                 break;
  91         case TTM_PL_TT:
  92                 /* GTT memory  */
  93                 man->func = &amdgpu_gtt_mgr_func;
  94                 man->gpu_offset = adev->gmc.gart_start;
  95                 man->available_caching = TTM_PL_MASK_CACHING;
  96                 man->default_caching = TTM_PL_FLAG_CACHED;
  97                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
  98                 break;
  99         case TTM_PL_VRAM:
 100                 /* "On-card" video ram */
 101                 man->func = &amdgpu_vram_mgr_func;
 102                 man->gpu_offset = adev->gmc.vram_start;
 103                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 104                              TTM_MEMTYPE_FLAG_MAPPABLE;
 105                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 106                 man->default_caching = TTM_PL_FLAG_WC;
 107                 break;
 108         case AMDGPU_PL_GDS:
 109         case AMDGPU_PL_GWS:
 110         case AMDGPU_PL_OA:
 111                 /* On-chip GDS memory*/
 112                 man->func = &ttm_bo_manager_func;
 113                 man->gpu_offset = 0;
 114                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 115                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 116                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 117                 break;
 118         default:
 119                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 120                 return -EINVAL;
 121         }
 122         return 0;
 123 }
 124
 125 /**
 126  * amdgpu_evict_flags - Compute placement flags
 127  *
 128  * @bo: The buffer object to evict
 129  * @placement: Possible destination(s) for evicted BO
 130  *
 131  * Fill in placement data when ttm_bo_evict() is called
 132  */
 133 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 134                                 struct ttm_placement *placement)
 135 {
 136         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 137         struct amdgpu_bo *abo;
 138         static const struct ttm_place placements = {
 139                 .fpfn = 0,
 140                 .lpfn = 0,
 141                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 142         };
 143
 144         /* Don't handle scatter gather BOs */
 145         if (bo->type == ttm_bo_type_sg) {
 146                 placement->num_placement = 0;
 147                 placement->num_busy_placement = 0;
 148                 return;
 149         }
 150
 151         /* Object isn't an AMDGPU object so ignore */
 152         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 153                 placement->placement = &placements;
 154                 placement->busy_placement = &placements;
 155                 placement->num_placement = 1;
 156                 placement->num_busy_placement = 1;
 157                 return;
 158         }
 159
 160         abo = ttm_to_amdgpu_bo(bo);
 161         switch (bo->mem.mem_type) {
 162         case AMDGPU_PL_GDS:
 163         case AMDGPU_PL_GWS:
 164         case AMDGPU_PL_OA:
 165                 placement->num_placement = 0;
 166                 placement->num_busy_placement = 0;
 167                 return;
 168
 169         case TTM_PL_VRAM:
 170                 if (!adev->mman.buffer_funcs_enabled) {
 171                         /* Move to system memory */
 172                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 173                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 174                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 175                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 176
 177                         /* Try evicting to the CPU inaccessible part of VRAM
 178                          * first, but only set GTT as busy placement, so this
 179                          * BO will be evicted to GTT rather than causing other
 180                          * BOs to be evicted from VRAM
 181                          */
 182                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 183                                                          AMDGPU_GEM_DOMAIN_GTT);
 184                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 185                         abo->placements[0].lpfn = 0;
 186                         abo->placement.busy_placement = &abo->placements[1];
 187                         abo->placement.num_busy_placement = 1;
 188                 } else {
 189                         /* Move to GTT memory */
 190                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 191                 }
 192                 break;
 193         case TTM_PL_TT:
 194         default:
 195                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 196                 break;
 197         }
 198         *placement = abo->placement;
 199 }
 200
 201 /**
 202  * amdgpu_verify_access - Verify access for a mmap call
 203  *
 204  * @bo: The buffer object to map
 205  * @filp: The file pointer from the process performing the mmap
 206  *
 207  * This is called by ttm_bo_mmap() to verify whether a process
 208  * has the right to mmap a BO to their process space.
 209  */
 210 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 211 {
 212         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 213
 214         /*
 215          * Don't verify access for KFD BOs. They don't have a GEM
 216          * object associated with them.
 217          */
 218         if (abo->kfd_bo)
 219                 return 0;
 220
 221         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 222                 return -EPERM;
 223         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 224                                           filp->private_data);
 225 }
 226
 227 /**
 228  * amdgpu_move_null - Register memory for a buffer object
 229  *
 230  * @bo: The bo to assign the memory to
 231  * @new_mem: The memory to be assigned.
 232  *
 233  * Assign the memory from new_mem to the memory of the buffer object bo.
 234  */
 235 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 236                              struct ttm_mem_reg *new_mem)
 237 {
 238         struct ttm_mem_reg *old_mem = &bo->mem;
 239
 240         BUG_ON(old_mem->mm_node != NULL);
 241         *old_mem = *new_mem;
 242         new_mem->mm_node = NULL;
 243 }
 244
 245 /**
 246  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 247  *
 248  * @bo: The bo to assign the memory to.
 249  * @mm_node: Memory manager node for drm allocator.
 250  * @mem: The region where the bo resides.
 251  *
 252  */
 253 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 254                                     struct drm_mm_node *mm_node,
 255                                     struct ttm_mem_reg *mem)
 256 {
 257         uint64_t addr = 0;
 258
 259         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 260                 addr = mm_node->start << PAGE_SHIFT;
 261                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 262         }
 263         return addr;
 264 }
 265
 266 /**
 267  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 268  * @offset. It also modifies the offset to be within the drm_mm_node returned
 269  *
 270  * @mem: The region where the bo resides.
 271  * @offset: The offset that drm_mm_node is used for finding.
 272  *
 273  */
 274 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 275                                                uint64_t *offset)
 276 {
 277         struct drm_mm_node *mm_node = mem->mm_node;
 278
 279         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 280                 *offset -= (mm_node->size << PAGE_SHIFT);
 281                 ++mm_node;
 282         }
 283         return mm_node;
 284 }
 285
 286 /**
 287  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 288  * @bo: buffer object to map
 289  * @mem: memory object to map
 290  * @mm_node: drm_mm node object to map
 291  * @num_pages: number of pages to map
 292  * @offset: offset into @mm_node where to start
 293  * @window: which GART window to use
 294  * @ring: DMA ring to use for the copy
 295  * @tmz: if we should setup a TMZ enabled mapping
 296  * @addr: resulting address inside the MC address space
 297  *
 298  * Setup one of the GART windows to access a specific piece of memory or return
 299  * the physical address for local memory.
 300  */
 301 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 302                                  struct ttm_mem_reg *mem,
 303                                  struct drm_mm_node *mm_node,
 304                                  unsigned num_pages, uint64_t offset,
 305                                  unsigned window, struct amdgpu_ring *ring,
 306                                  bool tmz, uint64_t *addr)
 307 {
 308         struct amdgpu_device *adev = ring->adev;
 309         struct amdgpu_job *job;
 310         unsigned num_dw, num_bytes;
 311         struct dma_fence *fence;
 312         uint64_t src_addr, dst_addr;
 313         void *cpu_addr;
 314         uint64_t flags;
 315         unsigned int i;
 316         int r;
 317
 318         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 319                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 320
 321         /* Map only what can't be accessed directly */
 322         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 323                 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
 324                 return 0;
 325         }
 326
 327         *addr = adev->gmc.gart_start;
 328         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 329                 AMDGPU_GPU_PAGE_SIZE;
 330         *addr += offset & ~PAGE_MASK;
 331
 332         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 333         num_bytes = num_pages * 8;
 334
 335         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 336                                      AMDGPU_IB_POOL_NORMAL, &job);
 337         if (r)
 338                 return r;
 339
 340         src_addr = num_dw * 4;
 341         src_addr += job->ibs[0].gpu_addr;
 342
 343         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 344         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 345         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 346                                 dst_addr, num_bytes, false);
 347
 348         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 349         WARN_ON(job->ibs[0].length_dw > num_dw);
 350
 351         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 352         if (tmz)
 353                 flags |= AMDGPU_PTE_TMZ;
 354
 355         cpu_addr = &job->ibs[0].ptr[num_dw];
 356
 357         if (mem->mem_type == TTM_PL_TT) {
 358                 struct ttm_dma_tt *dma;
 359                 dma_addr_t *dma_address;
 360
 361                 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
 362                 dma_address = &dma->dma_address[offset >> PAGE_SHIFT];
 363                 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
 364                                     cpu_addr);
 365                 if (r)
 366                         goto error_free;
 367         } else {
 368                 dma_addr_t dma_address;
 369
 370                 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
 371                 dma_address += adev->vm_manager.vram_base_offset;
 372
 373                 for (i = 0; i < num_pages; ++i) {
 374                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 375                                             &dma_address, flags, cpu_addr);
 376                         if (r)
 377                                 goto error_free;
 378
 379                         dma_address += PAGE_SIZE;
 380                 }
 381         }
 382
 383         r = amdgpu_job_submit(job, &adev->mman.entity,
 384                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 385         if (r)
 386                 goto error_free;
 387
 388         dma_fence_put(fence);
 389
 390         return r;
 391
 392 error_free:
 393         amdgpu_job_free(job);
 394         return r;
 395 }
 396
 397 /**
 398  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 399  * @adev: amdgpu device
 400  * @src: buffer/address where to read from
 401  * @dst: buffer/address where to write to
 402  * @size: number of bytes to copy
 403  * @tmz: if a secure copy should be used
 404  * @resv: resv object to sync to
 405  * @f: Returns the last fence if multiple jobs are submitted.
 406  *
 407  * The function copies @size bytes from {src->mem + src->offset} to
 408  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 409  * move and different for a BO to BO copy.
 410  *
 411  */
 412 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 413                                const struct amdgpu_copy_mem *src,
 414                                const struct amdgpu_copy_mem *dst,
 415                                uint64_t size, bool tmz,
 416                                struct dma_resv *resv,
 417                                struct dma_fence **f)
 418 {
 419         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 420                                         AMDGPU_GPU_PAGE_SIZE);
 421
 422         uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
 423         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 424         struct drm_mm_node *src_mm, *dst_mm;
 425         struct dma_fence *fence = NULL;
 426         int r = 0;
 427
 428         if (!adev->mman.buffer_funcs_enabled) {
 429                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 430                 return -EINVAL;
 431         }
 432
 433         src_offset = src->offset;
 434         src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
 435         src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
 436
 437         dst_offset = dst->offset;
 438         dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
 439         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
 440
 441         mutex_lock(&adev->mman.gtt_window_lock);
 442
 443         while (size) {
 444                 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
 445                 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
 446                 struct dma_fence *next;
 447                 uint32_t cur_size;
 448                 uint64_t from, to;
 449
 450                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 451                  * begins at an offset, then adjust the size accordingly
 452                  */
 453                 cur_size = min3(src_node_size, dst_node_size, size);
 454                 cur_size = min(GTT_MAX_BYTES - src_page_offset, cur_size);
 455                 cur_size = min(GTT_MAX_BYTES - dst_page_offset, cur_size);
 456
 457                 /* Map src to window 0 and dst to window 1. */
 458                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
 459                                           PFN_UP(cur_size + src_page_offset),
 460                                           src_offset, 0, ring, tmz, &from);
 461                 if (r)
 462                         goto error;
 463
 464                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
 465                                           PFN_UP(cur_size + dst_page_offset),
 466                                           dst_offset, 1, ring, tmz, &to);
 467                 if (r)
 468                         goto error;
 469
 470                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 471                                        resv, &next, false, true, tmz);
 472                 if (r)
 473                         goto error;
 474
 475                 dma_fence_put(fence);
 476                 fence = next;
 477
 478                 size -= cur_size;
 479                 if (!size)
 480                         break;
 481
 482                 src_node_size -= cur_size;
 483                 if (!src_node_size) {
 484                         ++src_mm;
 485                         src_node_size = src_mm->size << PAGE_SHIFT;
 486                         src_offset = 0;
 487                 } else {
 488                         src_offset += cur_size;
 489                 }
 490
 491                 dst_node_size -= cur_size;
 492                 if (!dst_node_size) {
 493                         ++dst_mm;
 494                         dst_node_size = dst_mm->size << PAGE_SHIFT;
 495                         dst_offset = 0;
 496                 } else {
 497                         dst_offset += cur_size;
 498                 }
 499         }
 500 error:
 501         mutex_unlock(&adev->mman.gtt_window_lock);
 502         if (f)
 503                 *f = dma_fence_get(fence);
 504         dma_fence_put(fence);
 505         return r;
 506 }
 507
 508 /**
 509  * amdgpu_move_blit - Copy an entire buffer to another buffer
 510  *
 511  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 512  * help move buffers to and from VRAM.
 513  */
 514 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 515                             bool evict, bool no_wait_gpu,
 516                             struct ttm_mem_reg *new_mem,
 517                             struct ttm_mem_reg *old_mem)
 518 {
 519         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 520         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 521         struct amdgpu_copy_mem src, dst;
 522         struct dma_fence *fence = NULL;
 523         int r;
 524
 525         src.bo = bo;
 526         dst.bo = bo;
 527         src.mem = old_mem;
 528         dst.mem = new_mem;
 529         src.offset = 0;
 530         dst.offset = 0;
 531
 532         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 533                                        new_mem->num_pages << PAGE_SHIFT,
 534                                        amdgpu_bo_encrypted(abo),
 535                                        bo->base.resv, &fence);
 536         if (r)
 537                 goto error;
 538
 539         /* clear the space being freed */
 540         if (old_mem->mem_type == TTM_PL_VRAM &&
 541             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 542                 struct dma_fence *wipe_fence = NULL;
 543
 544                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 545                                        NULL, &wipe_fence);
 546                 if (r) {
 547                         goto error;
 548                 } else if (wipe_fence) {
 549                         dma_fence_put(fence);
 550                         fence = wipe_fence;
 551                 }
 552         }
 553
 554         /* Always block for VM page tables before committing the new location */
 555         if (bo->type == ttm_bo_type_kernel)
 556                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 557         else
 558                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 559         dma_fence_put(fence);
 560         return r;
 561
 562 error:
 563         if (fence)
 564                 dma_fence_wait(fence, false);
 565         dma_fence_put(fence);
 566         return r;
 567 }
 568
 569 /**
 570  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 571  *
 572  * Called by amdgpu_bo_move().
 573  */
 574 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 575                                 struct ttm_operation_ctx *ctx,
 576                                 struct ttm_mem_reg *new_mem)
 577 {
 578         struct ttm_mem_reg *old_mem = &bo->mem;
 579         struct ttm_mem_reg tmp_mem;
 580         struct ttm_place placements;
 581         struct ttm_placement placement;
 582         int r;
 583
 584         /* create space/pages for new_mem in GTT space */
 585         tmp_mem = *new_mem;
 586         tmp_mem.mm_node = NULL;
 587         placement.num_placement = 1;
 588         placement.placement = &placements;
 589         placement.num_busy_placement = 1;
 590         placement.busy_placement = &placements;
 591         placements.fpfn = 0;
 592         placements.lpfn = 0;
 593         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 594         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 595         if (unlikely(r)) {
 596                 pr_err("Failed to find GTT space for blit from VRAM\n");
 597                 return r;
 598         }
 599
 600         /* set caching flags */
 601         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 602         if (unlikely(r)) {
 603                 goto out_cleanup;
 604         }
 605
 606         /* Bind the memory to the GTT space */
 607         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 608         if (unlikely(r)) {
 609                 goto out_cleanup;
 610         }
 611
 612         /* blit VRAM to GTT */
 613         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 614         if (unlikely(r)) {
 615                 goto out_cleanup;
 616         }
 617
 618         /* move BO (in tmp_mem) to new_mem */
 619         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 620 out_cleanup:
 621         ttm_bo_mem_put(bo, &tmp_mem);
 622         return r;
 623 }
 624
 625 /**
 626  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 627  *
 628  * Called by amdgpu_bo_move().
 629  */
 630 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 631                                 struct ttm_operation_ctx *ctx,
 632                                 struct ttm_mem_reg *new_mem)
 633 {
 634         struct ttm_mem_reg *old_mem = &bo->mem;
 635         struct ttm_mem_reg tmp_mem;
 636         struct ttm_placement placement;
 637         struct ttm_place placements;
 638         int r;
 639
 640         /* make space in GTT for old_mem buffer */
 641         tmp_mem = *new_mem;
 642         tmp_mem.mm_node = NULL;
 643         placement.num_placement = 1;
 644         placement.placement = &placements;
 645         placement.num_busy_placement = 1;
 646         placement.busy_placement = &placements;
 647         placements.fpfn = 0;
 648         placements.lpfn = 0;
 649         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 650         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 651         if (unlikely(r)) {
 652                 pr_err("Failed to find GTT space for blit to VRAM\n");
 653                 return r;
 654         }
 655
 656         /* move/bind old memory to GTT space */
 657         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 658         if (unlikely(r)) {
 659                 goto out_cleanup;
 660         }
 661
 662         /* copy to VRAM */
 663         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 664         if (unlikely(r)) {
 665                 goto out_cleanup;
 666         }
 667 out_cleanup:
 668         ttm_bo_mem_put(bo, &tmp_mem);
 669         return r;
 670 }
 671
 672 /**
 673  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 674  *
 675  * Called by amdgpu_bo_move()
 676  */
 677 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 678                                struct ttm_mem_reg *mem)
 679 {
 680         struct drm_mm_node *nodes = mem->mm_node;
 681
 682         if (mem->mem_type == TTM_PL_SYSTEM ||
 683             mem->mem_type == TTM_PL_TT)
 684                 return true;
 685         if (mem->mem_type != TTM_PL_VRAM)
 686                 return false;
 687
 688         /* ttm_mem_reg_ioremap only supports contiguous memory */
 689         if (nodes->size != mem->num_pages)
 690                 return false;
 691
 692         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 693                 <= adev->gmc.visible_vram_size;
 694 }
 695
 696 /**
 697  * amdgpu_bo_move - Move a buffer object to a new memory location
 698  *
 699  * Called by ttm_bo_handle_move_mem()
 700  */
 701 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 702                           struct ttm_operation_ctx *ctx,
 703                           struct ttm_mem_reg *new_mem)
 704 {
 705         struct amdgpu_device *adev;
 706         struct amdgpu_bo *abo;
 707         struct ttm_mem_reg *old_mem = &bo->mem;
 708         int r;
 709
 710         /* Can't move a pinned BO */
 711         abo = ttm_to_amdgpu_bo(bo);
 712         if (WARN_ON_ONCE(abo->pin_count > 0))
 713                 return -EINVAL;
 714
 715         adev = amdgpu_ttm_adev(bo->bdev);
 716
 717         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 718                 amdgpu_move_null(bo, new_mem);
 719                 return 0;
 720         }
 721         if ((old_mem->mem_type == TTM_PL_TT &&
 722              new_mem->mem_type == TTM_PL_SYSTEM) ||
 723             (old_mem->mem_type == TTM_PL_SYSTEM &&
 724              new_mem->mem_type == TTM_PL_TT)) {
 725                 /* bind is enough */
 726                 amdgpu_move_null(bo, new_mem);
 727                 return 0;
 728         }
 729         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 730             old_mem->mem_type == AMDGPU_PL_GWS ||
 731             old_mem->mem_type == AMDGPU_PL_OA ||
 732             new_mem->mem_type == AMDGPU_PL_GDS ||
 733             new_mem->mem_type == AMDGPU_PL_GWS ||
 734             new_mem->mem_type == AMDGPU_PL_OA) {
 735                 /* Nothing to save here */
 736                 amdgpu_move_null(bo, new_mem);
 737                 return 0;
 738         }
 739
 740         if (!adev->mman.buffer_funcs_enabled) {
 741                 r = -ENODEV;
 742                 goto memcpy;
 743         }
 744
 745         if (old_mem->mem_type == TTM_PL_VRAM &&
 746             new_mem->mem_type == TTM_PL_SYSTEM) {
 747                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 748         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 749                    new_mem->mem_type == TTM_PL_VRAM) {
 750                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 751         } else {
 752                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 753                                      new_mem, old_mem);
 754         }
 755
 756         if (r) {
 757 memcpy:
 758                 /* Check that all memory is CPU accessible */
 759                 if (!amdgpu_mem_visible(adev, old_mem) ||
 760                     !amdgpu_mem_visible(adev, new_mem)) {
 761                         pr_err("Move buffer fallback to memcpy unavailable\n");
 762                         return r;
 763                 }
 764
 765                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 766                 if (r)
 767                         return r;
 768         }
 769
 770         if (bo->type == ttm_bo_type_device &&
 771             new_mem->mem_type == TTM_PL_VRAM &&
 772             old_mem->mem_type != TTM_PL_VRAM) {
 773                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 774                  * accesses the BO after it's moved.
 775                  */
 776                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 777         }
 778
 779         /* update statistics */
 780         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 781         return 0;
 782 }
 783
 784 /**
 785  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 786  *
 787  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 788  */
 789 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 790 {
 791         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 792         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 793         struct drm_mm_node *mm_node = mem->mm_node;
 794
 795         mem->bus.addr = NULL;
 796         mem->bus.offset = 0;
 797         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 798         mem->bus.base = 0;
 799         mem->bus.is_iomem = false;
 800         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 801                 return -EINVAL;
 802         switch (mem->mem_type) {
 803         case TTM_PL_SYSTEM:
 804                 /* system memory */
 805                 return 0;
 806         case TTM_PL_TT:
 807                 break;
 808         case TTM_PL_VRAM:
 809                 mem->bus.offset = mem->start << PAGE_SHIFT;
 810                 /* check if it's visible */
 811                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 812                         return -EINVAL;
 813                 /* Only physically contiguous buffers apply. In a contiguous
 814                  * buffer, size of the first mm_node would match the number of
 815                  * pages in ttm_mem_reg.
 816                  */
 817                 if (adev->mman.aper_base_kaddr &&
 818                     (mm_node->size == mem->num_pages))
 819                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 820                                         mem->bus.offset;
 821
 822                 mem->bus.base = adev->gmc.aper_base;
 823                 mem->bus.is_iomem = true;
 824                 break;
 825         default:
 826                 return -EINVAL;
 827         }
 828         return 0;
 829 }
 830
 831 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 832 {
 833 }
 834
 835 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 836                                            unsigned long page_offset)
 837 {
 838         uint64_t offset = (page_offset << PAGE_SHIFT);
 839         struct drm_mm_node *mm;
 840
 841         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 842         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 843                 (offset >> PAGE_SHIFT);
 844 }
 845
 846 /*
 847  * TTM backend functions.
 848  */
 849 struct amdgpu_ttm_tt {
 850         struct ttm_dma_tt       ttm;
 851         struct drm_gem_object   *gobj;
 852         u64                     offset;
 853         uint64_t                userptr;
 854         struct task_struct      *usertask;
 855         uint32_t                userflags;
 856 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 857         struct hmm_range        *range;
 858 #endif
 859 };
 860
 861 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 862 /* flags used by HMM internal, not related to CPU/GPU PTE flags */
 863 static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = {
 864         (1 << 0), /* HMM_PFN_VALID */
 865         (1 << 1), /* HMM_PFN_WRITE */
 866         0 /* HMM_PFN_DEVICE_PRIVATE */
 867 };
 868
 869 static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = {
 870         0xfffffffffffffffeUL, /* HMM_PFN_ERROR */
 871         0, /* HMM_PFN_NONE */
 872         0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */
 873 };
 874
 875 /**
 876  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 877  * memory and start HMM tracking CPU page table update
 878  *
 879  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 880  * once afterwards to stop HMM tracking
 881  */
 882 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 883 {
 884         struct ttm_tt *ttm = bo->tbo.ttm;
 885         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 886         unsigned long start = gtt->userptr;
 887         struct vm_area_struct *vma;
 888         struct hmm_range *range;
 889         unsigned long timeout;
 890         struct mm_struct *mm;
 891         unsigned long i;
 892         int r = 0;
 893
 894         mm = bo->notifier.mm;
 895         if (unlikely(!mm)) {
 896                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 897                 return -EFAULT;
 898         }
 899
 900         /* Another get_user_pages is running at the same time?? */
 901         if (WARN_ON(gtt->range))
 902                 return -EFAULT;
 903
 904         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 905                 return -ESRCH;
 906
 907         range = kzalloc(sizeof(*range), GFP_KERNEL);
 908         if (unlikely(!range)) {
 909                 r = -ENOMEM;
 910                 goto out;
 911         }
 912         range->notifier = &bo->notifier;
 913         range->flags = hmm_range_flags;
 914         range->values = hmm_range_values;
 915         range->pfn_shift = PAGE_SHIFT;
 916         range->start = bo->notifier.interval_tree.start;
 917         range->end = bo->notifier.interval_tree.last + 1;
 918         range->default_flags = hmm_range_flags[HMM_PFN_VALID];
 919         if (!amdgpu_ttm_tt_is_readonly(ttm))
 920                 range->default_flags |= range->flags[HMM_PFN_WRITE];
 921
 922         range->pfns = kvmalloc_array(ttm->num_pages, sizeof(*range->pfns),
 923                                      GFP_KERNEL);
 924         if (unlikely(!range->pfns)) {
 925                 r = -ENOMEM;
 926                 goto out_free_ranges;
 927         }
 928
 929         down_read(&mm->mmap_sem);
 930         vma = find_vma(mm, start);
 931         if (unlikely(!vma || start < vma->vm_start)) {
 932                 r = -EFAULT;
 933                 goto out_unlock;
 934         }
 935         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 936                 vma->vm_file)) {
 937                 r = -EPERM;
 938                 goto out_unlock;
 939         }
 940         up_read(&mm->mmap_sem);
 941         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 942
 943 retry:
 944         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 945
 946         down_read(&mm->mmap_sem);
 947         r = hmm_range_fault(range, 0);
 948         up_read(&mm->mmap_sem);
 949         if (unlikely(r <= 0)) {
 950                 /*
 951                  * FIXME: This timeout should encompass the retry from
 952                  * mmu_interval_read_retry() as well.
 953                  */
 954                 if ((r == 0 || r == -EBUSY) && !time_after(jiffies, timeout))
 955                         goto retry;
 956                 goto out_free_pfns;
 957         }
 958
 959         for (i = 0; i < ttm->num_pages; i++) {
 960                 /* FIXME: The pages cannot be touched outside the notifier_lock */
 961                 pages[i] = hmm_device_entry_to_page(range, range->pfns[i]);
 962                 if (unlikely(!pages[i])) {
 963                         pr_err("Page fault failed for pfn[%lu] = 0x%llx\n",
 964                                i, range->pfns[i]);
 965                         r = -ENOMEM;
 966
 967                         goto out_free_pfns;
 968                 }
 969         }
 970
 971         gtt->range = range;
 972         mmput(mm);
 973
 974         return 0;
 975
 976 out_unlock:
 977         up_read(&mm->mmap_sem);
 978 out_free_pfns:
 979         kvfree(range->pfns);
 980 out_free_ranges:
 981         kfree(range);
 982 out:
 983         mmput(mm);
 984         return r;
 985 }
 986
 987 /**
 988  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 989  * Check if the pages backing this ttm range have been invalidated
 990  *
 991  * Returns: true if pages are still valid
 992  */
 993 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 994 {
 995         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 996         bool r = false;
 997
 998         if (!gtt || !gtt->userptr)
 999                 return false;
1000
1001         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
1002                 gtt->userptr, ttm->num_pages);
1003
1004         WARN_ONCE(!gtt->range || !gtt->range->pfns,
1005                 "No user pages to check\n");
1006
1007         if (gtt->range) {
1008                 /*
1009                  * FIXME: Must always hold notifier_lock for this, and must
1010                  * not ignore the return code.
1011                  */
1012                 r = mmu_interval_read_retry(gtt->range->notifier,
1013                                          gtt->range->notifier_seq);
1014                 kvfree(gtt->range->pfns);
1015                 kfree(gtt->range);
1016                 gtt->range = NULL;
1017         }
1018
1019         return !r;
1020 }
1021 #endif
1022
1023 /**
1024  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
1025  *
1026  * Called by amdgpu_cs_list_validate(). This creates the page list
1027  * that backs user memory and will ultimately be mapped into the device
1028  * address space.
1029  */
1030 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
1031 {
1032         unsigned long i;
1033
1034         for (i = 0; i < ttm->num_pages; ++i)
1035                 ttm->pages[i] = pages ? pages[i] : NULL;
1036 }
1037
1038 /**
1039  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
1040  *
1041  * Called by amdgpu_ttm_backend_bind()
1042  **/
1043 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
1044 {
1045         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1046         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1047         unsigned nents;
1048         int r;
1049
1050         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1051         enum dma_data_direction direction = write ?
1052                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1053
1054         /* Allocate an SG array and squash pages into it */
1055         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
1056                                       ttm->num_pages << PAGE_SHIFT,
1057                                       GFP_KERNEL);
1058         if (r)
1059                 goto release_sg;
1060
1061         /* Map SG to device */
1062         r = -ENOMEM;
1063         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
1064         if (nents == 0)
1065                 goto release_sg;
1066
1067         /* convert SG to linear array of pages and dma addresses */
1068         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1069                                          gtt->ttm.dma_address, ttm->num_pages);
1070
1071         return 0;
1072
1073 release_sg:
1074         kfree(ttm->sg);
1075         return r;
1076 }
1077
1078 /**
1079  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1080  */
1081 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
1082 {
1083         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1084         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1085
1086         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1087         enum dma_data_direction direction = write ?
1088                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1089
1090         /* double check that we don't free the table twice */
1091         if (!ttm->sg->sgl)
1092                 return;
1093
1094         /* unmap the pages mapped to the device */
1095         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
1096
1097         sg_free_table(ttm->sg);
1098
1099 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1100         if (gtt->range) {
1101                 unsigned long i;
1102
1103                 for (i = 0; i < ttm->num_pages; i++) {
1104                         if (ttm->pages[i] !=
1105                                 hmm_device_entry_to_page(gtt->range,
1106                                               gtt->range->pfns[i]))
1107                                 break;
1108                 }
1109
1110                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1111         }
1112 #endif
1113 }
1114
1115 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1116                                 struct ttm_buffer_object *tbo,
1117                                 uint64_t flags)
1118 {
1119         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1120         struct ttm_tt *ttm = tbo->ttm;
1121         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1122         int r;
1123
1124         if (amdgpu_bo_encrypted(abo))
1125                 flags |= AMDGPU_PTE_TMZ;
1126
1127         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1128                 uint64_t page_idx = 1;
1129
1130                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1131                                 ttm->pages, gtt->ttm.dma_address, flags);
1132                 if (r)
1133                         goto gart_bind_fail;
1134
1135                 /* The memory type of the first page defaults to UC. Now
1136                  * modify the memory type to NC from the second page of
1137                  * the BO onward.
1138                  */
1139                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1140                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1141
1142                 r = amdgpu_gart_bind(adev,
1143                                 gtt->offset + (page_idx << PAGE_SHIFT),
1144                                 ttm->num_pages - page_idx,
1145                                 &ttm->pages[page_idx],
1146                                 &(gtt->ttm.dma_address[page_idx]), flags);
1147         } else {
1148                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1149                                      ttm->pages, gtt->ttm.dma_address, flags);
1150         }
1151
1152 gart_bind_fail:
1153         if (r)
1154                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1155                           ttm->num_pages, gtt->offset);
1156
1157         return r;
1158 }
1159
1160 /**
1161  * amdgpu_ttm_backend_bind - Bind GTT memory
1162  *
1163  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1164  * This handles binding GTT memory to the device address space.
1165  */
1166 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1167                                    struct ttm_mem_reg *bo_mem)
1168 {
1169         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1170         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1171         uint64_t flags;
1172         int r = 0;
1173
1174         if (gtt->userptr) {
1175                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1176                 if (r) {
1177                         DRM_ERROR("failed to pin userptr\n");
1178                         return r;
1179                 }
1180         }
1181         if (!ttm->num_pages) {
1182                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1183                      ttm->num_pages, bo_mem, ttm);
1184         }
1185
1186         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1187             bo_mem->mem_type == AMDGPU_PL_GWS ||
1188             bo_mem->mem_type == AMDGPU_PL_OA)
1189                 return -EINVAL;
1190
1191         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1192                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1193                 return 0;
1194         }
1195
1196         /* compute PTE flags relevant to this BO memory */
1197         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1198
1199         /* bind pages into GART page tables */
1200         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1201         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1202                 ttm->pages, gtt->ttm.dma_address, flags);
1203
1204         if (r)
1205                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1206                           ttm->num_pages, gtt->offset);
1207         return r;
1208 }
1209
1210 /**
1211  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1212  */
1213 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1214 {
1215         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1216         struct ttm_operation_ctx ctx = { false, false };
1217         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1218         struct ttm_mem_reg tmp;
1219         struct ttm_placement placement;
1220         struct ttm_place placements;
1221         uint64_t addr, flags;
1222         int r;
1223
1224         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1225                 return 0;
1226
1227         addr = amdgpu_gmc_agp_addr(bo);
1228         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1229                 bo->mem.start = addr >> PAGE_SHIFT;
1230         } else {
1231
1232                 /* allocate GART space */
1233                 tmp = bo->mem;
1234                 tmp.mm_node = NULL;
1235                 placement.num_placement = 1;
1236                 placement.placement = &placements;
1237                 placement.num_busy_placement = 1;
1238                 placement.busy_placement = &placements;
1239                 placements.fpfn = 0;
1240                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1241                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1242                         TTM_PL_FLAG_TT;
1243
1244                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1245                 if (unlikely(r))
1246                         return r;
1247
1248                 /* compute PTE flags for this buffer object */
1249                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1250
1251                 /* Bind pages */
1252                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1253                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1254                 if (unlikely(r)) {
1255                         ttm_bo_mem_put(bo, &tmp);
1256                         return r;
1257                 }
1258
1259                 ttm_bo_mem_put(bo, &bo->mem);
1260                 bo->mem = tmp;
1261         }
1262
1263         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1264                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1265
1266         return 0;
1267 }
1268
1269 /**
1270  * amdgpu_ttm_recover_gart - Rebind GTT pages
1271  *
1272  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1273  * rebind GTT pages during a GPU reset.
1274  */
1275 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1276 {
1277         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1278         uint64_t flags;
1279         int r;
1280
1281         if (!tbo->ttm)
1282                 return 0;
1283
1284         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1285         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1286
1287         return r;
1288 }
1289
1290 /**
1291  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1292  *
1293  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1294  * ttm_tt_destroy().
1295  */
1296 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1297 {
1298         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1299         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1300         int r;
1301
1302         /* if the pages have userptr pinning then clear that first */
1303         if (gtt->userptr)
1304                 amdgpu_ttm_tt_unpin_userptr(ttm);
1305
1306         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1307                 return 0;
1308
1309         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1310         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1311         if (r)
1312                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1313                           gtt->ttm.ttm.num_pages, gtt->offset);
1314         return r;
1315 }
1316
1317 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1318 {
1319         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1320
1321         if (gtt->usertask)
1322                 put_task_struct(gtt->usertask);
1323
1324         ttm_dma_tt_fini(&gtt->ttm);
1325         kfree(gtt);
1326 }
1327
1328 static struct ttm_backend_func amdgpu_backend_func = {
1329         .bind = &amdgpu_ttm_backend_bind,
1330         .unbind = &amdgpu_ttm_backend_unbind,
1331         .destroy = &amdgpu_ttm_backend_destroy,
1332 };
1333
1334 /**
1335  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1336  *
1337  * @bo: The buffer object to create a GTT ttm_tt object around
1338  *
1339  * Called by ttm_tt_create().
1340  */
1341 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1342                                            uint32_t page_flags)
1343 {
1344         struct amdgpu_ttm_tt *gtt;
1345
1346         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1347         if (gtt == NULL) {
1348                 return NULL;
1349         }
1350         gtt->ttm.ttm.func = &amdgpu_backend_func;
1351         gtt->gobj = &bo->base;
1352
1353         /* allocate space for the uninitialized page entries */
1354         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1355                 kfree(gtt);
1356                 return NULL;
1357         }
1358         return &gtt->ttm.ttm;
1359 }
1360
1361 /**
1362  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1363  *
1364  * Map the pages of a ttm_tt object to an address space visible
1365  * to the underlying device.
1366  */
1367 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1368                         struct ttm_operation_ctx *ctx)
1369 {
1370         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1371         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1372
1373         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1374         if (gtt && gtt->userptr) {
1375                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1376                 if (!ttm->sg)
1377                         return -ENOMEM;
1378
1379                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1380                 ttm->state = tt_unbound;
1381                 return 0;
1382         }
1383
1384         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1385                 if (!ttm->sg) {
1386                         struct dma_buf_attachment *attach;
1387                         struct sg_table *sgt;
1388
1389                         attach = gtt->gobj->import_attach;
1390                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1391                         if (IS_ERR(sgt))
1392                                 return PTR_ERR(sgt);
1393
1394                         ttm->sg = sgt;
1395                 }
1396
1397                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1398                                                  gtt->ttm.dma_address,
1399                                                  ttm->num_pages);
1400                 ttm->state = tt_unbound;
1401                 return 0;
1402         }
1403
1404 #ifdef CONFIG_SWIOTLB
1405         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1406                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1407         }
1408 #endif
1409
1410         /* fall back to generic helper to populate the page array
1411          * and map them to the device */
1412         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1413 }
1414
1415 /**
1416  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1417  *
1418  * Unmaps pages of a ttm_tt object from the device address space and
1419  * unpopulates the page array backing it.
1420  */
1421 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1422 {
1423         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1424         struct amdgpu_device *adev;
1425
1426         if (gtt && gtt->userptr) {
1427                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1428                 kfree(ttm->sg);
1429                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1430                 return;
1431         }
1432
1433         if (ttm->sg && gtt->gobj->import_attach) {
1434                 struct dma_buf_attachment *attach;
1435
1436                 attach = gtt->gobj->import_attach;
1437                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1438                 ttm->sg = NULL;
1439                 return;
1440         }
1441
1442         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1443                 return;
1444
1445         adev = amdgpu_ttm_adev(ttm->bdev);
1446
1447 #ifdef CONFIG_SWIOTLB
1448         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1449                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1450                 return;
1451         }
1452 #endif
1453
1454         /* fall back to generic helper to unmap and unpopulate array */
1455         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1456 }
1457
1458 /**
1459  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1460  * task
1461  *
1462  * @ttm: The ttm_tt object to bind this userptr object to
1463  * @addr:  The address in the current tasks VM space to use
1464  * @flags: Requirements of userptr object.
1465  *
1466  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1467  * to current task
1468  */
1469 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1470                               uint32_t flags)
1471 {
1472         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1473
1474         if (gtt == NULL)
1475                 return -EINVAL;
1476
1477         gtt->userptr = addr;
1478         gtt->userflags = flags;
1479
1480         if (gtt->usertask)
1481                 put_task_struct(gtt->usertask);
1482         gtt->usertask = current->group_leader;
1483         get_task_struct(gtt->usertask);
1484
1485         return 0;
1486 }
1487
1488 /**
1489  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1490  */
1491 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1492 {
1493         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1494
1495         if (gtt == NULL)
1496                 return NULL;
1497
1498         if (gtt->usertask == NULL)
1499                 return NULL;
1500
1501         return gtt->usertask->mm;
1502 }
1503
1504 /**
1505  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1506  * address range for the current task.
1507  *
1508  */
1509 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1510                                   unsigned long end)
1511 {
1512         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1513         unsigned long size;
1514
1515         if (gtt == NULL || !gtt->userptr)
1516                 return false;
1517
1518         /* Return false if no part of the ttm_tt object lies within
1519          * the range
1520          */
1521         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1522         if (gtt->userptr > end || gtt->userptr + size <= start)
1523                 return false;
1524
1525         return true;
1526 }
1527
1528 /**
1529  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1530  */
1531 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1532 {
1533         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1534
1535         if (gtt == NULL || !gtt->userptr)
1536                 return false;
1537
1538         return true;
1539 }
1540
1541 /**
1542  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1543  */
1544 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1545 {
1546         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1547
1548         if (gtt == NULL)
1549                 return false;
1550
1551         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1552 }
1553
1554 /**
1555  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1556  *
1557  * @ttm: The ttm_tt object to compute the flags for
1558  * @mem: The memory registry backing this ttm_tt object
1559  *
1560  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1561  */
1562 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1563 {
1564         uint64_t flags = 0;
1565
1566         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1567                 flags |= AMDGPU_PTE_VALID;
1568
1569         if (mem && mem->mem_type == TTM_PL_TT) {
1570                 flags |= AMDGPU_PTE_SYSTEM;
1571
1572                 if (ttm->caching_state == tt_cached)
1573                         flags |= AMDGPU_PTE_SNOOPED;
1574         }
1575
1576         return flags;
1577 }
1578
1579 /**
1580  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1581  *
1582  * @ttm: The ttm_tt object to compute the flags for
1583  * @mem: The memory registry backing this ttm_tt object
1584
1585  * Figure out the flags to use for a VM PTE (Page Table Entry).
1586  */
1587 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1588                                  struct ttm_mem_reg *mem)
1589 {
1590         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1591
1592         flags |= adev->gart.gart_pte_flags;
1593         flags |= AMDGPU_PTE_READABLE;
1594
1595         if (!amdgpu_ttm_tt_is_readonly(ttm))
1596                 flags |= AMDGPU_PTE_WRITEABLE;
1597
1598         return flags;
1599 }
1600
1601 /**
1602  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1603  * object.
1604  *
1605  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1606  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1607  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1608  * used to clean out a memory space.
1609  */
1610 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1611                                             const struct ttm_place *place)
1612 {
1613         unsigned long num_pages = bo->mem.num_pages;
1614         struct drm_mm_node *node = bo->mem.mm_node;
1615         struct dma_resv_list *flist;
1616         struct dma_fence *f;
1617         int i;
1618
1619         if (bo->type == ttm_bo_type_kernel &&
1620             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1621                 return false;
1622
1623         /* If bo is a KFD BO, check if the bo belongs to the current process.
1624          * If true, then return false as any KFD process needs all its BOs to
1625          * be resident to run successfully
1626          */
1627         flist = dma_resv_get_list(bo->base.resv);
1628         if (flist) {
1629                 for (i = 0; i < flist->shared_count; ++i) {
1630                         f = rcu_dereference_protected(flist->shared[i],
1631                                 dma_resv_held(bo->base.resv));
1632                         if (amdkfd_fence_check_mm(f, current->mm))
1633                                 return false;
1634                 }
1635         }
1636
1637         switch (bo->mem.mem_type) {
1638         case TTM_PL_TT:
1639                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1640                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1641                         return false;
1642                 return true;
1643
1644         case TTM_PL_VRAM:
1645                 /* Check each drm MM node individually */
1646                 while (num_pages) {
1647                         if (place->fpfn < (node->start + node->size) &&
1648                             !(place->lpfn && place->lpfn <= node->start))
1649                                 return true;
1650
1651                         num_pages -= node->size;
1652                         ++node;
1653                 }
1654                 return false;
1655
1656         default:
1657                 break;
1658         }
1659
1660         return ttm_bo_eviction_valuable(bo, place);
1661 }
1662
1663 /**
1664  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1665  *
1666  * @bo:  The buffer object to read/write
1667  * @offset:  Offset into buffer object
1668  * @buf:  Secondary buffer to write/read from
1669  * @len: Length in bytes of access
1670  * @write:  true if writing
1671  *
1672  * This is used to access VRAM that backs a buffer object via MMIO
1673  * access for debugging purposes.
1674  */
1675 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1676                                     unsigned long offset,
1677                                     void *buf, int len, int write)
1678 {
1679         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1680         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1681         struct drm_mm_node *nodes;
1682         uint32_t value = 0;
1683         int ret = 0;
1684         uint64_t pos;
1685         unsigned long flags;
1686
1687         if (bo->mem.mem_type != TTM_PL_VRAM)
1688                 return -EIO;
1689
1690         pos = offset;
1691         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1692         pos += (nodes->start << PAGE_SHIFT);
1693
1694         while (len && pos < adev->gmc.mc_vram_size) {
1695                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1696                 uint64_t bytes = 4 - (pos & 3);
1697                 uint32_t shift = (pos & 3) * 8;
1698                 uint32_t mask = 0xffffffff << shift;
1699
1700                 if (len < bytes) {
1701                         mask &= 0xffffffff >> (bytes - len) * 8;
1702                         bytes = len;
1703                 }
1704
1705                 if (mask != 0xffffffff) {
1706                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1707                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1708                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1709                         if (!write || mask != 0xffffffff)
1710                                 value = RREG32_NO_KIQ(mmMM_DATA);
1711                         if (write) {
1712                                 value &= ~mask;
1713                                 value |= (*(uint32_t *)buf << shift) & mask;
1714                                 WREG32_NO_KIQ(mmMM_DATA, value);
1715                         }
1716                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1717                         if (!write) {
1718                                 value = (value & mask) >> shift;
1719                                 memcpy(buf, &value, bytes);
1720                         }
1721                 } else {
1722                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1723                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1724
1725                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1726                                                   bytes, write);
1727                 }
1728
1729                 ret += bytes;
1730                 buf = (uint8_t *)buf + bytes;
1731                 pos += bytes;
1732                 len -= bytes;
1733                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1734                         ++nodes;
1735                         pos = (nodes->start << PAGE_SHIFT);
1736                 }
1737         }
1738
1739         return ret;
1740 }
1741
1742 static struct ttm_bo_driver amdgpu_bo_driver = {
1743         .ttm_tt_create = &amdgpu_ttm_tt_create,
1744         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1745         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1746         .init_mem_type = &amdgpu_init_mem_type,
1747         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1748         .evict_flags = &amdgpu_evict_flags,
1749         .move = &amdgpu_bo_move,
1750         .verify_access = &amdgpu_verify_access,
1751         .move_notify = &amdgpu_bo_move_notify,
1752         .release_notify = &amdgpu_bo_release_notify,
1753         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1754         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1755         .io_mem_free = &amdgpu_ttm_io_mem_free,
1756         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1757         .access_memory = &amdgpu_ttm_access_memory,
1758         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1759 };
1760
1761 /*
1762  * Firmware Reservation functions
1763  */
1764 /**
1765  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1766  *
1767  * @adev: amdgpu_device pointer
1768  *
1769  * free fw reserved vram if it has been reserved.
1770  */
1771 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1772 {
1773         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1774                 NULL, &adev->fw_vram_usage.va);
1775 }
1776
1777 /**
1778  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1779  *
1780  * @adev: amdgpu_device pointer
1781  *
1782  * create bo vram reservation from fw.
1783  */
1784 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1785 {
1786         uint64_t vram_size = adev->gmc.visible_vram_size;
1787
1788         adev->fw_vram_usage.va = NULL;
1789         adev->fw_vram_usage.reserved_bo = NULL;
1790
1791         if (adev->fw_vram_usage.size == 0 ||
1792             adev->fw_vram_usage.size > vram_size)
1793                 return 0;
1794
1795         return amdgpu_bo_create_kernel_at(adev,
1796                                           adev->fw_vram_usage.start_offset,
1797                                           adev->fw_vram_usage.size,
1798                                           AMDGPU_GEM_DOMAIN_VRAM,
1799                                           &adev->fw_vram_usage.reserved_bo,
1800                                           &adev->fw_vram_usage.va);
1801 }
1802
1803 /*
1804  * Memoy training reservation functions
1805  */
1806
1807 /**
1808  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1809  *
1810  * @adev: amdgpu_device pointer
1811  *
1812  * free memory training reserved vram if it has been reserved.
1813  */
1814 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1815 {
1816         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1817
1818         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1819         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1820         ctx->c2p_bo = NULL;
1821
1822         return 0;
1823 }
1824
1825 static u64 amdgpu_ttm_training_get_c2p_offset(u64 vram_size)
1826 {
1827        if ((vram_size & (SZ_1M - 1)) < (SZ_4K + 1) )
1828                vram_size -= SZ_1M;
1829
1830        return ALIGN(vram_size, SZ_1M);
1831 }
1832
1833 /**
1834  * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training
1835  *
1836  * @adev: amdgpu_device pointer
1837  *
1838  * create bo vram reservation from memory training.
1839  */
1840 static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
1841 {
1842         int ret;
1843         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1844
1845         memset(ctx, 0, sizeof(*ctx));
1846         if (!adev->fw_vram_usage.mem_train_support) {
1847                 DRM_DEBUG("memory training does not support!\n");
1848                 return 0;
1849         }
1850
1851         ctx->c2p_train_data_offset = amdgpu_ttm_training_get_c2p_offset(adev->gmc.mc_vram_size);
1852         ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1853         ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1854
1855         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1856                   ctx->train_data_size,
1857                   ctx->p2c_train_data_offset,
1858                   ctx->c2p_train_data_offset);
1859
1860         ret = amdgpu_bo_create_kernel_at(adev,
1861                                          ctx->c2p_train_data_offset,
1862                                          ctx->train_data_size,
1863                                          AMDGPU_GEM_DOMAIN_VRAM,
1864                                          &ctx->c2p_bo,
1865                                          NULL);
1866         if (ret) {
1867                 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1868                 amdgpu_ttm_training_reserve_vram_fini(adev);
1869                 return ret;
1870         }
1871
1872         ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1873         return 0;
1874 }
1875
1876 /**
1877  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1878  * gtt/vram related fields.
1879  *
1880  * This initializes all of the memory space pools that the TTM layer
1881  * will need such as the GTT space (system memory mapped to the device),
1882  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1883  * can be mapped per VMID.
1884  */
1885 int amdgpu_ttm_init(struct amdgpu_device *adev)
1886 {
1887         uint64_t gtt_size;
1888         int r;
1889         u64 vis_vram_limit;
1890         void *stolen_vga_buf;
1891
1892         mutex_init(&adev->mman.gtt_window_lock);
1893
1894         /* No others user of address space so set it to 0 */
1895         r = ttm_bo_device_init(&adev->mman.bdev,
1896                                &amdgpu_bo_driver,
1897                                adev->ddev->anon_inode->i_mapping,
1898                                adev->ddev->vma_offset_manager,
1899                                dma_addressing_limited(adev->dev));
1900         if (r) {
1901                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1902                 return r;
1903         }
1904         adev->mman.initialized = true;
1905
1906         /* We opt to avoid OOM on system pages allocations */
1907         adev->mman.bdev.no_retry = true;
1908
1909         /* Initialize VRAM pool with all of VRAM divided into pages */
1910         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1911                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1912         if (r) {
1913                 DRM_ERROR("Failed initializing VRAM heap.\n");
1914                 return r;
1915         }
1916
1917         /* Reduce size of CPU-visible VRAM if requested */
1918         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1919         if (amdgpu_vis_vram_limit > 0 &&
1920             vis_vram_limit <= adev->gmc.visible_vram_size)
1921                 adev->gmc.visible_vram_size = vis_vram_limit;
1922
1923         /* Change the size here instead of the init above so only lpfn is affected */
1924         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1925 #ifdef CONFIG_64BIT
1926         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1927                                                 adev->gmc.visible_vram_size);
1928 #endif
1929
1930         /*
1931          *The reserved vram for firmware must be pinned to the specified
1932          *place on the VRAM, so reserve it early.
1933          */
1934         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1935         if (r) {
1936                 return r;
1937         }
1938
1939         /*
1940          *The reserved vram for memory training must be pinned to the specified
1941          *place on the VRAM, so reserve it early.
1942          */
1943         if (!amdgpu_sriov_vf(adev)) {
1944                 r = amdgpu_ttm_training_reserve_vram_init(adev);
1945                 if (r)
1946                         return r;
1947         }
1948
1949         /* allocate memory as required for VGA
1950          * This is used for VGA emulation and pre-OS scanout buffers to
1951          * avoid display artifacts while transitioning between pre-OS
1952          * and driver.  */
1953         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1954                                     AMDGPU_GEM_DOMAIN_VRAM,
1955                                     &adev->stolen_vga_memory,
1956                                     NULL, &stolen_vga_buf);
1957         if (r)
1958                 return r;
1959
1960         /*
1961          * reserve one TMR (64K) memory at the top of VRAM which holds
1962          * IP Discovery data and is protected by PSP.
1963          */
1964         r = amdgpu_bo_create_kernel_at(adev,
1965                                        adev->gmc.real_vram_size - DISCOVERY_TMR_SIZE,
1966                                        DISCOVERY_TMR_SIZE,
1967                                        AMDGPU_GEM_DOMAIN_VRAM,
1968                                        &adev->discovery_memory,
1969                                        NULL);
1970         if (r)
1971                 return r;
1972
1973         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1974                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1975
1976         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1977          * or whatever the user passed on module init */
1978         if (amdgpu_gtt_size == -1) {
1979                 struct sysinfo si;
1980
1981                 si_meminfo(&si);
1982                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1983                                adev->gmc.mc_vram_size),
1984                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1985         }
1986         else
1987                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1988
1989         /* Initialize GTT memory pool */
1990         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1991         if (r) {
1992                 DRM_ERROR("Failed initializing GTT heap.\n");
1993                 return r;
1994         }
1995         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1996                  (unsigned)(gtt_size / (1024 * 1024)));
1997
1998         /* Initialize various on-chip memory pools */
1999         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
2000                            adev->gds.gds_size);
2001         if (r) {
2002                 DRM_ERROR("Failed initializing GDS heap.\n");
2003                 return r;
2004         }
2005
2006         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
2007                            adev->gds.gws_size);
2008         if (r) {
2009                 DRM_ERROR("Failed initializing gws heap.\n");
2010                 return r;
2011         }
2012
2013         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
2014                            adev->gds.oa_size);
2015         if (r) {
2016                 DRM_ERROR("Failed initializing oa heap.\n");
2017                 return r;
2018         }
2019
2020         return 0;
2021 }
2022
2023 /**
2024  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
2025  */
2026 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
2027 {
2028         void *stolen_vga_buf;
2029         /* return the VGA stolen memory (if any) back to VRAM */
2030         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
2031 }
2032
2033 /**
2034  * amdgpu_ttm_fini - De-initialize the TTM memory pools
2035  */
2036 void amdgpu_ttm_fini(struct amdgpu_device *adev)
2037 {
2038         if (!adev->mman.initialized)
2039                 return;
2040
2041         amdgpu_ttm_training_reserve_vram_fini(adev);
2042         /* return the IP Discovery TMR memory back to VRAM */
2043         amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
2044         amdgpu_ttm_fw_reserve_vram_fini(adev);
2045
2046         if (adev->mman.aper_base_kaddr)
2047                 iounmap(adev->mman.aper_base_kaddr);
2048         adev->mman.aper_base_kaddr = NULL;
2049
2050         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
2051         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
2052         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
2053         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
2054         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
2055         ttm_bo_device_release(&adev->mman.bdev);
2056         adev->mman.initialized = false;
2057         DRM_INFO("amdgpu: ttm finalized\n");
2058 }
2059
2060 /**
2061  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2062  *
2063  * @adev: amdgpu_device pointer
2064  * @enable: true when we can use buffer functions.
2065  *
2066  * Enable/disable use of buffer functions during suspend/resume. This should
2067  * only be called at bootup or when userspace isn't running.
2068  */
2069 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2070 {
2071         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
2072         uint64_t size;
2073         int r;
2074
2075         if (!adev->mman.initialized || adev->in_gpu_reset ||
2076             adev->mman.buffer_funcs_enabled == enable)
2077                 return;
2078
2079         if (enable) {
2080                 struct amdgpu_ring *ring;
2081                 struct drm_gpu_scheduler *sched;
2082
2083                 ring = adev->mman.buffer_funcs_ring;
2084                 sched = &ring->sched;
2085                 r = drm_sched_entity_init(&adev->mman.entity,
2086                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
2087                                           1, NULL);
2088                 if (r) {
2089                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2090                                   r);
2091                         return;
2092                 }
2093         } else {
2094                 drm_sched_entity_destroy(&adev->mman.entity);
2095                 dma_fence_put(man->move);
2096                 man->move = NULL;
2097         }
2098
2099         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2100         if (enable)
2101                 size = adev->gmc.real_vram_size;
2102         else
2103                 size = adev->gmc.visible_vram_size;
2104         man->size = size >> PAGE_SHIFT;
2105         adev->mman.buffer_funcs_enabled = enable;
2106 }
2107
2108 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2109 {
2110         struct drm_file *file_priv = filp->private_data;
2111         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
2112
2113         if (adev == NULL)
2114                 return -EINVAL;
2115
2116         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2117 }
2118
2119 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2120                        uint64_t dst_offset, uint32_t byte_count,
2121                        struct dma_resv *resv,
2122                        struct dma_fence **fence, bool direct_submit,
2123                        bool vm_needs_flush, bool tmz)
2124 {
2125         struct amdgpu_device *adev = ring->adev;
2126         struct amdgpu_job *job;
2127
2128         uint32_t max_bytes;
2129         unsigned num_loops, num_dw;
2130         unsigned i;
2131         int r;
2132
2133         if (direct_submit && !ring->sched.ready) {
2134                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2135                 return -EINVAL;
2136         }
2137
2138         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2139         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2140         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2141
2142         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4,
2143                         direct_submit ? AMDGPU_IB_POOL_DIRECT : AMDGPU_IB_POOL_NORMAL, &job);
2144         if (r)
2145                 return r;
2146
2147         if (vm_needs_flush) {
2148                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2149                 job->vm_needs_flush = true;
2150         }
2151         if (resv) {
2152                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2153                                      AMDGPU_SYNC_ALWAYS,
2154                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2155                 if (r) {
2156                         DRM_ERROR("sync failed (%d).\n", r);
2157                         goto error_free;
2158                 }
2159         }
2160
2161         for (i = 0; i < num_loops; i++) {
2162                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2163
2164                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2165                                         dst_offset, cur_size_in_bytes, tmz);
2166
2167                 src_offset += cur_size_in_bytes;
2168                 dst_offset += cur_size_in_bytes;
2169                 byte_count -= cur_size_in_bytes;
2170         }
2171
2172         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2173         WARN_ON(job->ibs[0].length_dw > num_dw);
2174         if (direct_submit)
2175                 r = amdgpu_job_submit_direct(job, ring, fence);
2176         else
2177                 r = amdgpu_job_submit(job, &adev->mman.entity,
2178                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2179         if (r)
2180                 goto error_free;
2181
2182         return r;
2183
2184 error_free:
2185         amdgpu_job_free(job);
2186         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2187         return r;
2188 }
2189
2190 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2191                        uint32_t src_data,
2192                        struct dma_resv *resv,
2193                        struct dma_fence **fence)
2194 {
2195         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2196         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2197         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2198
2199         struct drm_mm_node *mm_node;
2200         unsigned long num_pages;
2201         unsigned int num_loops, num_dw;
2202
2203         struct amdgpu_job *job;
2204         int r;
2205
2206         if (!adev->mman.buffer_funcs_enabled) {
2207                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2208                 return -EINVAL;
2209         }
2210
2211         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2212                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2213                 if (r)
2214                         return r;
2215         }
2216
2217         num_pages = bo->tbo.num_pages;
2218         mm_node = bo->tbo.mem.mm_node;
2219         num_loops = 0;
2220         while (num_pages) {
2221                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2222
2223                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2224                 num_pages -= mm_node->size;
2225                 ++mm_node;
2226         }
2227         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2228
2229         /* for IB padding */
2230         num_dw += 64;
2231
2232         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_NORMAL, &job);
2233         if (r)
2234                 return r;
2235
2236         if (resv) {
2237                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2238                                      AMDGPU_SYNC_ALWAYS,
2239                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2240                 if (r) {
2241                         DRM_ERROR("sync failed (%d).\n", r);
2242                         goto error_free;
2243                 }
2244         }
2245
2246         num_pages = bo->tbo.num_pages;
2247         mm_node = bo->tbo.mem.mm_node;
2248
2249         while (num_pages) {
2250                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2251                 uint64_t dst_addr;
2252
2253                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2254                 while (byte_count) {
2255                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2256                                                            max_bytes);
2257
2258                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2259                                                 dst_addr, cur_size_in_bytes);
2260
2261                         dst_addr += cur_size_in_bytes;
2262                         byte_count -= cur_size_in_bytes;
2263                 }
2264
2265                 num_pages -= mm_node->size;
2266                 ++mm_node;
2267         }
2268
2269         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2270         WARN_ON(job->ibs[0].length_dw > num_dw);
2271         r = amdgpu_job_submit(job, &adev->mman.entity,
2272                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2273         if (r)
2274                 goto error_free;
2275
2276         return 0;
2277
2278 error_free:
2279         amdgpu_job_free(job);
2280         return r;
2281 }
2282
2283 #if defined(CONFIG_DEBUG_FS)
2284
2285 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2286 {
2287         struct drm_info_node *node = (struct drm_info_node *)m->private;
2288         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2289         struct drm_device *dev = node->minor->dev;
2290         struct amdgpu_device *adev = dev->dev_private;
2291         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2292         struct drm_printer p = drm_seq_file_printer(m);
2293
2294         man->func->debug(man, &p);
2295         return 0;
2296 }
2297
2298 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2299         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2300         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2301         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2302         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2303         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2304         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2305 #ifdef CONFIG_SWIOTLB
2306         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2307 #endif
2308 };
2309
2310 /**
2311  * amdgpu_ttm_vram_read - Linear read access to VRAM
2312  *
2313  * Accesses VRAM via MMIO for debugging purposes.
2314  */
2315 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2316                                     size_t size, loff_t *pos)
2317 {
2318         struct amdgpu_device *adev = file_inode(f)->i_private;
2319         ssize_t result = 0;
2320
2321         if (size & 0x3 || *pos & 0x3)
2322                 return -EINVAL;
2323
2324         if (*pos >= adev->gmc.mc_vram_size)
2325                 return -ENXIO;
2326
2327         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2328         while (size) {
2329                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2330                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2331
2332                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2333                 if (copy_to_user(buf, value, bytes))
2334                         return -EFAULT;
2335
2336                 result += bytes;
2337                 buf += bytes;
2338                 *pos += bytes;
2339                 size -= bytes;
2340         }
2341
2342         return result;
2343 }
2344
2345 /**
2346  * amdgpu_ttm_vram_write - Linear write access to VRAM
2347  *
2348  * Accesses VRAM via MMIO for debugging purposes.
2349  */
2350 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2351                                     size_t size, loff_t *pos)
2352 {
2353         struct amdgpu_device *adev = file_inode(f)->i_private;
2354         ssize_t result = 0;
2355         int r;
2356
2357         if (size & 0x3 || *pos & 0x3)
2358                 return -EINVAL;
2359
2360         if (*pos >= adev->gmc.mc_vram_size)
2361                 return -ENXIO;
2362
2363         while (size) {
2364                 unsigned long flags;
2365                 uint32_t value;
2366
2367                 if (*pos >= adev->gmc.mc_vram_size)
2368                         return result;
2369
2370                 r = get_user(value, (uint32_t *)buf);
2371                 if (r)
2372                         return r;
2373
2374                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2375                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2376                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2377                 WREG32_NO_KIQ(mmMM_DATA, value);
2378                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2379
2380                 result += 4;
2381                 buf += 4;
2382                 *pos += 4;
2383                 size -= 4;
2384         }
2385
2386         return result;
2387 }
2388
2389 static const struct file_operations amdgpu_ttm_vram_fops = {
2390         .owner = THIS_MODULE,
2391         .read = amdgpu_ttm_vram_read,
2392         .write = amdgpu_ttm_vram_write,
2393         .llseek = default_llseek,
2394 };
2395
2396 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2397
2398 /**
2399  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2400  */
2401 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2402                                    size_t size, loff_t *pos)
2403 {
2404         struct amdgpu_device *adev = file_inode(f)->i_private;
2405         ssize_t result = 0;
2406         int r;
2407
2408         while (size) {
2409                 loff_t p = *pos / PAGE_SIZE;
2410                 unsigned off = *pos & ~PAGE_MASK;
2411                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2412                 struct page *page;
2413                 void *ptr;
2414
2415                 if (p >= adev->gart.num_cpu_pages)
2416                         return result;
2417
2418                 page = adev->gart.pages[p];
2419                 if (page) {
2420                         ptr = kmap(page);
2421                         ptr += off;
2422
2423                         r = copy_to_user(buf, ptr, cur_size);
2424                         kunmap(adev->gart.pages[p]);
2425                 } else
2426                         r = clear_user(buf, cur_size);
2427
2428                 if (r)
2429                         return -EFAULT;
2430
2431                 result += cur_size;
2432                 buf += cur_size;
2433                 *pos += cur_size;
2434                 size -= cur_size;
2435         }
2436
2437         return result;
2438 }
2439
2440 static const struct file_operations amdgpu_ttm_gtt_fops = {
2441         .owner = THIS_MODULE,
2442         .read = amdgpu_ttm_gtt_read,
2443         .llseek = default_llseek
2444 };
2445
2446 #endif
2447
2448 /**
2449  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2450  *
2451  * This function is used to read memory that has been mapped to the
2452  * GPU and the known addresses are not physical addresses but instead
2453  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2454  */
2455 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2456                                  size_t size, loff_t *pos)
2457 {
2458         struct amdgpu_device *adev = file_inode(f)->i_private;
2459         struct iommu_domain *dom;
2460         ssize_t result = 0;
2461         int r;
2462
2463         /* retrieve the IOMMU domain if any for this device */
2464         dom = iommu_get_domain_for_dev(adev->dev);
2465
2466         while (size) {
2467                 phys_addr_t addr = *pos & PAGE_MASK;
2468                 loff_t off = *pos & ~PAGE_MASK;
2469                 size_t bytes = PAGE_SIZE - off;
2470                 unsigned long pfn;
2471                 struct page *p;
2472                 void *ptr;
2473
2474                 bytes = bytes < size ? bytes : size;
2475
2476                 /* Translate the bus address to a physical address.  If
2477                  * the domain is NULL it means there is no IOMMU active
2478                  * and the address translation is the identity
2479                  */
2480                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2481
2482                 pfn = addr >> PAGE_SHIFT;
2483                 if (!pfn_valid(pfn))
2484                         return -EPERM;
2485
2486                 p = pfn_to_page(pfn);
2487                 if (p->mapping != adev->mman.bdev.dev_mapping)
2488                         return -EPERM;
2489
2490                 ptr = kmap(p);
2491                 r = copy_to_user(buf, ptr + off, bytes);
2492                 kunmap(p);
2493                 if (r)
2494                         return -EFAULT;
2495
2496                 size -= bytes;
2497                 *pos += bytes;
2498                 result += bytes;
2499         }
2500
2501         return result;
2502 }
2503
2504 /**
2505  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2506  *
2507  * This function is used to write memory that has been mapped to the
2508  * GPU and the known addresses are not physical addresses but instead
2509  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2510  */
2511 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2512                                  size_t size, loff_t *pos)
2513 {
2514         struct amdgpu_device *adev = file_inode(f)->i_private;
2515         struct iommu_domain *dom;
2516         ssize_t result = 0;
2517         int r;
2518
2519         dom = iommu_get_domain_for_dev(adev->dev);
2520
2521         while (size) {
2522                 phys_addr_t addr = *pos & PAGE_MASK;
2523                 loff_t off = *pos & ~PAGE_MASK;
2524                 size_t bytes = PAGE_SIZE - off;
2525                 unsigned long pfn;
2526                 struct page *p;
2527                 void *ptr;
2528
2529                 bytes = bytes < size ? bytes : size;
2530
2531                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2532
2533                 pfn = addr >> PAGE_SHIFT;
2534                 if (!pfn_valid(pfn))
2535                         return -EPERM;
2536
2537                 p = pfn_to_page(pfn);
2538                 if (p->mapping != adev->mman.bdev.dev_mapping)
2539                         return -EPERM;
2540
2541                 ptr = kmap(p);
2542                 r = copy_from_user(ptr + off, buf, bytes);
2543                 kunmap(p);
2544                 if (r)
2545                         return -EFAULT;
2546
2547                 size -= bytes;
2548                 *pos += bytes;
2549                 result += bytes;
2550         }
2551
2552         return result;
2553 }
2554
2555 static const struct file_operations amdgpu_ttm_iomem_fops = {
2556         .owner = THIS_MODULE,
2557         .read = amdgpu_iomem_read,
2558         .write = amdgpu_iomem_write,
2559         .llseek = default_llseek
2560 };
2561
2562 static const struct {
2563         char *name;
2564         const struct file_operations *fops;
2565         int domain;
2566 } ttm_debugfs_entries[] = {
2567         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2568 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2569         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2570 #endif
2571         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2572 };
2573
2574 #endif
2575
2576 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2577 {
2578 #if defined(CONFIG_DEBUG_FS)
2579         unsigned count;
2580
2581         struct drm_minor *minor = adev->ddev->primary;
2582         struct dentry *ent, *root = minor->debugfs_root;
2583
2584         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2585                 ent = debugfs_create_file(
2586                                 ttm_debugfs_entries[count].name,
2587                                 S_IFREG | S_IRUGO, root,
2588                                 adev,
2589                                 ttm_debugfs_entries[count].fops);
2590                 if (IS_ERR(ent))
2591                         return PTR_ERR(ent);
2592                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2593                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2594                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2595                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2596                 adev->mman.debugfs_entries[count] = ent;
2597         }
2598
2599         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2600
2601 #ifdef CONFIG_SWIOTLB
2602         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2603                 --count;
2604 #endif
2605
2606         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2607 #else
2608         return 0;
2609 #endif
2610 }