2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Christian König
24 #ifndef __AMDGPU_RING_H__
25 #define __AMDGPU_RING_H__
27 #include <drm/amdgpu_drm.h>
28 #include <drm/gpu_scheduler.h>
29 #include <drm/drm_print.h>
30 #include <drm/drm_suballoc.h>
35 struct amdgpu_cs_parser;
39 /* max number of rings */
40 #define AMDGPU_MAX_RINGS 28
41 #define AMDGPU_MAX_HWIP_RINGS 8
42 #define AMDGPU_MAX_GFX_RINGS 2
43 #define AMDGPU_MAX_SW_GFX_RINGS 2
44 #define AMDGPU_MAX_COMPUTE_RINGS 8
45 #define AMDGPU_MAX_VCE_RINGS 3
46 #define AMDGPU_MAX_UVD_ENC_RINGS 2
48 enum amdgpu_ring_priority_level {
51 AMDGPU_RING_PRIO_DEFAULT = 1,
56 /* some special values for the owner field */
57 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul)
58 #define AMDGPU_FENCE_OWNER_VM ((void *)1ul)
59 #define AMDGPU_FENCE_OWNER_KFD ((void *)2ul)
61 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
62 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
63 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
64 #define AMDGPU_FENCE_FLAG_EXEC (1 << 3)
66 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
68 #define AMDGPU_IB_POOL_SIZE (1024 * 1024)
70 enum amdgpu_ring_type {
71 AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX,
72 AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE,
73 AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA,
74 AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD,
75 AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE,
76 AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC,
77 AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC,
78 AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC,
79 AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG,
84 enum amdgpu_ib_pool_type {
85 /* Normal submissions to the top of the pipeline. */
86 AMDGPU_IB_POOL_DELAYED,
87 /* Immediate submissions to the bottom of the pipeline. */
88 AMDGPU_IB_POOL_IMMEDIATE,
89 /* Direct submission to the ring buffer during init and reset. */
90 AMDGPU_IB_POOL_DIRECT,
96 struct drm_suballoc *sa_bo;
103 struct amdgpu_sched {
105 struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS];
111 struct amdgpu_fence_driver {
113 volatile uint32_t *cpu_addr;
114 /* sync_seq is protected by ring emission lock */
118 struct amdgpu_irq_src *irq_src;
120 struct timer_list fallback_timer;
121 unsigned num_fences_mask;
123 struct dma_fence **fences;
126 extern const struct drm_sched_backend_ops amdgpu_sched_ops;
128 void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
129 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
131 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
132 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
133 struct amdgpu_irq_src *irq_src,
135 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev);
136 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev);
137 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev);
138 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev);
139 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, struct amdgpu_job *job,
141 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
143 bool amdgpu_fence_process(struct amdgpu_ring *ring);
144 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
145 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
147 signed long timeout);
148 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
150 void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop);
152 u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring);
153 void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq,
160 /* provided by hw blocks that expose a ring buffer for commands */
161 struct amdgpu_ring_funcs {
162 enum amdgpu_ring_type type;
165 bool support_64bit_ptrs;
167 bool secure_submission_supported;
170 /* ring read/write ptr handling */
171 u64 (*get_rptr)(struct amdgpu_ring *ring);
172 u64 (*get_wptr)(struct amdgpu_ring *ring);
173 void (*set_wptr)(struct amdgpu_ring *ring);
174 /* validating and patching of IBs */
175 int (*parse_cs)(struct amdgpu_cs_parser *p,
176 struct amdgpu_job *job,
177 struct amdgpu_ib *ib);
178 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p,
179 struct amdgpu_job *job,
180 struct amdgpu_ib *ib);
181 /* constants to calculate how many DW are needed for an emit */
182 unsigned emit_frame_size;
183 unsigned emit_ib_size;
184 /* command emit functions */
185 void (*emit_ib)(struct amdgpu_ring *ring,
186 struct amdgpu_job *job,
187 struct amdgpu_ib *ib,
189 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
190 uint64_t seq, unsigned flags);
191 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
192 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
194 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
195 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
196 uint32_t gds_base, uint32_t gds_size,
197 uint32_t gws_base, uint32_t gws_size,
198 uint32_t oa_base, uint32_t oa_size);
199 /* testing functions */
200 int (*test_ring)(struct amdgpu_ring *ring);
201 int (*test_ib)(struct amdgpu_ring *ring, long timeout);
202 /* insert NOP packets */
203 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
204 void (*insert_start)(struct amdgpu_ring *ring);
205 void (*insert_end)(struct amdgpu_ring *ring);
206 /* pad the indirect buffer to the necessary number of dw */
207 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
208 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
209 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
210 /* note usage for clock and power gating */
211 void (*begin_use)(struct amdgpu_ring *ring);
212 void (*end_use)(struct amdgpu_ring *ring);
213 void (*emit_switch_buffer) (struct amdgpu_ring *ring);
214 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
215 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
216 uint32_t reg_val_offs);
217 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
218 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
219 uint32_t val, uint32_t mask);
220 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
221 uint32_t reg0, uint32_t reg1,
222 uint32_t ref, uint32_t mask);
223 void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start,
225 /* Try to soft recover the ring to make the fence signal */
226 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
227 int (*preempt_ib)(struct amdgpu_ring *ring);
228 void (*emit_mem_sync)(struct amdgpu_ring *ring);
229 void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
233 struct amdgpu_device *adev;
234 const struct amdgpu_ring_funcs *funcs;
235 struct amdgpu_fence_driver fence_drv;
236 struct drm_gpu_scheduler sched;
238 struct amdgpu_bo *ring_obj;
239 volatile uint32_t *ring;
242 volatile u32 *rptr_cpu_addr;
256 struct amdgpu_bo *mqd_obj;
257 uint64_t mqd_gpu_addr;
259 uint64_t eop_gpu_addr;
265 volatile u32 *wptr_cpu_addr;
268 volatile u32 *fence_cpu_addr;
269 uint64_t current_ctx;
272 unsigned trail_fence_offs;
273 u64 trail_fence_gpu_addr;
274 volatile u32 *trail_fence_cpu_addr;
275 unsigned cond_exe_offs;
276 u64 cond_exe_gpu_addr;
277 volatile u32 *cond_exe_cpu_addr;
280 struct dma_fence *vmid_wait;
281 bool has_compute_vm_bug;
284 unsigned num_hw_submission;
285 atomic_t *sched_score;
289 uint32_t hw_queue_id;
290 struct amdgpu_mes_ctx_data *mes_ctx;
293 unsigned int entry_index;
297 #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))
298 #define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib)))
299 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
300 #define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0)
301 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
302 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
303 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
304 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
305 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
306 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
307 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
308 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
309 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
310 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
311 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
312 #define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
313 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
314 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
315 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
316 #define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
317 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
318 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
319 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
320 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
322 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
323 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring);
324 void amdgpu_ring_ib_end(struct amdgpu_ring *ring);
326 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
327 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
328 void amdgpu_ring_commit(struct amdgpu_ring *ring);
329 void amdgpu_ring_undo(struct amdgpu_ring *ring);
330 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
331 unsigned int max_dw, struct amdgpu_irq_src *irq_src,
332 unsigned int irq_type, unsigned int hw_prio,
333 atomic_t *sched_score);
334 void amdgpu_ring_fini(struct amdgpu_ring *ring);
335 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
336 uint32_t reg0, uint32_t val0,
337 uint32_t reg1, uint32_t val1);
338 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
339 struct dma_fence *fence);
341 static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
344 *ring->cond_exe_cpu_addr = cond_exec;
347 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
350 while (i <= ring->buf_mask)
351 ring->ring[i++] = ring->funcs->nop;
355 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
357 if (ring->count_dw <= 0)
358 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
359 ring->ring[ring->wptr++ & ring->buf_mask] = v;
360 ring->wptr &= ring->ptr_mask;
364 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
365 void *src, int count_dw)
367 unsigned occupied, chunk1, chunk2;
370 if (unlikely(ring->count_dw < count_dw))
371 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
373 occupied = ring->wptr & ring->buf_mask;
374 dst = (void *)&ring->ring[occupied];
375 chunk1 = ring->buf_mask + 1 - occupied;
376 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
377 chunk2 = count_dw - chunk1;
382 memcpy(dst, src, chunk1);
386 dst = (void *)ring->ring;
387 memcpy(dst, src, chunk2);
390 ring->wptr += count_dw;
391 ring->wptr &= ring->ptr_mask;
392 ring->count_dw -= count_dw;
395 #define amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset) \
396 (ring->is_mes_queue && ring->mes_ctx ? \
397 (ring->mes_ctx->meta_data_gpu_addr + offset) : 0)
399 #define amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset) \
400 (ring->is_mes_queue && ring->mes_ctx ? \
401 (void *)((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : \
404 int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
406 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
407 struct amdgpu_ring *ring);
409 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring);
411 static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx)
416 static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx,
419 ib->ptr[idx] = value;
422 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
424 enum amdgpu_ib_pool_type pool,
425 struct amdgpu_ib *ib);
426 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
427 struct dma_fence *f);
428 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
429 struct amdgpu_ib *ibs, struct amdgpu_job *job,
430 struct dma_fence **f);
431 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
432 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
433 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);