drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König
  23  */
  24 #ifndef __AMDGPU_RING_H__
  25 #define __AMDGPU_RING_H__
  26
  27 #include <drm/amdgpu_drm.h>
  28 #include <drm/gpu_scheduler.h>
  29 #include <drm/drm_print.h>
  30 #include <drm/drm_suballoc.h>
  31
  32 struct amdgpu_device;
  33 struct amdgpu_ring;
  34 struct amdgpu_ib;
  35 struct amdgpu_cs_parser;
  36 struct amdgpu_job;
  37 struct amdgpu_vm;
  38
  39 /* max number of rings */
  40 #define AMDGPU_MAX_RINGS                28
  41 #define AMDGPU_MAX_HWIP_RINGS           8
  42 #define AMDGPU_MAX_GFX_RINGS            2
  43 #define AMDGPU_MAX_SW_GFX_RINGS         2
  44 #define AMDGPU_MAX_COMPUTE_RINGS        8
  45 #define AMDGPU_MAX_VCE_RINGS            3
  46 #define AMDGPU_MAX_UVD_ENC_RINGS        2
  47
  48 enum amdgpu_ring_priority_level {
  49         AMDGPU_RING_PRIO_0,
  50         AMDGPU_RING_PRIO_1,
  51         AMDGPU_RING_PRIO_DEFAULT = 1,
  52         AMDGPU_RING_PRIO_2,
  53         AMDGPU_RING_PRIO_MAX
  54 };
  55
  56 /* some special values for the owner field */
  57 #define AMDGPU_FENCE_OWNER_UNDEFINED    ((void *)0ul)
  58 #define AMDGPU_FENCE_OWNER_VM           ((void *)1ul)
  59 #define AMDGPU_FENCE_OWNER_KFD          ((void *)2ul)
  60
  61 #define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
  62 #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
  63 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)
  64 #define AMDGPU_FENCE_FLAG_EXEC          (1 << 3)
  65
  66 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
  67
  68 #define AMDGPU_IB_POOL_SIZE     (1024 * 1024)
  69
  70 enum amdgpu_ring_type {
  71         AMDGPU_RING_TYPE_GFX            = AMDGPU_HW_IP_GFX,
  72         AMDGPU_RING_TYPE_COMPUTE        = AMDGPU_HW_IP_COMPUTE,
  73         AMDGPU_RING_TYPE_SDMA           = AMDGPU_HW_IP_DMA,
  74         AMDGPU_RING_TYPE_UVD            = AMDGPU_HW_IP_UVD,
  75         AMDGPU_RING_TYPE_VCE            = AMDGPU_HW_IP_VCE,
  76         AMDGPU_RING_TYPE_UVD_ENC        = AMDGPU_HW_IP_UVD_ENC,
  77         AMDGPU_RING_TYPE_VCN_DEC        = AMDGPU_HW_IP_VCN_DEC,
  78         AMDGPU_RING_TYPE_VCN_ENC        = AMDGPU_HW_IP_VCN_ENC,
  79         AMDGPU_RING_TYPE_VCN_JPEG       = AMDGPU_HW_IP_VCN_JPEG,
  80         AMDGPU_RING_TYPE_KIQ,
  81         AMDGPU_RING_TYPE_MES
  82 };
  83
  84 enum amdgpu_ib_pool_type {
  85         /* Normal submissions to the top of the pipeline. */
  86         AMDGPU_IB_POOL_DELAYED,
  87         /* Immediate submissions to the bottom of the pipeline. */
  88         AMDGPU_IB_POOL_IMMEDIATE,
  89         /* Direct submission to the ring buffer during init and reset. */
  90         AMDGPU_IB_POOL_DIRECT,
  91
  92         AMDGPU_IB_POOL_MAX
  93 };
  94
  95 struct amdgpu_ib {
  96         struct drm_suballoc             *sa_bo;
  97         uint32_t                        length_dw;
  98         uint64_t                        gpu_addr;
  99         uint32_t                        *ptr;
 100         uint32_t                        flags;
 101 };
 102
 103 struct amdgpu_sched {
 104         u32                             num_scheds;
 105         struct drm_gpu_scheduler        *sched[AMDGPU_MAX_HWIP_RINGS];
 106 };
 107
 108 /*
 109  * Fences.
 110  */
 111 struct amdgpu_fence_driver {
 112         uint64_t                        gpu_addr;
 113         volatile uint32_t               *cpu_addr;
 114         /* sync_seq is protected by ring emission lock */
 115         uint32_t                        sync_seq;
 116         atomic_t                        last_seq;
 117         bool                            initialized;
 118         struct amdgpu_irq_src           *irq_src;
 119         unsigned                        irq_type;
 120         struct timer_list               fallback_timer;
 121         unsigned                        num_fences_mask;
 122         spinlock_t                      lock;
 123         struct dma_fence                **fences;
 124 };
 125
 126 extern const struct drm_sched_backend_ops amdgpu_sched_ops;
 127
 128 void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
 129 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
 130
 131 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
 132 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 133                                    struct amdgpu_irq_src *irq_src,
 134                                    unsigned irq_type);
 135 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev);
 136 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev);
 137 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev);
 138 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev);
 139 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, struct amdgpu_job *job,
 140                       unsigned flags);
 141 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
 142                               uint32_t timeout);
 143 bool amdgpu_fence_process(struct amdgpu_ring *ring);
 144 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
 145 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
 146                                       uint32_t wait_seq,
 147                                       signed long timeout);
 148 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
 149
 150 void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop);
 151
 152 u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring);
 153 void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq,
 154                                          ktime_t timestamp);
 155
 156 /*
 157  * Rings.
 158  */
 159
 160 /* provided by hw blocks that expose a ring buffer for commands */
 161 struct amdgpu_ring_funcs {
 162         enum amdgpu_ring_type   type;
 163         uint32_t                align_mask;
 164         u32                     nop;
 165         bool                    support_64bit_ptrs;
 166         bool                    no_user_fence;
 167         bool                    secure_submission_supported;
 168         unsigned                extra_dw;
 169
 170         /* ring read/write ptr handling */
 171         u64 (*get_rptr)(struct amdgpu_ring *ring);
 172         u64 (*get_wptr)(struct amdgpu_ring *ring);
 173         void (*set_wptr)(struct amdgpu_ring *ring);
 174         /* validating and patching of IBs */
 175         int (*parse_cs)(struct amdgpu_cs_parser *p,
 176                         struct amdgpu_job *job,
 177                         struct amdgpu_ib *ib);
 178         int (*patch_cs_in_place)(struct amdgpu_cs_parser *p,
 179                                  struct amdgpu_job *job,
 180                                  struct amdgpu_ib *ib);
 181         /* constants to calculate how many DW are needed for an emit */
 182         unsigned emit_frame_size;
 183         unsigned emit_ib_size;
 184         /* command emit functions */
 185         void (*emit_ib)(struct amdgpu_ring *ring,
 186                         struct amdgpu_job *job,
 187                         struct amdgpu_ib *ib,
 188                         uint32_t flags);
 189         void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
 190                            uint64_t seq, unsigned flags);
 191         void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
 192         void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
 193                               uint64_t pd_addr);
 194         void (*emit_hdp_flush)(struct amdgpu_ring *ring);
 195         void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
 196                                 uint32_t gds_base, uint32_t gds_size,
 197                                 uint32_t gws_base, uint32_t gws_size,
 198                                 uint32_t oa_base, uint32_t oa_size);
 199         /* testing functions */
 200         int (*test_ring)(struct amdgpu_ring *ring);
 201         int (*test_ib)(struct amdgpu_ring *ring, long timeout);
 202         /* insert NOP packets */
 203         void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
 204         void (*insert_start)(struct amdgpu_ring *ring);
 205         void (*insert_end)(struct amdgpu_ring *ring);
 206         /* pad the indirect buffer to the necessary number of dw */
 207         void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
 208         unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
 209         void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
 210         /* note usage for clock and power gating */
 211         void (*begin_use)(struct amdgpu_ring *ring);
 212         void (*end_use)(struct amdgpu_ring *ring);
 213         void (*emit_switch_buffer) (struct amdgpu_ring *ring);
 214         void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
 215         void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va,
 216                                 u64 gds_va, bool init_shadow, int vmid);
 217         void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
 218                           uint32_t reg_val_offs);
 219         void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
 220         void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
 221                               uint32_t val, uint32_t mask);
 222         void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
 223                                         uint32_t reg0, uint32_t reg1,
 224                                         uint32_t ref, uint32_t mask);
 225         void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start,
 226                                 bool secure);
 227         /* Try to soft recover the ring to make the fence signal */
 228         void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
 229         int (*preempt_ib)(struct amdgpu_ring *ring);
 230         void (*emit_mem_sync)(struct amdgpu_ring *ring);
 231         void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
 232 };
 233
 234 struct amdgpu_ring {
 235         struct amdgpu_device            *adev;
 236         const struct amdgpu_ring_funcs  *funcs;
 237         struct amdgpu_fence_driver      fence_drv;
 238         struct drm_gpu_scheduler        sched;
 239
 240         struct amdgpu_bo        *ring_obj;
 241         volatile uint32_t       *ring;
 242         unsigned                rptr_offs;
 243         u64                     rptr_gpu_addr;
 244         volatile u32            *rptr_cpu_addr;
 245         u64                     wptr;
 246         u64                     wptr_old;
 247         unsigned                ring_size;
 248         unsigned                max_dw;
 249         int                     count_dw;
 250         uint64_t                gpu_addr;
 251         uint64_t                ptr_mask;
 252         uint32_t                buf_mask;
 253         u32                     idx;
 254         u32                     xcc_id;
 255         u32                     me;
 256         u32                     pipe;
 257         u32                     queue;
 258         struct amdgpu_bo        *mqd_obj;
 259         uint64_t                mqd_gpu_addr;
 260         void                    *mqd_ptr;
 261         uint64_t                eop_gpu_addr;
 262         u32                     doorbell_index;
 263         bool                    use_doorbell;
 264         bool                    use_pollmem;
 265         unsigned                wptr_offs;
 266         u64                     wptr_gpu_addr;
 267         volatile u32            *wptr_cpu_addr;
 268         unsigned                fence_offs;
 269         u64                     fence_gpu_addr;
 270         volatile u32            *fence_cpu_addr;
 271         uint64_t                current_ctx;
 272         char                    name[16];
 273         u32                     trail_seq;
 274         unsigned                trail_fence_offs;
 275         u64                     trail_fence_gpu_addr;
 276         volatile u32            *trail_fence_cpu_addr;
 277         unsigned                cond_exe_offs;
 278         u64                     cond_exe_gpu_addr;
 279         volatile u32            *cond_exe_cpu_addr;
 280         unsigned                vm_hub;
 281         unsigned                vm_inv_eng;
 282         struct dma_fence        *vmid_wait;
 283         bool                    has_compute_vm_bug;
 284         bool                    no_scheduler;
 285         int                     hw_prio;
 286         unsigned                num_hw_submission;
 287         atomic_t                *sched_score;
 288
 289         /* used for mes */
 290         bool                    is_mes_queue;
 291         uint32_t                hw_queue_id;
 292         struct amdgpu_mes_ctx_data *mes_ctx;
 293
 294         bool            is_sw_ring;
 295         unsigned int    entry_index;
 296
 297 };
 298
 299 #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))
 300 #define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib)))
 301 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
 302 #define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0)
 303 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
 304 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
 305 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
 306 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
 307 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
 308 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
 309 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
 310 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
 311 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
 312 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
 313 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
 314 #define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v)))
 315 #define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
 316 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
 317 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
 318 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
 319 #define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
 320 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
 321 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
 322 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
 323 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
 324
 325 unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type);
 326 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
 327 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring);
 328 void amdgpu_ring_ib_end(struct amdgpu_ring *ring);
 329
 330 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
 331 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
 332 void amdgpu_ring_commit(struct amdgpu_ring *ring);
 333 void amdgpu_ring_undo(struct amdgpu_ring *ring);
 334 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 335                      unsigned int max_dw, struct amdgpu_irq_src *irq_src,
 336                      unsigned int irq_type, unsigned int hw_prio,
 337                      atomic_t *sched_score);
 338 void amdgpu_ring_fini(struct amdgpu_ring *ring);
 339 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
 340                                                 uint32_t reg0, uint32_t val0,
 341                                                 uint32_t reg1, uint32_t val1);
 342 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
 343                                struct dma_fence *fence);
 344
 345 static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
 346                                                         bool cond_exec)
 347 {
 348         *ring->cond_exe_cpu_addr = cond_exec;
 349 }
 350
 351 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
 352 {
 353         int i = 0;
 354         while (i <= ring->buf_mask)
 355                 ring->ring[i++] = ring->funcs->nop;
 356
 357 }
 358
 359 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
 360 {
 361         if (ring->count_dw <= 0)
 362                 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
 363         ring->ring[ring->wptr++ & ring->buf_mask] = v;
 364         ring->wptr &= ring->ptr_mask;
 365         ring->count_dw--;
 366 }
 367
 368 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
 369                                               void *src, int count_dw)
 370 {
 371         unsigned occupied, chunk1, chunk2;
 372         void *dst;
 373
 374         if (unlikely(ring->count_dw < count_dw))
 375                 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
 376
 377         occupied = ring->wptr & ring->buf_mask;
 378         dst = (void *)&ring->ring[occupied];
 379         chunk1 = ring->buf_mask + 1 - occupied;
 380         chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
 381         chunk2 = count_dw - chunk1;
 382         chunk1 <<= 2;
 383         chunk2 <<= 2;
 384
 385         if (chunk1)
 386                 memcpy(dst, src, chunk1);
 387
 388         if (chunk2) {
 389                 src += chunk1;
 390                 dst = (void *)ring->ring;
 391                 memcpy(dst, src, chunk2);
 392         }
 393
 394         ring->wptr += count_dw;
 395         ring->wptr &= ring->ptr_mask;
 396         ring->count_dw -= count_dw;
 397 }
 398
 399 #define amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset)                  \
 400         (ring->is_mes_queue && ring->mes_ctx ?                          \
 401          (ring->mes_ctx->meta_data_gpu_addr + offset) : 0)
 402
 403 #define amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset)                  \
 404         (ring->is_mes_queue && ring->mes_ctx ?                          \
 405          (void *)((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : \
 406          NULL)
 407
 408 int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
 409
 410 void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
 411                               struct amdgpu_ring *ring);
 412
 413 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring);
 414
 415 static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx)
 416 {
 417         return ib->ptr[idx];
 418 }
 419
 420 static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx,
 421                                        uint32_t value)
 422 {
 423         ib->ptr[idx] = value;
 424 }
 425
 426 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 427                   unsigned size,
 428                   enum amdgpu_ib_pool_type pool,
 429                   struct amdgpu_ib *ib);
 430 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
 431                     struct dma_fence *f);
 432 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 433                        struct amdgpu_ib *ibs, struct amdgpu_job *job,
 434                        struct dma_fence **f);
 435 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
 436 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
 437 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
 438
 439 #endif