drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drm_drv.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_xgmi.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v11_0_8.h"
  38 #include "psp_v12_0.h"
  39 #include "psp_v13_0.h"
  40 #include "psp_v13_0_4.h"
  41
  42 #include "amdgpu_ras.h"
  43 #include "amdgpu_securedisplay.h"
  44 #include "amdgpu_atomfirmware.h"
  45
  46 #define AMD_VBIOS_FILE_MAX_SIZE_B      (1024*1024*3)
  47
  48 static int psp_load_smu_fw(struct psp_context *psp);
  49 static int psp_rap_terminate(struct psp_context *psp);
  50 static int psp_securedisplay_terminate(struct psp_context *psp);
  51
  52 static int psp_ring_init(struct psp_context *psp,
  53                          enum psp_ring_type ring_type)
  54 {
  55         int ret = 0;
  56         struct psp_ring *ring;
  57         struct amdgpu_device *adev = psp->adev;
  58
  59         ring = &psp->km_ring;
  60
  61         ring->ring_type = ring_type;
  62
  63         /* allocate 4k Page of Local Frame Buffer memory for ring */
  64         ring->ring_size = 0x1000;
  65         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
  66                                       AMDGPU_GEM_DOMAIN_VRAM |
  67                                       AMDGPU_GEM_DOMAIN_GTT,
  68                                       &adev->firmware.rbuf,
  69                                       &ring->ring_mem_mc_addr,
  70                                       (void **)&ring->ring_mem);
  71         if (ret) {
  72                 ring->ring_size = 0;
  73                 return ret;
  74         }
  75
  76         return 0;
  77 }
  78
  79 /*
  80  * Due to DF Cstate management centralized to PMFW, the firmware
  81  * loading sequence will be updated as below:
  82  *   - Load KDB
  83  *   - Load SYS_DRV
  84  *   - Load tOS
  85  *   - Load PMFW
  86  *   - Setup TMR
  87  *   - Load other non-psp fw
  88  *   - Load ASD
  89  *   - Load XGMI/RAS/HDCP/DTM TA if any
  90  *
  91  * This new sequence is required for
  92  *   - Arcturus and onwards
  93  */
  94 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  95 {
  96         struct amdgpu_device *adev = psp->adev;
  97
  98         if (amdgpu_sriov_vf(adev)) {
  99                 psp->pmfw_centralized_cstate_management = false;
 100                 return;
 101         }
 102
 103         switch (adev->ip_versions[MP0_HWIP][0]) {
 104         case IP_VERSION(11, 0, 0):
 105         case IP_VERSION(11, 0, 4):
 106         case IP_VERSION(11, 0, 5):
 107         case IP_VERSION(11, 0, 7):
 108         case IP_VERSION(11, 0, 9):
 109         case IP_VERSION(11, 0, 11):
 110         case IP_VERSION(11, 0, 12):
 111         case IP_VERSION(11, 0, 13):
 112         case IP_VERSION(13, 0, 0):
 113         case IP_VERSION(13, 0, 2):
 114         case IP_VERSION(13, 0, 7):
 115                 psp->pmfw_centralized_cstate_management = true;
 116                 break;
 117         default:
 118                 psp->pmfw_centralized_cstate_management = false;
 119                 break;
 120         }
 121 }
 122
 123 static int psp_init_sriov_microcode(struct psp_context *psp)
 124 {
 125         struct amdgpu_device *adev = psp->adev;
 126         char ucode_prefix[30];
 127         int ret = 0;
 128
 129         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 130
 131         switch (adev->ip_versions[MP0_HWIP][0]) {
 132         case IP_VERSION(9, 0, 0):
 133         case IP_VERSION(11, 0, 7):
 134         case IP_VERSION(11, 0, 9):
 135                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 136                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 137                 break;
 138         case IP_VERSION(13, 0, 2):
 139                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 140                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 141                 ret &= psp_init_ta_microcode(psp, ucode_prefix);
 142                 break;
 143         case IP_VERSION(13, 0, 0):
 144                 adev->virt.autoload_ucode_id = 0;
 145                 break;
 146         case IP_VERSION(13, 0, 6):
 147                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 148                 break;
 149         case IP_VERSION(13, 0, 10):
 150                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
 151                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 152                 break;
 153         default:
 154                 return -EINVAL;
 155         }
 156         return ret;
 157 }
 158
 159 static int psp_early_init(void *handle)
 160 {
 161         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 162         struct psp_context *psp = &adev->psp;
 163
 164         switch (adev->ip_versions[MP0_HWIP][0]) {
 165         case IP_VERSION(9, 0, 0):
 166                 psp_v3_1_set_psp_funcs(psp);
 167                 psp->autoload_supported = false;
 168                 break;
 169         case IP_VERSION(10, 0, 0):
 170         case IP_VERSION(10, 0, 1):
 171                 psp_v10_0_set_psp_funcs(psp);
 172                 psp->autoload_supported = false;
 173                 break;
 174         case IP_VERSION(11, 0, 2):
 175         case IP_VERSION(11, 0, 4):
 176                 psp_v11_0_set_psp_funcs(psp);
 177                 psp->autoload_supported = false;
 178                 break;
 179         case IP_VERSION(11, 0, 0):
 180         case IP_VERSION(11, 0, 5):
 181         case IP_VERSION(11, 0, 9):
 182         case IP_VERSION(11, 0, 7):
 183         case IP_VERSION(11, 0, 11):
 184         case IP_VERSION(11, 5, 0):
 185         case IP_VERSION(11, 0, 12):
 186         case IP_VERSION(11, 0, 13):
 187                 psp_v11_0_set_psp_funcs(psp);
 188                 psp->autoload_supported = true;
 189                 break;
 190         case IP_VERSION(11, 0, 3):
 191         case IP_VERSION(12, 0, 1):
 192                 psp_v12_0_set_psp_funcs(psp);
 193                 break;
 194         case IP_VERSION(13, 0, 2):
 195         case IP_VERSION(13, 0, 6):
 196                 psp_v13_0_set_psp_funcs(psp);
 197                 break;
 198         case IP_VERSION(13, 0, 1):
 199         case IP_VERSION(13, 0, 3):
 200         case IP_VERSION(13, 0, 5):
 201         case IP_VERSION(13, 0, 8):
 202         case IP_VERSION(13, 0, 11):
 203                 psp_v13_0_set_psp_funcs(psp);
 204                 psp->autoload_supported = true;
 205                 break;
 206         case IP_VERSION(11, 0, 8):
 207                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 208                         psp_v11_0_8_set_psp_funcs(psp);
 209                         psp->autoload_supported = false;
 210                 }
 211                 break;
 212         case IP_VERSION(13, 0, 0):
 213         case IP_VERSION(13, 0, 7):
 214         case IP_VERSION(13, 0, 10):
 215                 psp_v13_0_set_psp_funcs(psp);
 216                 psp->autoload_supported = true;
 217                 break;
 218         case IP_VERSION(13, 0, 4):
 219                 psp_v13_0_4_set_psp_funcs(psp);
 220                 psp->autoload_supported = true;
 221                 break;
 222         default:
 223                 return -EINVAL;
 224         }
 225
 226         psp->adev = adev;
 227
 228         psp_check_pmfw_centralized_cstate_management(psp);
 229
 230         if (amdgpu_sriov_vf(adev))
 231                 return psp_init_sriov_microcode(psp);
 232         else
 233                 return psp_init_microcode(psp);
 234 }
 235
 236 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
 237 {
 238         amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
 239                               &mem_ctx->shared_buf);
 240         mem_ctx->shared_bo = NULL;
 241 }
 242
 243 static void psp_free_shared_bufs(struct psp_context *psp)
 244 {
 245         void *tmr_buf;
 246         void **pptr;
 247
 248         /* free TMR memory buffer */
 249         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 250         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 251         psp->tmr_bo = NULL;
 252
 253         /* free xgmi shared memory */
 254         psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
 255
 256         /* free ras shared memory */
 257         psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
 258
 259         /* free hdcp shared memory */
 260         psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
 261
 262         /* free dtm shared memory */
 263         psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
 264
 265         /* free rap shared memory */
 266         psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
 267
 268         /* free securedisplay shared memory */
 269         psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
 270
 271
 272 }
 273
 274 static void psp_memory_training_fini(struct psp_context *psp)
 275 {
 276         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 277
 278         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 279         kfree(ctx->sys_cache);
 280         ctx->sys_cache = NULL;
 281 }
 282
 283 static int psp_memory_training_init(struct psp_context *psp)
 284 {
 285         int ret;
 286         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 287
 288         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 289                 DRM_DEBUG("memory training is not supported!\n");
 290                 return 0;
 291         }
 292
 293         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 294         if (ctx->sys_cache == NULL) {
 295                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 296                 ret = -ENOMEM;
 297                 goto Err_out;
 298         }
 299
 300         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 301                   ctx->train_data_size,
 302                   ctx->p2c_train_data_offset,
 303                   ctx->c2p_train_data_offset);
 304         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 305         return 0;
 306
 307 Err_out:
 308         psp_memory_training_fini(psp);
 309         return ret;
 310 }
 311
 312 /*
 313  * Helper funciton to query psp runtime database entry
 314  *
 315  * @adev: amdgpu_device pointer
 316  * @entry_type: the type of psp runtime database entry
 317  * @db_entry: runtime database entry pointer
 318  *
 319  * Return false if runtime database doesn't exit or entry is invalid
 320  * or true if the specific database entry is found, and copy to @db_entry
 321  */
 322 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
 323                                      enum psp_runtime_entry_type entry_type,
 324                                      void *db_entry)
 325 {
 326         uint64_t db_header_pos, db_dir_pos;
 327         struct psp_runtime_data_header db_header = {0};
 328         struct psp_runtime_data_directory db_dir = {0};
 329         bool ret = false;
 330         int i;
 331
 332         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6))
 333                 return false;
 334
 335         db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
 336         db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
 337
 338         /* read runtime db header from vram */
 339         amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
 340                         sizeof(struct psp_runtime_data_header), false);
 341
 342         if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
 343                 /* runtime db doesn't exist, exit */
 344                 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
 345                 return false;
 346         }
 347
 348         /* read runtime database entry from vram */
 349         amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
 350                         sizeof(struct psp_runtime_data_directory), false);
 351
 352         if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
 353                 /* invalid db entry count, exit */
 354                 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
 355                 return false;
 356         }
 357
 358         /* look up for requested entry type */
 359         for (i = 0; i < db_dir.entry_count && !ret; i++) {
 360                 if (db_dir.entry_list[i].entry_type == entry_type) {
 361                         switch (entry_type) {
 362                         case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
 363                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
 364                                         /* invalid db entry size */
 365                                         dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
 366                                         return false;
 367                                 }
 368                                 /* read runtime database entry */
 369                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 370                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
 371                                 ret = true;
 372                                 break;
 373                         case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
 374                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
 375                                         /* invalid db entry size */
 376                                         dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
 377                                         return false;
 378                                 }
 379                                 /* read runtime database entry */
 380                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 381                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
 382                                 ret = true;
 383                                 break;
 384                         default:
 385                                 ret = false;
 386                                 break;
 387                         }
 388                 }
 389         }
 390
 391         return ret;
 392 }
 393
 394 static int psp_sw_init(void *handle)
 395 {
 396         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 397         struct psp_context *psp = &adev->psp;
 398         int ret;
 399         struct psp_runtime_boot_cfg_entry boot_cfg_entry;
 400         struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 401         struct psp_runtime_scpm_entry scpm_entry;
 402
 403         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 404         if (!psp->cmd) {
 405                 DRM_ERROR("Failed to allocate memory to command buffer!\n");
 406                 ret = -ENOMEM;
 407         }
 408
 409         adev->psp.xgmi_context.supports_extended_data =
 410                 !adev->gmc.xgmi.connected_to_cpu &&
 411                         adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
 412
 413         memset(&scpm_entry, 0, sizeof(scpm_entry));
 414         if ((psp_get_runtime_db_entry(adev,
 415                                 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
 416                                 &scpm_entry)) &&
 417             (scpm_entry.scpm_status != SCPM_DISABLE)) {
 418                 adev->scpm_enabled = true;
 419                 adev->scpm_status = scpm_entry.scpm_status;
 420         } else {
 421                 adev->scpm_enabled = false;
 422                 adev->scpm_status = SCPM_DISABLE;
 423         }
 424
 425         /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
 426
 427         memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
 428         if (psp_get_runtime_db_entry(adev,
 429                                 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
 430                                 &boot_cfg_entry)) {
 431                 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
 432                 if ((psp->boot_cfg_bitmask) &
 433                     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
 434                         /* If psp runtime database exists, then
 435                          * only enable two stage memory training
 436                          * when TWO_STAGE_DRAM_TRAINING bit is set
 437                          * in runtime database */
 438                         mem_training_ctx->enable_mem_training = true;
 439                 }
 440
 441         } else {
 442                 /* If psp runtime database doesn't exist or
 443                  * is invalid, force enable two stage memory
 444                  * training */
 445                 mem_training_ctx->enable_mem_training = true;
 446         }
 447
 448         if (mem_training_ctx->enable_mem_training) {
 449                 ret = psp_memory_training_init(psp);
 450                 if (ret) {
 451                         DRM_ERROR("Failed to initialize memory training!\n");
 452                         return ret;
 453                 }
 454
 455                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 456                 if (ret) {
 457                         DRM_ERROR("Failed to process memory training!\n");
 458                         return ret;
 459                 }
 460         }
 461
 462         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 463                                       amdgpu_sriov_vf(adev) ?
 464                                       AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 465                                       &psp->fw_pri_bo,
 466                                       &psp->fw_pri_mc_addr,
 467                                       &psp->fw_pri_buf);
 468         if (ret)
 469                 return ret;
 470
 471         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 472                                       AMDGPU_GEM_DOMAIN_VRAM |
 473                                       AMDGPU_GEM_DOMAIN_GTT,
 474                                       &psp->fence_buf_bo,
 475                                       &psp->fence_buf_mc_addr,
 476                                       &psp->fence_buf);
 477         if (ret)
 478                 goto failed1;
 479
 480         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 481                                       AMDGPU_GEM_DOMAIN_VRAM |
 482                                       AMDGPU_GEM_DOMAIN_GTT,
 483                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 484                                       (void **)&psp->cmd_buf_mem);
 485         if (ret)
 486                 goto failed2;
 487
 488         return 0;
 489
 490 failed2:
 491         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 492                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 493 failed1:
 494         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 495                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 496         return ret;
 497 }
 498
 499 static int psp_sw_fini(void *handle)
 500 {
 501         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 502         struct psp_context *psp = &adev->psp;
 503         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 504
 505         psp_memory_training_fini(psp);
 506
 507         amdgpu_ucode_release(&psp->sos_fw);
 508         amdgpu_ucode_release(&psp->asd_fw);
 509         amdgpu_ucode_release(&psp->ta_fw);
 510         amdgpu_ucode_release(&psp->cap_fw);
 511         amdgpu_ucode_release(&psp->toc_fw);
 512
 513         kfree(cmd);
 514         cmd = NULL;
 515
 516         psp_free_shared_bufs(psp);
 517
 518         if (psp->km_ring.ring_mem)
 519                 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 520                                       &psp->km_ring.ring_mem_mc_addr,
 521                                       (void **)&psp->km_ring.ring_mem);
 522
 523         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 524                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 525         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 526                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 527         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 528                               (void **)&psp->cmd_buf_mem);
 529
 530         return 0;
 531 }
 532
 533 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 534                  uint32_t reg_val, uint32_t mask, bool check_changed)
 535 {
 536         uint32_t val;
 537         int i;
 538         struct amdgpu_device *adev = psp->adev;
 539
 540         if (psp->adev->no_hw_access)
 541                 return 0;
 542
 543         for (i = 0; i < adev->usec_timeout; i++) {
 544                 val = RREG32(reg_index);
 545                 if (check_changed) {
 546                         if (val != reg_val)
 547                                 return 0;
 548                 } else {
 549                         if ((val & mask) == reg_val)
 550                                 return 0;
 551                 }
 552                 udelay(1);
 553         }
 554
 555         return -ETIME;
 556 }
 557
 558 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
 559                                uint32_t reg_val, uint32_t mask, uint32_t msec_timeout)
 560 {
 561         uint32_t val;
 562         int i;
 563         struct amdgpu_device *adev = psp->adev;
 564
 565         if (psp->adev->no_hw_access)
 566                 return 0;
 567
 568         for (i = 0; i < msec_timeout; i++) {
 569                 val = RREG32(reg_index);
 570                 if ((val & mask) == reg_val)
 571                         return 0;
 572                 msleep(1);
 573         }
 574
 575         return -ETIME;
 576 }
 577
 578 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
 579 {
 580         switch (cmd_id) {
 581         case GFX_CMD_ID_LOAD_TA:
 582                 return "LOAD_TA";
 583         case GFX_CMD_ID_UNLOAD_TA:
 584                 return "UNLOAD_TA";
 585         case GFX_CMD_ID_INVOKE_CMD:
 586                 return "INVOKE_CMD";
 587         case GFX_CMD_ID_LOAD_ASD:
 588                 return "LOAD_ASD";
 589         case GFX_CMD_ID_SETUP_TMR:
 590                 return "SETUP_TMR";
 591         case GFX_CMD_ID_LOAD_IP_FW:
 592                 return "LOAD_IP_FW";
 593         case GFX_CMD_ID_DESTROY_TMR:
 594                 return "DESTROY_TMR";
 595         case GFX_CMD_ID_SAVE_RESTORE:
 596                 return "SAVE_RESTORE_IP_FW";
 597         case GFX_CMD_ID_SETUP_VMR:
 598                 return "SETUP_VMR";
 599         case GFX_CMD_ID_DESTROY_VMR:
 600                 return "DESTROY_VMR";
 601         case GFX_CMD_ID_PROG_REG:
 602                 return "PROG_REG";
 603         case GFX_CMD_ID_GET_FW_ATTESTATION:
 604                 return "GET_FW_ATTESTATION";
 605         case GFX_CMD_ID_LOAD_TOC:
 606                 return "ID_LOAD_TOC";
 607         case GFX_CMD_ID_AUTOLOAD_RLC:
 608                 return "AUTOLOAD_RLC";
 609         case GFX_CMD_ID_BOOT_CFG:
 610                 return "BOOT_CFG";
 611         default:
 612                 return "UNKNOWN CMD";
 613         }
 614 }
 615
 616 static int
 617 psp_cmd_submit_buf(struct psp_context *psp,
 618                    struct amdgpu_firmware_info *ucode,
 619                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 620 {
 621         int ret;
 622         int index;
 623         int timeout = 20000;
 624         bool ras_intr = false;
 625         bool skip_unsupport = false;
 626
 627         if (psp->adev->no_hw_access)
 628                 return 0;
 629
 630         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 631
 632         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 633
 634         index = atomic_inc_return(&psp->fence_value);
 635         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 636         if (ret) {
 637                 atomic_dec(&psp->fence_value);
 638                 goto exit;
 639         }
 640
 641         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 642         while (*((unsigned int *)psp->fence_buf) != index) {
 643                 if (--timeout == 0)
 644                         break;
 645                 /*
 646                  * Shouldn't wait for timeout when err_event_athub occurs,
 647                  * because gpu reset thread triggered and lock resource should
 648                  * be released for psp resume sequence.
 649                  */
 650                 ras_intr = amdgpu_ras_intr_triggered();
 651                 if (ras_intr)
 652                         break;
 653                 usleep_range(10, 100);
 654                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 655         }
 656
 657         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 658         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 659                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 660
 661         memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 662
 663         /* In some cases, psp response status is not 0 even there is no
 664          * problem while the command is submitted. Some version of PSP FW
 665          * doesn't write 0 to that field.
 666          * So here we would like to only print a warning instead of an error
 667          * during psp initialization to avoid breaking hw_init and it doesn't
 668          * return -EINVAL.
 669          */
 670         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 671                 if (ucode)
 672                         DRM_WARN("failed to load ucode %s(0x%X) ",
 673                                   amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
 674                 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
 675                          psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
 676                          psp->cmd_buf_mem->resp.status);
 677                 /* If any firmware (including CAP) load fails under SRIOV, it should
 678                  * return failure to stop the VF from initializing.
 679                  * Also return failure in case of timeout
 680                  */
 681                 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
 682                         ret = -EINVAL;
 683                         goto exit;
 684                 }
 685         }
 686
 687         if (ucode) {
 688                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 689                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 690         }
 691
 692 exit:
 693         return ret;
 694 }
 695
 696 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
 697 {
 698         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 699
 700         mutex_lock(&psp->mutex);
 701
 702         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 703
 704         return cmd;
 705 }
 706
 707 static void release_psp_cmd_buf(struct psp_context *psp)
 708 {
 709         mutex_unlock(&psp->mutex);
 710 }
 711
 712 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 713                                  struct psp_gfx_cmd_resp *cmd,
 714                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 715 {
 716         struct amdgpu_device *adev = psp->adev;
 717         uint32_t size = 0;
 718         uint64_t tmr_pa = 0;
 719
 720         if (tmr_bo) {
 721                 size = amdgpu_bo_size(tmr_bo);
 722                 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 723         }
 724
 725         if (amdgpu_sriov_vf(psp->adev))
 726                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 727         else
 728                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 729         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 730         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 731         cmd->cmd.cmd_setup_tmr.buf_size = size;
 732         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 733         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 734         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 735 }
 736
 737 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 738                                       uint64_t pri_buf_mc, uint32_t size)
 739 {
 740         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 741         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 742         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 743         cmd->cmd.cmd_load_toc.toc_size = size;
 744 }
 745
 746 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 747 static int psp_load_toc(struct psp_context *psp,
 748                         uint32_t *tmr_size)
 749 {
 750         int ret;
 751         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 752
 753         /* Copy toc to psp firmware private buffer */
 754         psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
 755
 756         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
 757
 758         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 759                                  psp->fence_buf_mc_addr);
 760         if (!ret)
 761                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 762
 763         release_psp_cmd_buf(psp);
 764
 765         return ret;
 766 }
 767
 768 static bool psp_boottime_tmr(struct psp_context *psp)
 769 {
 770         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 771         case IP_VERSION(13, 0, 6):
 772                 return true;
 773         default:
 774                 return false;
 775         }
 776 }
 777
 778 /* Set up Trusted Memory Region */
 779 static int psp_tmr_init(struct psp_context *psp)
 780 {
 781         int ret = 0;
 782         int tmr_size;
 783         void *tmr_buf;
 784         void **pptr;
 785
 786         /*
 787          * According to HW engineer, they prefer the TMR address be "naturally
 788          * aligned" , e.g. the start address be an integer divide of TMR size.
 789          *
 790          * Note: this memory need be reserved till the driver
 791          * uninitializes.
 792          */
 793         tmr_size = PSP_TMR_SIZE(psp->adev);
 794
 795         /* For ASICs support RLC autoload, psp will parse the toc
 796          * and calculate the total size of TMR needed */
 797         if (!amdgpu_sriov_vf(psp->adev) &&
 798             psp->toc.start_addr &&
 799             psp->toc.size_bytes &&
 800             psp->fw_pri_buf) {
 801                 ret = psp_load_toc(psp, &tmr_size);
 802                 if (ret) {
 803                         DRM_ERROR("Failed to load toc\n");
 804                         return ret;
 805                 }
 806         }
 807
 808         if (!psp->tmr_bo) {
 809                 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 810                 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
 811                                               PSP_TMR_ALIGNMENT,
 812                                               AMDGPU_HAS_VRAM(psp->adev) ?
 813                                               AMDGPU_GEM_DOMAIN_VRAM :
 814                                               AMDGPU_GEM_DOMAIN_GTT,
 815                                               &psp->tmr_bo, &psp->tmr_mc_addr,
 816                                               pptr);
 817         }
 818
 819         return ret;
 820 }
 821
 822 static bool psp_skip_tmr(struct psp_context *psp)
 823 {
 824         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 825         case IP_VERSION(11, 0, 9):
 826         case IP_VERSION(11, 0, 7):
 827         case IP_VERSION(13, 0, 2):
 828         case IP_VERSION(13, 0, 6):
 829         case IP_VERSION(13, 0, 10):
 830                 return true;
 831         default:
 832                 return false;
 833         }
 834 }
 835
 836 static int psp_tmr_load(struct psp_context *psp)
 837 {
 838         int ret;
 839         struct psp_gfx_cmd_resp *cmd;
 840
 841         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 842          * Already set up by host driver.
 843          */
 844         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 845                 return 0;
 846
 847         cmd = acquire_psp_cmd_buf(psp);
 848
 849         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 850         if (psp->tmr_bo)
 851                 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 852                          amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 853
 854         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 855                                  psp->fence_buf_mc_addr);
 856
 857         release_psp_cmd_buf(psp);
 858
 859         return ret;
 860 }
 861
 862 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 863                                         struct psp_gfx_cmd_resp *cmd)
 864 {
 865         if (amdgpu_sriov_vf(psp->adev))
 866                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 867         else
 868                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 869 }
 870
 871 static int psp_tmr_unload(struct psp_context *psp)
 872 {
 873         int ret;
 874         struct psp_gfx_cmd_resp *cmd;
 875
 876         /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV,
 877          * as TMR is not loaded at all
 878          */
 879         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 880                 return 0;
 881
 882         cmd = acquire_psp_cmd_buf(psp);
 883
 884         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 885         dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
 886
 887         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 888                                  psp->fence_buf_mc_addr);
 889
 890         release_psp_cmd_buf(psp);
 891
 892         return ret;
 893 }
 894
 895 static int psp_tmr_terminate(struct psp_context *psp)
 896 {
 897         return psp_tmr_unload(psp);
 898 }
 899
 900 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 901                                         uint64_t *output_ptr)
 902 {
 903         int ret;
 904         struct psp_gfx_cmd_resp *cmd;
 905
 906         if (!output_ptr)
 907                 return -EINVAL;
 908
 909         if (amdgpu_sriov_vf(psp->adev))
 910                 return 0;
 911
 912         cmd = acquire_psp_cmd_buf(psp);
 913
 914         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 915
 916         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 917                                  psp->fence_buf_mc_addr);
 918
 919         if (!ret) {
 920                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 921                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 922         }
 923
 924         release_psp_cmd_buf(psp);
 925
 926         return ret;
 927 }
 928
 929 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 930 {
 931         struct psp_context *psp = &adev->psp;
 932         struct psp_gfx_cmd_resp *cmd;
 933         int ret;
 934
 935         if (amdgpu_sriov_vf(adev))
 936                 return 0;
 937
 938         cmd = acquire_psp_cmd_buf(psp);
 939
 940         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 941         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 942
 943         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 944         if (!ret) {
 945                 *boot_cfg =
 946                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 947         }
 948
 949         release_psp_cmd_buf(psp);
 950
 951         return ret;
 952 }
 953
 954 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 955 {
 956         int ret;
 957         struct psp_context *psp = &adev->psp;
 958         struct psp_gfx_cmd_resp *cmd;
 959
 960         if (amdgpu_sriov_vf(adev))
 961                 return 0;
 962
 963         cmd = acquire_psp_cmd_buf(psp);
 964
 965         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 966         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 967         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 968         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 969
 970         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 971
 972         release_psp_cmd_buf(psp);
 973
 974         return ret;
 975 }
 976
 977 static int psp_rl_load(struct amdgpu_device *adev)
 978 {
 979         int ret;
 980         struct psp_context *psp = &adev->psp;
 981         struct psp_gfx_cmd_resp *cmd;
 982
 983         if (!is_psp_fw_valid(psp->rl))
 984                 return 0;
 985
 986         cmd = acquire_psp_cmd_buf(psp);
 987
 988         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 989         memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
 990
 991         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 992         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 993         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 994         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
 995         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 996
 997         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 998
 999         release_psp_cmd_buf(psp);
1000
1001         return ret;
1002 }
1003
1004 int psp_spatial_partition(struct psp_context *psp, int mode)
1005 {
1006         struct psp_gfx_cmd_resp *cmd;
1007         int ret;
1008
1009         if (amdgpu_sriov_vf(psp->adev))
1010                 return 0;
1011
1012         cmd = acquire_psp_cmd_buf(psp);
1013
1014         cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART;
1015         cmd->cmd.cmd_spatial_part.mode = mode;
1016
1017         dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode);
1018         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1019
1020         release_psp_cmd_buf(psp);
1021
1022         return ret;
1023 }
1024
1025 static int psp_asd_initialize(struct psp_context *psp)
1026 {
1027         int ret;
1028
1029         /* If PSP version doesn't match ASD version, asd loading will be failed.
1030          * add workaround to bypass it for sriov now.
1031          * TODO: add version check to make it common
1032          */
1033         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
1034                 return 0;
1035
1036         psp->asd_context.mem_context.shared_mc_addr  = 0;
1037         psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
1038         psp->asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;
1039
1040         ret = psp_ta_load(psp, &psp->asd_context);
1041         if (!ret)
1042                 psp->asd_context.initialized = true;
1043
1044         return ret;
1045 }
1046
1047 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1048                                        uint32_t session_id)
1049 {
1050         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
1051         cmd->cmd.cmd_unload_ta.session_id = session_id;
1052 }
1053
1054 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
1055 {
1056         int ret;
1057         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1058
1059         psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
1060
1061         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1062
1063         context->resp_status = cmd->resp.status;
1064
1065         release_psp_cmd_buf(psp);
1066
1067         return ret;
1068 }
1069
1070 static int psp_asd_terminate(struct psp_context *psp)
1071 {
1072         int ret;
1073
1074         if (amdgpu_sriov_vf(psp->adev))
1075                 return 0;
1076
1077         if (!psp->asd_context.initialized)
1078                 return 0;
1079
1080         ret = psp_ta_unload(psp, &psp->asd_context);
1081         if (!ret)
1082                 psp->asd_context.initialized = false;
1083
1084         return ret;
1085 }
1086
1087 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1088                 uint32_t id, uint32_t value)
1089 {
1090         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1091         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1092         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1093 }
1094
1095 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1096                 uint32_t value)
1097 {
1098         struct psp_gfx_cmd_resp *cmd;
1099         int ret = 0;
1100
1101         if (reg >= PSP_REG_LAST)
1102                 return -EINVAL;
1103
1104         cmd = acquire_psp_cmd_buf(psp);
1105
1106         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1107         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1108         if (ret)
1109                 DRM_ERROR("PSP failed to program reg id %d", reg);
1110
1111         release_psp_cmd_buf(psp);
1112
1113         return ret;
1114 }
1115
1116 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1117                                      uint64_t ta_bin_mc,
1118                                      struct ta_context *context)
1119 {
1120         cmd->cmd_id                             = context->ta_load_type;
1121         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
1122         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
1123         cmd->cmd.cmd_load_ta.app_len            = context->bin_desc.size_bytes;
1124
1125         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1126                 lower_32_bits(context->mem_context.shared_mc_addr);
1127         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1128                 upper_32_bits(context->mem_context.shared_mc_addr);
1129         cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1130 }
1131
1132 int psp_ta_init_shared_buf(struct psp_context *psp,
1133                                   struct ta_mem_context *mem_ctx)
1134 {
1135         /*
1136         * Allocate 16k memory aligned to 4k from Frame Buffer (local
1137         * physical) for ta to host memory
1138         */
1139         return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1140                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1141                                       AMDGPU_GEM_DOMAIN_GTT,
1142                                       &mem_ctx->shared_bo,
1143                                       &mem_ctx->shared_mc_addr,
1144                                       &mem_ctx->shared_buf);
1145 }
1146
1147 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1148                                        uint32_t ta_cmd_id,
1149                                        uint32_t session_id)
1150 {
1151         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
1152         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
1153         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
1154 }
1155
1156 int psp_ta_invoke(struct psp_context *psp,
1157                   uint32_t ta_cmd_id,
1158                   struct ta_context *context)
1159 {
1160         int ret;
1161         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1162
1163         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1164
1165         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1166                                  psp->fence_buf_mc_addr);
1167
1168         context->resp_status = cmd->resp.status;
1169
1170         release_psp_cmd_buf(psp);
1171
1172         return ret;
1173 }
1174
1175 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1176 {
1177         int ret;
1178         struct psp_gfx_cmd_resp *cmd;
1179
1180         cmd = acquire_psp_cmd_buf(psp);
1181
1182         psp_copy_fw(psp, context->bin_desc.start_addr,
1183                     context->bin_desc.size_bytes);
1184
1185         psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1186
1187         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1188                                  psp->fence_buf_mc_addr);
1189
1190         context->resp_status = cmd->resp.status;
1191
1192         if (!ret)
1193                 context->session_id = cmd->resp.session_id;
1194
1195         release_psp_cmd_buf(psp);
1196
1197         return ret;
1198 }
1199
1200 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1201 {
1202         return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1203 }
1204
1205 int psp_xgmi_terminate(struct psp_context *psp)
1206 {
1207         int ret;
1208         struct amdgpu_device *adev = psp->adev;
1209
1210         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1211         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1212             (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1213              adev->gmc.xgmi.connected_to_cpu))
1214                 return 0;
1215
1216         if (!psp->xgmi_context.context.initialized)
1217                 return 0;
1218
1219         ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1220
1221         psp->xgmi_context.context.initialized = false;
1222
1223         return ret;
1224 }
1225
1226 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1227 {
1228         struct ta_xgmi_shared_memory *xgmi_cmd;
1229         int ret;
1230
1231         if (!psp->ta_fw ||
1232             !psp->xgmi_context.context.bin_desc.size_bytes ||
1233             !psp->xgmi_context.context.bin_desc.start_addr)
1234                 return -ENOENT;
1235
1236         if (!load_ta)
1237                 goto invoke;
1238
1239         psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1240         psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1241
1242         if (!psp->xgmi_context.context.mem_context.shared_buf) {
1243                 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1244                 if (ret)
1245                         return ret;
1246         }
1247
1248         /* Load XGMI TA */
1249         ret = psp_ta_load(psp, &psp->xgmi_context.context);
1250         if (!ret)
1251                 psp->xgmi_context.context.initialized = true;
1252         else
1253                 return ret;
1254
1255 invoke:
1256         /* Initialize XGMI session */
1257         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1258         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1259         xgmi_cmd->flag_extend_link_record = set_extended_data;
1260         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1261
1262         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1263
1264         return ret;
1265 }
1266
1267 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1268 {
1269         struct ta_xgmi_shared_memory *xgmi_cmd;
1270         int ret;
1271
1272         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1273         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1274
1275         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1276
1277         /* Invoke xgmi ta to get hive id */
1278         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1279         if (ret)
1280                 return ret;
1281
1282         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1283
1284         return 0;
1285 }
1286
1287 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1288 {
1289         struct ta_xgmi_shared_memory *xgmi_cmd;
1290         int ret;
1291
1292         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1293         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1294
1295         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1296
1297         /* Invoke xgmi ta to get the node id */
1298         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1299         if (ret)
1300                 return ret;
1301
1302         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1303
1304         return 0;
1305 }
1306
1307 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1308 {
1309         return (psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1310                 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) ||
1311                 psp->adev->ip_versions[MP0_HWIP][0] >= IP_VERSION(13, 0, 6);
1312 }
1313
1314 /*
1315  * Chips that support extended topology information require the driver to
1316  * reflect topology information in the opposite direction.  This is
1317  * because the TA has already exceeded its link record limit and if the
1318  * TA holds bi-directional information, the driver would have to do
1319  * multiple fetches instead of just two.
1320  */
1321 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1322                                         struct psp_xgmi_node_info node_info)
1323 {
1324         struct amdgpu_device *mirror_adev;
1325         struct amdgpu_hive_info *hive;
1326         uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1327         uint64_t dst_node_id = node_info.node_id;
1328         uint8_t dst_num_hops = node_info.num_hops;
1329         uint8_t dst_num_links = node_info.num_links;
1330
1331         hive = amdgpu_get_xgmi_hive(psp->adev);
1332         list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1333                 struct psp_xgmi_topology_info *mirror_top_info;
1334                 int j;
1335
1336                 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1337                         continue;
1338
1339                 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1340                 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1341                         if (mirror_top_info->nodes[j].node_id != src_node_id)
1342                                 continue;
1343
1344                         mirror_top_info->nodes[j].num_hops = dst_num_hops;
1345                         /*
1346                          * prevent 0 num_links value re-reflection since reflection
1347                          * criteria is based on num_hops (direct or indirect).
1348                          *
1349                          */
1350                         if (dst_num_links)
1351                                 mirror_top_info->nodes[j].num_links = dst_num_links;
1352
1353                         break;
1354                 }
1355
1356                 break;
1357         }
1358
1359         amdgpu_put_xgmi_hive(hive);
1360 }
1361
1362 int psp_xgmi_get_topology_info(struct psp_context *psp,
1363                                int number_devices,
1364                                struct psp_xgmi_topology_info *topology,
1365                                bool get_extended_data)
1366 {
1367         struct ta_xgmi_shared_memory *xgmi_cmd;
1368         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1369         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1370         int i;
1371         int ret;
1372
1373         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1374                 return -EINVAL;
1375
1376         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1377         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1378         xgmi_cmd->flag_extend_link_record = get_extended_data;
1379
1380         /* Fill in the shared memory with topology information as input */
1381         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1382         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1383         topology_info_input->num_nodes = number_devices;
1384
1385         for (i = 0; i < topology_info_input->num_nodes; i++) {
1386                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1387                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1388                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1389                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1390         }
1391
1392         /* Invoke xgmi ta to get the topology information */
1393         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1394         if (ret)
1395                 return ret;
1396
1397         /* Read the output topology information from the shared memory */
1398         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1399         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1400         for (i = 0; i < topology->num_nodes; i++) {
1401                 /* extended data will either be 0 or equal to non-extended data */
1402                 if (topology_info_output->nodes[i].num_hops)
1403                         topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1404
1405                 /* non-extended data gets everything here so no need to update */
1406                 if (!get_extended_data) {
1407                         topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1408                         topology->nodes[i].is_sharing_enabled =
1409                                         topology_info_output->nodes[i].is_sharing_enabled;
1410                         topology->nodes[i].sdma_engine =
1411                                         topology_info_output->nodes[i].sdma_engine;
1412                 }
1413
1414         }
1415
1416         /* Invoke xgmi ta again to get the link information */
1417         if (psp_xgmi_peer_link_info_supported(psp)) {
1418                 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1419                 bool requires_reflection =
1420                         (psp->xgmi_context.supports_extended_data && get_extended_data) ||
1421                                 psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6);
1422
1423                 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1424
1425                 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1426
1427                 if (ret)
1428                         return ret;
1429
1430                 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1431                 for (i = 0; i < topology->num_nodes; i++) {
1432                         /* accumulate num_links on extended data */
1433                         topology->nodes[i].num_links = get_extended_data ?
1434                                         topology->nodes[i].num_links +
1435                                                         link_info_output->nodes[i].num_links :
1436                                         ((requires_reflection && topology->nodes[i].num_links) ? topology->nodes[i].num_links :
1437                                          link_info_output->nodes[i].num_links);
1438
1439                         /* reflect the topology information for bi-directionality */
1440                         if (requires_reflection && topology->nodes[i].num_hops)
1441                                 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1442                 }
1443         }
1444
1445         return 0;
1446 }
1447
1448 int psp_xgmi_set_topology_info(struct psp_context *psp,
1449                                int number_devices,
1450                                struct psp_xgmi_topology_info *topology)
1451 {
1452         struct ta_xgmi_shared_memory *xgmi_cmd;
1453         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1454         int i;
1455
1456         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1457                 return -EINVAL;
1458
1459         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1460         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1461
1462         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1463         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1464         topology_info_input->num_nodes = number_devices;
1465
1466         for (i = 0; i < topology_info_input->num_nodes; i++) {
1467                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1468                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1469                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1470                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1471         }
1472
1473         /* Invoke xgmi ta to set topology information */
1474         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1475 }
1476
1477 // ras begin
1478 static void psp_ras_ta_check_status(struct psp_context *psp)
1479 {
1480         struct ta_ras_shared_memory *ras_cmd =
1481                 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1482
1483         switch (ras_cmd->ras_status) {
1484         case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1485                 dev_warn(psp->adev->dev,
1486                                 "RAS WARNING: cmd failed due to unsupported ip\n");
1487                 break;
1488         case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1489                 dev_warn(psp->adev->dev,
1490                                 "RAS WARNING: cmd failed due to unsupported error injection\n");
1491                 break;
1492         case TA_RAS_STATUS__SUCCESS:
1493                 break;
1494         case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1495                 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1496                         dev_warn(psp->adev->dev,
1497                                         "RAS WARNING: Inject error to critical region is not allowed\n");
1498                 break;
1499         default:
1500                 dev_warn(psp->adev->dev,
1501                                 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1502                 break;
1503         }
1504 }
1505
1506 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1507 {
1508         struct ta_ras_shared_memory *ras_cmd;
1509         int ret;
1510
1511         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1512
1513         /*
1514          * TODO: bypass the loading in sriov for now
1515          */
1516         if (amdgpu_sriov_vf(psp->adev))
1517                 return 0;
1518
1519         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1520
1521         if (amdgpu_ras_intr_triggered())
1522                 return ret;
1523
1524         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) {
1525                 DRM_WARN("RAS: Unsupported Interface");
1526                 return -EINVAL;
1527         }
1528
1529         if (!ret) {
1530                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1531                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1532
1533                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1534                 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1535                         dev_warn(psp->adev->dev,
1536                                  "RAS internal register access blocked\n");
1537
1538                 psp_ras_ta_check_status(psp);
1539         }
1540
1541         return ret;
1542 }
1543
1544 int psp_ras_enable_features(struct psp_context *psp,
1545                 union ta_ras_cmd_input *info, bool enable)
1546 {
1547         struct ta_ras_shared_memory *ras_cmd;
1548         int ret;
1549
1550         if (!psp->ras_context.context.initialized)
1551                 return -EINVAL;
1552
1553         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1554         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1555
1556         if (enable)
1557                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1558         else
1559                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1560
1561         ras_cmd->ras_in_message = *info;
1562
1563         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1564         if (ret)
1565                 return -EINVAL;
1566
1567         return 0;
1568 }
1569
1570 int psp_ras_terminate(struct psp_context *psp)
1571 {
1572         int ret;
1573
1574         /*
1575          * TODO: bypass the terminate in sriov for now
1576          */
1577         if (amdgpu_sriov_vf(psp->adev))
1578                 return 0;
1579
1580         if (!psp->ras_context.context.initialized)
1581                 return 0;
1582
1583         ret = psp_ta_unload(psp, &psp->ras_context.context);
1584
1585         psp->ras_context.context.initialized = false;
1586
1587         return ret;
1588 }
1589
1590 int psp_ras_initialize(struct psp_context *psp)
1591 {
1592         int ret;
1593         uint32_t boot_cfg = 0xFF;
1594         struct amdgpu_device *adev = psp->adev;
1595         struct ta_ras_shared_memory *ras_cmd;
1596
1597         /*
1598          * TODO: bypass the initialize in sriov for now
1599          */
1600         if (amdgpu_sriov_vf(adev))
1601                 return 0;
1602
1603         if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1604             !adev->psp.ras_context.context.bin_desc.start_addr) {
1605                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1606                 return 0;
1607         }
1608
1609         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1610                 /* query GECC enablement status from boot config
1611                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1612                  */
1613                 ret = psp_boot_config_get(adev, &boot_cfg);
1614                 if (ret)
1615                         dev_warn(adev->dev, "PSP get boot config failed\n");
1616
1617                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1618                         if (!boot_cfg) {
1619                                 dev_info(adev->dev, "GECC is disabled\n");
1620                         } else {
1621                                 /* disable GECC in next boot cycle if ras is
1622                                  * disabled by module parameter amdgpu_ras_enable
1623                                  * and/or amdgpu_ras_mask, or boot_config_get call
1624                                  * is failed
1625                                  */
1626                                 ret = psp_boot_config_set(adev, 0);
1627                                 if (ret)
1628                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1629                                 else
1630                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1631                         }
1632                 } else {
1633                         if (boot_cfg == 1) {
1634                                 dev_info(adev->dev, "GECC is enabled\n");
1635                         } else {
1636                                 /* enable GECC in next boot cycle if it is disabled
1637                                  * in boot config, or force enable GECC if failed to
1638                                  * get boot configuration
1639                                  */
1640                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1641                                 if (ret)
1642                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1643                                 else
1644                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1645                         }
1646                 }
1647         }
1648
1649         psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1650         psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1651
1652         if (!psp->ras_context.context.mem_context.shared_buf) {
1653                 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1654                 if (ret)
1655                         return ret;
1656         }
1657
1658         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1659         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1660
1661         if (amdgpu_ras_is_poison_mode_supported(adev))
1662                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1663         if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
1664                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1665         ras_cmd->ras_in_message.init_flags.xcc_mask =
1666                 adev->gfx.xcc_mask;
1667         ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2;
1668
1669         ret = psp_ta_load(psp, &psp->ras_context.context);
1670
1671         if (!ret && !ras_cmd->ras_status)
1672                 psp->ras_context.context.initialized = true;
1673         else {
1674                 if (ras_cmd->ras_status)
1675                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1676
1677                 /* fail to load RAS TA */
1678                 psp->ras_context.context.initialized = false;
1679         }
1680
1681         return ret;
1682 }
1683
1684 int psp_ras_trigger_error(struct psp_context *psp,
1685                           struct ta_ras_trigger_error_input *info, uint32_t instance_mask)
1686 {
1687         struct ta_ras_shared_memory *ras_cmd;
1688         struct amdgpu_device *adev = psp->adev;
1689         int ret;
1690         uint32_t dev_mask;
1691
1692         if (!psp->ras_context.context.initialized)
1693                 return -EINVAL;
1694
1695         switch (info->block_id) {
1696         case TA_RAS_BLOCK__GFX:
1697                 dev_mask = GET_MASK(GC, instance_mask);
1698                 break;
1699         case TA_RAS_BLOCK__SDMA:
1700                 dev_mask = GET_MASK(SDMA0, instance_mask);
1701                 break;
1702         case TA_RAS_BLOCK__VCN:
1703         case TA_RAS_BLOCK__JPEG:
1704                 dev_mask = GET_MASK(VCN, instance_mask);
1705                 break;
1706         default:
1707                 dev_mask = instance_mask;
1708                 break;
1709         }
1710
1711         /* reuse sub_block_index for backward compatibility */
1712         dev_mask <<= AMDGPU_RAS_INST_SHIFT;
1713         dev_mask &= AMDGPU_RAS_INST_MASK;
1714         info->sub_block_index |= dev_mask;
1715
1716         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1717         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1718
1719         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1720         ras_cmd->ras_in_message.trigger_error = *info;
1721
1722         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1723         if (ret)
1724                 return -EINVAL;
1725
1726         /* If err_event_athub occurs error inject was successful, however
1727            return status from TA is no long reliable */
1728         if (amdgpu_ras_intr_triggered())
1729                 return 0;
1730
1731         if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1732                 return -EACCES;
1733         else if (ras_cmd->ras_status)
1734                 return -EINVAL;
1735
1736         return 0;
1737 }
1738 // ras end
1739
1740 // HDCP start
1741 static int psp_hdcp_initialize(struct psp_context *psp)
1742 {
1743         int ret;
1744
1745         /*
1746          * TODO: bypass the initialize in sriov for now
1747          */
1748         if (amdgpu_sriov_vf(psp->adev))
1749                 return 0;
1750
1751         if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1752             !psp->hdcp_context.context.bin_desc.start_addr) {
1753                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1754                 return 0;
1755         }
1756
1757         psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1758         psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1759
1760         if (!psp->hdcp_context.context.mem_context.shared_buf) {
1761                 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1762                 if (ret)
1763                         return ret;
1764         }
1765
1766         ret = psp_ta_load(psp, &psp->hdcp_context.context);
1767         if (!ret) {
1768                 psp->hdcp_context.context.initialized = true;
1769                 mutex_init(&psp->hdcp_context.mutex);
1770         }
1771
1772         return ret;
1773 }
1774
1775 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1776 {
1777         /*
1778          * TODO: bypass the loading in sriov for now
1779          */
1780         if (amdgpu_sriov_vf(psp->adev))
1781                 return 0;
1782
1783         return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1784 }
1785
1786 static int psp_hdcp_terminate(struct psp_context *psp)
1787 {
1788         int ret;
1789
1790         /*
1791          * TODO: bypass the terminate in sriov for now
1792          */
1793         if (amdgpu_sriov_vf(psp->adev))
1794                 return 0;
1795
1796         if (!psp->hdcp_context.context.initialized)
1797                 return 0;
1798
1799         ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1800
1801         psp->hdcp_context.context.initialized = false;
1802
1803         return ret;
1804 }
1805 // HDCP end
1806
1807 // DTM start
1808 static int psp_dtm_initialize(struct psp_context *psp)
1809 {
1810         int ret;
1811
1812         /*
1813          * TODO: bypass the initialize in sriov for now
1814          */
1815         if (amdgpu_sriov_vf(psp->adev))
1816                 return 0;
1817
1818         if (!psp->dtm_context.context.bin_desc.size_bytes ||
1819             !psp->dtm_context.context.bin_desc.start_addr) {
1820                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1821                 return 0;
1822         }
1823
1824         psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1825         psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1826
1827         if (!psp->dtm_context.context.mem_context.shared_buf) {
1828                 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1829                 if (ret)
1830                         return ret;
1831         }
1832
1833         ret = psp_ta_load(psp, &psp->dtm_context.context);
1834         if (!ret) {
1835                 psp->dtm_context.context.initialized = true;
1836                 mutex_init(&psp->dtm_context.mutex);
1837         }
1838
1839         return ret;
1840 }
1841
1842 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1843 {
1844         /*
1845          * TODO: bypass the loading in sriov for now
1846          */
1847         if (amdgpu_sriov_vf(psp->adev))
1848                 return 0;
1849
1850         return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1851 }
1852
1853 static int psp_dtm_terminate(struct psp_context *psp)
1854 {
1855         int ret;
1856
1857         /*
1858          * TODO: bypass the terminate in sriov for now
1859          */
1860         if (amdgpu_sriov_vf(psp->adev))
1861                 return 0;
1862
1863         if (!psp->dtm_context.context.initialized)
1864                 return 0;
1865
1866         ret = psp_ta_unload(psp, &psp->dtm_context.context);
1867
1868         psp->dtm_context.context.initialized = false;
1869
1870         return ret;
1871 }
1872 // DTM end
1873
1874 // RAP start
1875 static int psp_rap_initialize(struct psp_context *psp)
1876 {
1877         int ret;
1878         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1879
1880         /*
1881          * TODO: bypass the initialize in sriov for now
1882          */
1883         if (amdgpu_sriov_vf(psp->adev))
1884                 return 0;
1885
1886         if (!psp->rap_context.context.bin_desc.size_bytes ||
1887             !psp->rap_context.context.bin_desc.start_addr) {
1888                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1889                 return 0;
1890         }
1891
1892         psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1893         psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1894
1895         if (!psp->rap_context.context.mem_context.shared_buf) {
1896                 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1897                 if (ret)
1898                         return ret;
1899         }
1900
1901         ret = psp_ta_load(psp, &psp->rap_context.context);
1902         if (!ret) {
1903                 psp->rap_context.context.initialized = true;
1904                 mutex_init(&psp->rap_context.mutex);
1905         } else
1906                 return ret;
1907
1908         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1909         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1910                 psp_rap_terminate(psp);
1911                 /* free rap shared memory */
1912                 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1913
1914                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1915                          ret, status);
1916
1917                 return ret;
1918         }
1919
1920         return 0;
1921 }
1922
1923 static int psp_rap_terminate(struct psp_context *psp)
1924 {
1925         int ret;
1926
1927         if (!psp->rap_context.context.initialized)
1928                 return 0;
1929
1930         ret = psp_ta_unload(psp, &psp->rap_context.context);
1931
1932         psp->rap_context.context.initialized = false;
1933
1934         return ret;
1935 }
1936
1937 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1938 {
1939         struct ta_rap_shared_memory *rap_cmd;
1940         int ret = 0;
1941
1942         if (!psp->rap_context.context.initialized)
1943                 return 0;
1944
1945         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1946             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1947                 return -EINVAL;
1948
1949         mutex_lock(&psp->rap_context.mutex);
1950
1951         rap_cmd = (struct ta_rap_shared_memory *)
1952                   psp->rap_context.context.mem_context.shared_buf;
1953         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1954
1955         rap_cmd->cmd_id = ta_cmd_id;
1956         rap_cmd->validation_method_id = METHOD_A;
1957
1958         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1959         if (ret)
1960                 goto out_unlock;
1961
1962         if (status)
1963                 *status = rap_cmd->rap_status;
1964
1965 out_unlock:
1966         mutex_unlock(&psp->rap_context.mutex);
1967
1968         return ret;
1969 }
1970 // RAP end
1971
1972 /* securedisplay start */
1973 static int psp_securedisplay_initialize(struct psp_context *psp)
1974 {
1975         int ret;
1976         struct ta_securedisplay_cmd *securedisplay_cmd;
1977
1978         /*
1979          * TODO: bypass the initialize in sriov for now
1980          */
1981         if (amdgpu_sriov_vf(psp->adev))
1982                 return 0;
1983
1984         if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1985             !psp->securedisplay_context.context.bin_desc.start_addr) {
1986                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1987                 return 0;
1988         }
1989
1990         psp->securedisplay_context.context.mem_context.shared_mem_size =
1991                 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1992         psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1993
1994         if (!psp->securedisplay_context.context.initialized) {
1995                 ret = psp_ta_init_shared_buf(psp,
1996                                              &psp->securedisplay_context.context.mem_context);
1997                 if (ret)
1998                         return ret;
1999         }
2000
2001         ret = psp_ta_load(psp, &psp->securedisplay_context.context);
2002         if (!ret) {
2003                 psp->securedisplay_context.context.initialized = true;
2004                 mutex_init(&psp->securedisplay_context.mutex);
2005         } else
2006                 return ret;
2007
2008         mutex_lock(&psp->securedisplay_context.mutex);
2009
2010         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
2011                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2012
2013         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2014
2015         mutex_unlock(&psp->securedisplay_context.mutex);
2016
2017         if (ret) {
2018                 psp_securedisplay_terminate(psp);
2019                 /* free securedisplay shared memory */
2020                 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
2021                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
2022                 return -EINVAL;
2023         }
2024
2025         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
2026                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
2027                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
2028                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
2029                 /* don't try again */
2030                 psp->securedisplay_context.context.bin_desc.size_bytes = 0;
2031         }
2032
2033         return 0;
2034 }
2035
2036 static int psp_securedisplay_terminate(struct psp_context *psp)
2037 {
2038         int ret;
2039
2040         /*
2041          * TODO:bypass the terminate in sriov for now
2042          */
2043         if (amdgpu_sriov_vf(psp->adev))
2044                 return 0;
2045
2046         if (!psp->securedisplay_context.context.initialized)
2047                 return 0;
2048
2049         ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
2050
2051         psp->securedisplay_context.context.initialized = false;
2052
2053         return ret;
2054 }
2055
2056 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2057 {
2058         int ret;
2059
2060         if (!psp->securedisplay_context.context.initialized)
2061                 return -EINVAL;
2062
2063         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2064             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
2065                 return -EINVAL;
2066
2067         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
2068
2069         return ret;
2070 }
2071 /* SECUREDISPLAY end */
2072
2073 static int psp_hw_start(struct psp_context *psp)
2074 {
2075         struct amdgpu_device *adev = psp->adev;
2076         int ret;
2077
2078         if (!amdgpu_sriov_vf(adev)) {
2079                 if ((is_psp_fw_valid(psp->kdb)) &&
2080                     (psp->funcs->bootloader_load_kdb != NULL)) {
2081                         ret = psp_bootloader_load_kdb(psp);
2082                         if (ret) {
2083                                 DRM_ERROR("PSP load kdb failed!\n");
2084                                 return ret;
2085                         }
2086                 }
2087
2088                 if ((is_psp_fw_valid(psp->spl)) &&
2089                     (psp->funcs->bootloader_load_spl != NULL)) {
2090                         ret = psp_bootloader_load_spl(psp);
2091                         if (ret) {
2092                                 DRM_ERROR("PSP load spl failed!\n");
2093                                 return ret;
2094                         }
2095                 }
2096
2097                 if ((is_psp_fw_valid(psp->sys)) &&
2098                     (psp->funcs->bootloader_load_sysdrv != NULL)) {
2099                         ret = psp_bootloader_load_sysdrv(psp);
2100                         if (ret) {
2101                                 DRM_ERROR("PSP load sys drv failed!\n");
2102                                 return ret;
2103                         }
2104                 }
2105
2106                 if ((is_psp_fw_valid(psp->soc_drv)) &&
2107                     (psp->funcs->bootloader_load_soc_drv != NULL)) {
2108                         ret = psp_bootloader_load_soc_drv(psp);
2109                         if (ret) {
2110                                 DRM_ERROR("PSP load soc drv failed!\n");
2111                                 return ret;
2112                         }
2113                 }
2114
2115                 if ((is_psp_fw_valid(psp->intf_drv)) &&
2116                     (psp->funcs->bootloader_load_intf_drv != NULL)) {
2117                         ret = psp_bootloader_load_intf_drv(psp);
2118                         if (ret) {
2119                                 DRM_ERROR("PSP load intf drv failed!\n");
2120                                 return ret;
2121                         }
2122                 }
2123
2124                 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2125                     (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2126                         ret = psp_bootloader_load_dbg_drv(psp);
2127                         if (ret) {
2128                                 DRM_ERROR("PSP load dbg drv failed!\n");
2129                                 return ret;
2130                         }
2131                 }
2132
2133                 if ((is_psp_fw_valid(psp->ras_drv)) &&
2134                     (psp->funcs->bootloader_load_ras_drv != NULL)) {
2135                         ret = psp_bootloader_load_ras_drv(psp);
2136                         if (ret) {
2137                                 DRM_ERROR("PSP load ras_drv failed!\n");
2138                                 return ret;
2139                         }
2140                 }
2141
2142                 if ((is_psp_fw_valid(psp->sos)) &&
2143                     (psp->funcs->bootloader_load_sos != NULL)) {
2144                         ret = psp_bootloader_load_sos(psp);
2145                         if (ret) {
2146                                 DRM_ERROR("PSP load sos failed!\n");
2147                                 return ret;
2148                         }
2149                 }
2150         }
2151
2152         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2153         if (ret) {
2154                 DRM_ERROR("PSP create ring failed!\n");
2155                 return ret;
2156         }
2157
2158         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2159                 goto skip_pin_bo;
2160
2161         if (!psp_boottime_tmr(psp)) {
2162                 ret = psp_tmr_init(psp);
2163                 if (ret) {
2164                         DRM_ERROR("PSP tmr init failed!\n");
2165                         return ret;
2166                 }
2167         }
2168
2169 skip_pin_bo:
2170         /*
2171          * For ASICs with DF Cstate management centralized
2172          * to PMFW, TMR setup should be performed after PMFW
2173          * loaded and before other non-psp firmware loaded.
2174          */
2175         if (psp->pmfw_centralized_cstate_management) {
2176                 ret = psp_load_smu_fw(psp);
2177                 if (ret)
2178                         return ret;
2179         }
2180
2181         ret = psp_tmr_load(psp);
2182         if (ret) {
2183                 DRM_ERROR("PSP load tmr failed!\n");
2184                 return ret;
2185         }
2186
2187         return 0;
2188 }
2189
2190 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2191                            enum psp_gfx_fw_type *type)
2192 {
2193         switch (ucode->ucode_id) {
2194         case AMDGPU_UCODE_ID_CAP:
2195                 *type = GFX_FW_TYPE_CAP;
2196                 break;
2197         case AMDGPU_UCODE_ID_SDMA0:
2198                 *type = GFX_FW_TYPE_SDMA0;
2199                 break;
2200         case AMDGPU_UCODE_ID_SDMA1:
2201                 *type = GFX_FW_TYPE_SDMA1;
2202                 break;
2203         case AMDGPU_UCODE_ID_SDMA2:
2204                 *type = GFX_FW_TYPE_SDMA2;
2205                 break;
2206         case AMDGPU_UCODE_ID_SDMA3:
2207                 *type = GFX_FW_TYPE_SDMA3;
2208                 break;
2209         case AMDGPU_UCODE_ID_SDMA4:
2210                 *type = GFX_FW_TYPE_SDMA4;
2211                 break;
2212         case AMDGPU_UCODE_ID_SDMA5:
2213                 *type = GFX_FW_TYPE_SDMA5;
2214                 break;
2215         case AMDGPU_UCODE_ID_SDMA6:
2216                 *type = GFX_FW_TYPE_SDMA6;
2217                 break;
2218         case AMDGPU_UCODE_ID_SDMA7:
2219                 *type = GFX_FW_TYPE_SDMA7;
2220                 break;
2221         case AMDGPU_UCODE_ID_CP_MES:
2222                 *type = GFX_FW_TYPE_CP_MES;
2223                 break;
2224         case AMDGPU_UCODE_ID_CP_MES_DATA:
2225                 *type = GFX_FW_TYPE_MES_STACK;
2226                 break;
2227         case AMDGPU_UCODE_ID_CP_MES1:
2228                 *type = GFX_FW_TYPE_CP_MES_KIQ;
2229                 break;
2230         case AMDGPU_UCODE_ID_CP_MES1_DATA:
2231                 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2232                 break;
2233         case AMDGPU_UCODE_ID_CP_CE:
2234                 *type = GFX_FW_TYPE_CP_CE;
2235                 break;
2236         case AMDGPU_UCODE_ID_CP_PFP:
2237                 *type = GFX_FW_TYPE_CP_PFP;
2238                 break;
2239         case AMDGPU_UCODE_ID_CP_ME:
2240                 *type = GFX_FW_TYPE_CP_ME;
2241                 break;
2242         case AMDGPU_UCODE_ID_CP_MEC1:
2243                 *type = GFX_FW_TYPE_CP_MEC;
2244                 break;
2245         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2246                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2247                 break;
2248         case AMDGPU_UCODE_ID_CP_MEC2:
2249                 *type = GFX_FW_TYPE_CP_MEC;
2250                 break;
2251         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2252                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2253                 break;
2254         case AMDGPU_UCODE_ID_RLC_P:
2255                 *type = GFX_FW_TYPE_RLC_P;
2256                 break;
2257         case AMDGPU_UCODE_ID_RLC_V:
2258                 *type = GFX_FW_TYPE_RLC_V;
2259                 break;
2260         case AMDGPU_UCODE_ID_RLC_G:
2261                 *type = GFX_FW_TYPE_RLC_G;
2262                 break;
2263         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2264                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2265                 break;
2266         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2267                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2268                 break;
2269         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2270                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2271                 break;
2272         case AMDGPU_UCODE_ID_RLC_IRAM:
2273                 *type = GFX_FW_TYPE_RLC_IRAM;
2274                 break;
2275         case AMDGPU_UCODE_ID_RLC_DRAM:
2276                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2277                 break;
2278         case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2279                 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2280                 break;
2281         case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2282                 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2283                 break;
2284         case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2285                 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2286                 break;
2287         case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2288                 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2289                 break;
2290         case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2291                 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2292                 break;
2293         case AMDGPU_UCODE_ID_SMC:
2294                 *type = GFX_FW_TYPE_SMU;
2295                 break;
2296         case AMDGPU_UCODE_ID_PPTABLE:
2297                 *type = GFX_FW_TYPE_PPTABLE;
2298                 break;
2299         case AMDGPU_UCODE_ID_UVD:
2300                 *type = GFX_FW_TYPE_UVD;
2301                 break;
2302         case AMDGPU_UCODE_ID_UVD1:
2303                 *type = GFX_FW_TYPE_UVD1;
2304                 break;
2305         case AMDGPU_UCODE_ID_VCE:
2306                 *type = GFX_FW_TYPE_VCE;
2307                 break;
2308         case AMDGPU_UCODE_ID_VCN:
2309                 *type = GFX_FW_TYPE_VCN;
2310                 break;
2311         case AMDGPU_UCODE_ID_VCN1:
2312                 *type = GFX_FW_TYPE_VCN1;
2313                 break;
2314         case AMDGPU_UCODE_ID_DMCU_ERAM:
2315                 *type = GFX_FW_TYPE_DMCU_ERAM;
2316                 break;
2317         case AMDGPU_UCODE_ID_DMCU_INTV:
2318                 *type = GFX_FW_TYPE_DMCU_ISR;
2319                 break;
2320         case AMDGPU_UCODE_ID_VCN0_RAM:
2321                 *type = GFX_FW_TYPE_VCN0_RAM;
2322                 break;
2323         case AMDGPU_UCODE_ID_VCN1_RAM:
2324                 *type = GFX_FW_TYPE_VCN1_RAM;
2325                 break;
2326         case AMDGPU_UCODE_ID_DMCUB:
2327                 *type = GFX_FW_TYPE_DMUB;
2328                 break;
2329         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2330                 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2331                 break;
2332         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2333                 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2334                 break;
2335         case AMDGPU_UCODE_ID_IMU_I:
2336                 *type = GFX_FW_TYPE_IMU_I;
2337                 break;
2338         case AMDGPU_UCODE_ID_IMU_D:
2339                 *type = GFX_FW_TYPE_IMU_D;
2340                 break;
2341         case AMDGPU_UCODE_ID_CP_RS64_PFP:
2342                 *type = GFX_FW_TYPE_RS64_PFP;
2343                 break;
2344         case AMDGPU_UCODE_ID_CP_RS64_ME:
2345                 *type = GFX_FW_TYPE_RS64_ME;
2346                 break;
2347         case AMDGPU_UCODE_ID_CP_RS64_MEC:
2348                 *type = GFX_FW_TYPE_RS64_MEC;
2349                 break;
2350         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2351                 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2352                 break;
2353         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2354                 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2355                 break;
2356         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2357                 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2358                 break;
2359         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2360                 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2361                 break;
2362         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2363                 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2364                 break;
2365         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2366                 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2367                 break;
2368         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2369                 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2370                 break;
2371         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2372                 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2373                 break;
2374         case AMDGPU_UCODE_ID_MAXIMUM:
2375         default:
2376                 return -EINVAL;
2377         }
2378
2379         return 0;
2380 }
2381
2382 static void psp_print_fw_hdr(struct psp_context *psp,
2383                              struct amdgpu_firmware_info *ucode)
2384 {
2385         struct amdgpu_device *adev = psp->adev;
2386         struct common_firmware_header *hdr;
2387
2388         switch (ucode->ucode_id) {
2389         case AMDGPU_UCODE_ID_SDMA0:
2390         case AMDGPU_UCODE_ID_SDMA1:
2391         case AMDGPU_UCODE_ID_SDMA2:
2392         case AMDGPU_UCODE_ID_SDMA3:
2393         case AMDGPU_UCODE_ID_SDMA4:
2394         case AMDGPU_UCODE_ID_SDMA5:
2395         case AMDGPU_UCODE_ID_SDMA6:
2396         case AMDGPU_UCODE_ID_SDMA7:
2397                 hdr = (struct common_firmware_header *)
2398                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2399                 amdgpu_ucode_print_sdma_hdr(hdr);
2400                 break;
2401         case AMDGPU_UCODE_ID_CP_CE:
2402                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2403                 amdgpu_ucode_print_gfx_hdr(hdr);
2404                 break;
2405         case AMDGPU_UCODE_ID_CP_PFP:
2406                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2407                 amdgpu_ucode_print_gfx_hdr(hdr);
2408                 break;
2409         case AMDGPU_UCODE_ID_CP_ME:
2410                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2411                 amdgpu_ucode_print_gfx_hdr(hdr);
2412                 break;
2413         case AMDGPU_UCODE_ID_CP_MEC1:
2414                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2415                 amdgpu_ucode_print_gfx_hdr(hdr);
2416                 break;
2417         case AMDGPU_UCODE_ID_RLC_G:
2418                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2419                 amdgpu_ucode_print_rlc_hdr(hdr);
2420                 break;
2421         case AMDGPU_UCODE_ID_SMC:
2422                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2423                 amdgpu_ucode_print_smc_hdr(hdr);
2424                 break;
2425         default:
2426                 break;
2427         }
2428 }
2429
2430 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2431                                        struct psp_gfx_cmd_resp *cmd)
2432 {
2433         int ret;
2434         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2435
2436         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2437         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2438         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2439         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2440
2441         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2442         if (ret)
2443                 DRM_ERROR("Unknown firmware type\n");
2444
2445         return ret;
2446 }
2447
2448 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2449                                   struct amdgpu_firmware_info *ucode)
2450 {
2451         int ret = 0;
2452         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2453
2454         ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2455         if (!ret) {
2456                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2457                                          psp->fence_buf_mc_addr);
2458         }
2459
2460         release_psp_cmd_buf(psp);
2461
2462         return ret;
2463 }
2464
2465 static int psp_load_smu_fw(struct psp_context *psp)
2466 {
2467         int ret;
2468         struct amdgpu_device *adev = psp->adev;
2469         struct amdgpu_firmware_info *ucode =
2470                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2471         struct amdgpu_ras *ras = psp->ras_context.ras;
2472
2473         /*
2474          * Skip SMU FW reloading in case of using BACO for runpm only,
2475          * as SMU is always alive.
2476          */
2477         if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2478                 return 0;
2479
2480         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2481                 return 0;
2482
2483         if ((amdgpu_in_reset(adev) &&
2484              ras && adev->ras_enabled &&
2485              (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2486               adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2487                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2488                 if (ret)
2489                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2490         }
2491
2492         ret = psp_execute_non_psp_fw_load(psp, ucode);
2493
2494         if (ret)
2495                 DRM_ERROR("PSP load smu failed!\n");
2496
2497         return ret;
2498 }
2499
2500 static bool fw_load_skip_check(struct psp_context *psp,
2501                                struct amdgpu_firmware_info *ucode)
2502 {
2503         if (!ucode->fw || !ucode->ucode_size)
2504                 return true;
2505
2506         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2507             (psp_smu_reload_quirk(psp) ||
2508              psp->autoload_supported ||
2509              psp->pmfw_centralized_cstate_management))
2510                 return true;
2511
2512         if (amdgpu_sriov_vf(psp->adev) &&
2513             amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2514                 return true;
2515
2516         if (psp->autoload_supported &&
2517             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2518              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2519                 /* skip mec JT when autoload is enabled */
2520                 return true;
2521
2522         return false;
2523 }
2524
2525 int psp_load_fw_list(struct psp_context *psp,
2526                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2527 {
2528         int ret = 0, i;
2529         struct amdgpu_firmware_info *ucode;
2530
2531         for (i = 0; i < ucode_count; ++i) {
2532                 ucode = ucode_list[i];
2533                 psp_print_fw_hdr(psp, ucode);
2534                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2535                 if (ret)
2536                         return ret;
2537         }
2538         return ret;
2539 }
2540
2541 static int psp_load_non_psp_fw(struct psp_context *psp)
2542 {
2543         int i, ret;
2544         struct amdgpu_firmware_info *ucode;
2545         struct amdgpu_device *adev = psp->adev;
2546
2547         if (psp->autoload_supported &&
2548             !psp->pmfw_centralized_cstate_management) {
2549                 ret = psp_load_smu_fw(psp);
2550                 if (ret)
2551                         return ret;
2552         }
2553
2554         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2555                 ucode = &adev->firmware.ucode[i];
2556
2557                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2558                     !fw_load_skip_check(psp, ucode)) {
2559                         ret = psp_load_smu_fw(psp);
2560                         if (ret)
2561                                 return ret;
2562                         continue;
2563                 }
2564
2565                 if (fw_load_skip_check(psp, ucode))
2566                         continue;
2567
2568                 if (psp->autoload_supported &&
2569                     (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2570                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2571                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2572                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2573                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2574                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2575                         /* PSP only receive one SDMA fw for sienna_cichlid,
2576                          * as all four sdma fw are same */
2577                         continue;
2578
2579                 psp_print_fw_hdr(psp, ucode);
2580
2581                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2582                 if (ret)
2583                         return ret;
2584
2585                 /* Start rlc autoload after psp recieved all the gfx firmware */
2586                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2587                     adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2588                         ret = psp_rlc_autoload_start(psp);
2589                         if (ret) {
2590                                 DRM_ERROR("Failed to start rlc autoload\n");
2591                                 return ret;
2592                         }
2593                 }
2594         }
2595
2596         return 0;
2597 }
2598
2599 static int psp_load_fw(struct amdgpu_device *adev)
2600 {
2601         int ret;
2602         struct psp_context *psp = &adev->psp;
2603
2604         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2605                 /* should not destroy ring, only stop */
2606                 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2607         } else {
2608                 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2609
2610                 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2611                 if (ret) {
2612                         DRM_ERROR("PSP ring init failed!\n");
2613                         goto failed;
2614                 }
2615         }
2616
2617         ret = psp_hw_start(psp);
2618         if (ret)
2619                 goto failed;
2620
2621         ret = psp_load_non_psp_fw(psp);
2622         if (ret)
2623                 goto failed1;
2624
2625         ret = psp_asd_initialize(psp);
2626         if (ret) {
2627                 DRM_ERROR("PSP load asd failed!\n");
2628                 goto failed1;
2629         }
2630
2631         ret = psp_rl_load(adev);
2632         if (ret) {
2633                 DRM_ERROR("PSP load RL failed!\n");
2634                 goto failed1;
2635         }
2636
2637         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2638                 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2639                         ret = psp_xgmi_initialize(psp, false, true);
2640                         /* Warning the XGMI seesion initialize failure
2641                         * Instead of stop driver initialization
2642                         */
2643                         if (ret)
2644                                 dev_err(psp->adev->dev,
2645                                         "XGMI: Failed to initialize XGMI session\n");
2646                 }
2647         }
2648
2649         if (psp->ta_fw) {
2650                 ret = psp_ras_initialize(psp);
2651                 if (ret)
2652                         dev_err(psp->adev->dev,
2653                                         "RAS: Failed to initialize RAS\n");
2654
2655                 ret = psp_hdcp_initialize(psp);
2656                 if (ret)
2657                         dev_err(psp->adev->dev,
2658                                 "HDCP: Failed to initialize HDCP\n");
2659
2660                 ret = psp_dtm_initialize(psp);
2661                 if (ret)
2662                         dev_err(psp->adev->dev,
2663                                 "DTM: Failed to initialize DTM\n");
2664
2665                 ret = psp_rap_initialize(psp);
2666                 if (ret)
2667                         dev_err(psp->adev->dev,
2668                                 "RAP: Failed to initialize RAP\n");
2669
2670                 ret = psp_securedisplay_initialize(psp);
2671                 if (ret)
2672                         dev_err(psp->adev->dev,
2673                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2674         }
2675
2676         return 0;
2677
2678 failed1:
2679         psp_free_shared_bufs(psp);
2680 failed:
2681         /*
2682          * all cleanup jobs (xgmi terminate, ras terminate,
2683          * ring destroy, cmd/fence/fw buffers destory,
2684          * psp->cmd destory) are delayed to psp_hw_fini
2685          */
2686         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2687         return ret;
2688 }
2689
2690 static int psp_hw_init(void *handle)
2691 {
2692         int ret;
2693         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2694
2695         mutex_lock(&adev->firmware.mutex);
2696         /*
2697          * This sequence is just used on hw_init only once, no need on
2698          * resume.
2699          */
2700         ret = amdgpu_ucode_init_bo(adev);
2701         if (ret)
2702                 goto failed;
2703
2704         ret = psp_load_fw(adev);
2705         if (ret) {
2706                 DRM_ERROR("PSP firmware loading failed\n");
2707                 goto failed;
2708         }
2709
2710         mutex_unlock(&adev->firmware.mutex);
2711         return 0;
2712
2713 failed:
2714         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2715         mutex_unlock(&adev->firmware.mutex);
2716         return -EINVAL;
2717 }
2718
2719 static int psp_hw_fini(void *handle)
2720 {
2721         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2722         struct psp_context *psp = &adev->psp;
2723
2724         if (psp->ta_fw) {
2725                 psp_ras_terminate(psp);
2726                 psp_securedisplay_terminate(psp);
2727                 psp_rap_terminate(psp);
2728                 psp_dtm_terminate(psp);
2729                 psp_hdcp_terminate(psp);
2730
2731                 if (adev->gmc.xgmi.num_physical_nodes > 1)
2732                         psp_xgmi_terminate(psp);
2733         }
2734
2735         psp_asd_terminate(psp);
2736         psp_tmr_terminate(psp);
2737
2738         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2739
2740         return 0;
2741 }
2742
2743 static int psp_suspend(void *handle)
2744 {
2745         int ret = 0;
2746         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2747         struct psp_context *psp = &adev->psp;
2748
2749         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2750             psp->xgmi_context.context.initialized) {
2751                 ret = psp_xgmi_terminate(psp);
2752                 if (ret) {
2753                         DRM_ERROR("Failed to terminate xgmi ta\n");
2754                         goto out;
2755                 }
2756         }
2757
2758         if (psp->ta_fw) {
2759                 ret = psp_ras_terminate(psp);
2760                 if (ret) {
2761                         DRM_ERROR("Failed to terminate ras ta\n");
2762                         goto out;
2763                 }
2764                 ret = psp_hdcp_terminate(psp);
2765                 if (ret) {
2766                         DRM_ERROR("Failed to terminate hdcp ta\n");
2767                         goto out;
2768                 }
2769                 ret = psp_dtm_terminate(psp);
2770                 if (ret) {
2771                         DRM_ERROR("Failed to terminate dtm ta\n");
2772                         goto out;
2773                 }
2774                 ret = psp_rap_terminate(psp);
2775                 if (ret) {
2776                         DRM_ERROR("Failed to terminate rap ta\n");
2777                         goto out;
2778                 }
2779                 ret = psp_securedisplay_terminate(psp);
2780                 if (ret) {
2781                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2782                         goto out;
2783                 }
2784         }
2785
2786         ret = psp_asd_terminate(psp);
2787         if (ret) {
2788                 DRM_ERROR("Failed to terminate asd\n");
2789                 goto out;
2790         }
2791
2792         ret = psp_tmr_terminate(psp);
2793         if (ret) {
2794                 DRM_ERROR("Failed to terminate tmr\n");
2795                 goto out;
2796         }
2797
2798         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2799         if (ret)
2800                 DRM_ERROR("PSP ring stop failed\n");
2801
2802 out:
2803         return ret;
2804 }
2805
2806 static int psp_resume(void *handle)
2807 {
2808         int ret;
2809         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2810         struct psp_context *psp = &adev->psp;
2811
2812         DRM_INFO("PSP is resuming...\n");
2813
2814         if (psp->mem_train_ctx.enable_mem_training) {
2815                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2816                 if (ret) {
2817                         DRM_ERROR("Failed to process memory training!\n");
2818                         return ret;
2819                 }
2820         }
2821
2822         mutex_lock(&adev->firmware.mutex);
2823
2824         ret = psp_hw_start(psp);
2825         if (ret)
2826                 goto failed;
2827
2828         ret = psp_load_non_psp_fw(psp);
2829         if (ret)
2830                 goto failed;
2831
2832         ret = psp_asd_initialize(psp);
2833         if (ret) {
2834                 DRM_ERROR("PSP load asd failed!\n");
2835                 goto failed;
2836         }
2837
2838         ret = psp_rl_load(adev);
2839         if (ret) {
2840                 dev_err(adev->dev, "PSP load RL failed!\n");
2841                 goto failed;
2842         }
2843
2844         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2845                 ret = psp_xgmi_initialize(psp, false, true);
2846                 /* Warning the XGMI seesion initialize failure
2847                  * Instead of stop driver initialization
2848                  */
2849                 if (ret)
2850                         dev_err(psp->adev->dev,
2851                                 "XGMI: Failed to initialize XGMI session\n");
2852         }
2853
2854         if (psp->ta_fw) {
2855                 ret = psp_ras_initialize(psp);
2856                 if (ret)
2857                         dev_err(psp->adev->dev,
2858                                         "RAS: Failed to initialize RAS\n");
2859
2860                 ret = psp_hdcp_initialize(psp);
2861                 if (ret)
2862                         dev_err(psp->adev->dev,
2863                                 "HDCP: Failed to initialize HDCP\n");
2864
2865                 ret = psp_dtm_initialize(psp);
2866                 if (ret)
2867                         dev_err(psp->adev->dev,
2868                                 "DTM: Failed to initialize DTM\n");
2869
2870                 ret = psp_rap_initialize(psp);
2871                 if (ret)
2872                         dev_err(psp->adev->dev,
2873                                 "RAP: Failed to initialize RAP\n");
2874
2875                 ret = psp_securedisplay_initialize(psp);
2876                 if (ret)
2877                         dev_err(psp->adev->dev,
2878                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2879         }
2880
2881         mutex_unlock(&adev->firmware.mutex);
2882
2883         return 0;
2884
2885 failed:
2886         DRM_ERROR("PSP resume failed\n");
2887         mutex_unlock(&adev->firmware.mutex);
2888         return ret;
2889 }
2890
2891 int psp_gpu_reset(struct amdgpu_device *adev)
2892 {
2893         int ret;
2894
2895         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2896                 return 0;
2897
2898         mutex_lock(&adev->psp.mutex);
2899         ret = psp_mode1_reset(&adev->psp);
2900         mutex_unlock(&adev->psp.mutex);
2901
2902         return ret;
2903 }
2904
2905 int psp_rlc_autoload_start(struct psp_context *psp)
2906 {
2907         int ret;
2908         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2909
2910         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2911
2912         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2913                                  psp->fence_buf_mc_addr);
2914
2915         release_psp_cmd_buf(psp);
2916
2917         return ret;
2918 }
2919
2920 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2921                         uint64_t cmd_gpu_addr, int cmd_size)
2922 {
2923         struct amdgpu_firmware_info ucode = {0};
2924
2925         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2926                 AMDGPU_UCODE_ID_VCN0_RAM;
2927         ucode.mc_addr = cmd_gpu_addr;
2928         ucode.ucode_size = cmd_size;
2929
2930         return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2931 }
2932
2933 int psp_ring_cmd_submit(struct psp_context *psp,
2934                         uint64_t cmd_buf_mc_addr,
2935                         uint64_t fence_mc_addr,
2936                         int index)
2937 {
2938         unsigned int psp_write_ptr_reg = 0;
2939         struct psp_gfx_rb_frame *write_frame;
2940         struct psp_ring *ring = &psp->km_ring;
2941         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2942         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2943                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2944         struct amdgpu_device *adev = psp->adev;
2945         uint32_t ring_size_dw = ring->ring_size / 4;
2946         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2947
2948         /* KM (GPCOM) prepare write pointer */
2949         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2950
2951         /* Update KM RB frame pointer to new frame */
2952         /* write_frame ptr increments by size of rb_frame in bytes */
2953         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2954         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2955                 write_frame = ring_buffer_start;
2956         else
2957                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2958         /* Check invalid write_frame ptr address */
2959         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2960                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2961                           ring_buffer_start, ring_buffer_end, write_frame);
2962                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2963                 return -EINVAL;
2964         }
2965
2966         /* Initialize KM RB frame */
2967         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2968
2969         /* Update KM RB frame */
2970         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2971         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2972         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2973         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2974         write_frame->fence_value = index;
2975         amdgpu_device_flush_hdp(adev, NULL);
2976
2977         /* Update the write Pointer in DWORDs */
2978         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2979         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2980         return 0;
2981 }
2982
2983 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
2984 {
2985         struct amdgpu_device *adev = psp->adev;
2986         char fw_name[PSP_FW_NAME_LEN];
2987         const struct psp_firmware_header_v1_0 *asd_hdr;
2988         int err = 0;
2989
2990         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2991         err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name);
2992         if (err)
2993                 goto out;
2994
2995         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2996         adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2997         adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2998         adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2999         adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
3000                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
3001         return 0;
3002 out:
3003         amdgpu_ucode_release(&adev->psp.asd_fw);
3004         return err;
3005 }
3006
3007 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
3008 {
3009         struct amdgpu_device *adev = psp->adev;
3010         char fw_name[PSP_FW_NAME_LEN];
3011         const struct psp_firmware_header_v1_0 *toc_hdr;
3012         int err = 0;
3013
3014         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
3015         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
3016         if (err)
3017                 goto out;
3018
3019         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
3020         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
3021         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
3022         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
3023         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
3024                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
3025         return 0;
3026 out:
3027         amdgpu_ucode_release(&adev->psp.toc_fw);
3028         return err;
3029 }
3030
3031 static int parse_sos_bin_descriptor(struct psp_context *psp,
3032                                    const struct psp_fw_bin_desc *desc,
3033                                    const struct psp_firmware_header_v2_0 *sos_hdr)
3034 {
3035         uint8_t *ucode_start_addr  = NULL;
3036
3037         if (!psp || !desc || !sos_hdr)
3038                 return -EINVAL;
3039
3040         ucode_start_addr  = (uint8_t *)sos_hdr +
3041                             le32_to_cpu(desc->offset_bytes) +
3042                             le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3043
3044         switch (desc->fw_type) {
3045         case PSP_FW_TYPE_PSP_SOS:
3046                 psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
3047                 psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
3048                 psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
3049                 psp->sos.start_addr        = ucode_start_addr;
3050                 break;
3051         case PSP_FW_TYPE_PSP_SYS_DRV:
3052                 psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
3053                 psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
3054                 psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
3055                 psp->sys.start_addr        = ucode_start_addr;
3056                 break;
3057         case PSP_FW_TYPE_PSP_KDB:
3058                 psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
3059                 psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
3060                 psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
3061                 psp->kdb.start_addr        = ucode_start_addr;
3062                 break;
3063         case PSP_FW_TYPE_PSP_TOC:
3064                 psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
3065                 psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
3066                 psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
3067                 psp->toc.start_addr        = ucode_start_addr;
3068                 break;
3069         case PSP_FW_TYPE_PSP_SPL:
3070                 psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
3071                 psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
3072                 psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
3073                 psp->spl.start_addr        = ucode_start_addr;
3074                 break;
3075         case PSP_FW_TYPE_PSP_RL:
3076                 psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
3077                 psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
3078                 psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
3079                 psp->rl.start_addr         = ucode_start_addr;
3080                 break;
3081         case PSP_FW_TYPE_PSP_SOC_DRV:
3082                 psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
3083                 psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
3084                 psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3085                 psp->soc_drv.start_addr         = ucode_start_addr;
3086                 break;
3087         case PSP_FW_TYPE_PSP_INTF_DRV:
3088                 psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
3089                 psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
3090                 psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
3091                 psp->intf_drv.start_addr        = ucode_start_addr;
3092                 break;
3093         case PSP_FW_TYPE_PSP_DBG_DRV:
3094                 psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
3095                 psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
3096                 psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3097                 psp->dbg_drv.start_addr         = ucode_start_addr;
3098                 break;
3099         case PSP_FW_TYPE_PSP_RAS_DRV:
3100                 psp->ras_drv.fw_version         = le32_to_cpu(desc->fw_version);
3101                 psp->ras_drv.feature_version    = le32_to_cpu(desc->fw_version);
3102                 psp->ras_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3103                 psp->ras_drv.start_addr         = ucode_start_addr;
3104                 break;
3105         default:
3106                 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3107                 break;
3108         }
3109
3110         return 0;
3111 }
3112
3113 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3114 {
3115         const struct psp_firmware_header_v1_0 *sos_hdr;
3116         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3117         uint8_t *ucode_array_start_addr;
3118
3119         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3120         ucode_array_start_addr = (uint8_t *)sos_hdr +
3121                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3122
3123         if (adev->gmc.xgmi.connected_to_cpu ||
3124             (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3125                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3126                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3127
3128                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3129                 adev->psp.sys.start_addr = ucode_array_start_addr;
3130
3131                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3132                 adev->psp.sos.start_addr = ucode_array_start_addr +
3133                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
3134         } else {
3135                 /* Load alternate PSP SOS FW */
3136                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3137
3138                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3139                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3140
3141                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3142                 adev->psp.sys.start_addr = ucode_array_start_addr +
3143                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3144
3145                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3146                 adev->psp.sos.start_addr = ucode_array_start_addr +
3147                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3148         }
3149
3150         if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3151                 dev_warn(adev->dev, "PSP SOS FW not available");
3152                 return -EINVAL;
3153         }
3154
3155         return 0;
3156 }
3157
3158 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
3159 {
3160         struct amdgpu_device *adev = psp->adev;
3161         char fw_name[PSP_FW_NAME_LEN];
3162         const struct psp_firmware_header_v1_0 *sos_hdr;
3163         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3164         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3165         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3166         const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3167         int err = 0;
3168         uint8_t *ucode_array_start_addr;
3169         int fw_index = 0;
3170
3171         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3172         err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name);
3173         if (err)
3174                 goto out;
3175
3176         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3177         ucode_array_start_addr = (uint8_t *)sos_hdr +
3178                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3179         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3180
3181         switch (sos_hdr->header.header_version_major) {
3182         case 1:
3183                 err = psp_init_sos_base_fw(adev);
3184                 if (err)
3185                         goto out;
3186
3187                 if (sos_hdr->header.header_version_minor == 1) {
3188                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3189                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3190                         adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3191                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3192                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3193                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3194                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3195                 }
3196                 if (sos_hdr->header.header_version_minor == 2) {
3197                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3198                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3199                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3200                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3201                 }
3202                 if (sos_hdr->header.header_version_minor == 3) {
3203                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3204                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3205                         adev->psp.toc.start_addr = ucode_array_start_addr +
3206                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3207                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3208                         adev->psp.kdb.start_addr = ucode_array_start_addr +
3209                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3210                         adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3211                         adev->psp.spl.start_addr = ucode_array_start_addr +
3212                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3213                         adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3214                         adev->psp.rl.start_addr = ucode_array_start_addr +
3215                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3216                 }
3217                 break;
3218         case 2:
3219                 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3220
3221                 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3222                         dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3223                         err = -EINVAL;
3224                         goto out;
3225                 }
3226
3227                 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3228                         err = parse_sos_bin_descriptor(psp,
3229                                                        &sos_hdr_v2_0->psp_fw_bin[fw_index],
3230                                                        sos_hdr_v2_0);
3231                         if (err)
3232                                 goto out;
3233                 }
3234                 break;
3235         default:
3236                 dev_err(adev->dev,
3237                         "unsupported psp sos firmware\n");
3238                 err = -EINVAL;
3239                 goto out;
3240         }
3241
3242         return 0;
3243 out:
3244         amdgpu_ucode_release(&adev->psp.sos_fw);
3245
3246         return err;
3247 }
3248
3249 static int parse_ta_bin_descriptor(struct psp_context *psp,
3250                                    const struct psp_fw_bin_desc *desc,
3251                                    const struct ta_firmware_header_v2_0 *ta_hdr)
3252 {
3253         uint8_t *ucode_start_addr  = NULL;
3254
3255         if (!psp || !desc || !ta_hdr)
3256                 return -EINVAL;
3257
3258         ucode_start_addr  = (uint8_t *)ta_hdr +
3259                             le32_to_cpu(desc->offset_bytes) +
3260                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3261
3262         switch (desc->fw_type) {
3263         case TA_FW_TYPE_PSP_ASD:
3264                 psp->asd_context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3265                 psp->asd_context.bin_desc.feature_version   = le32_to_cpu(desc->fw_version);
3266                 psp->asd_context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3267                 psp->asd_context.bin_desc.start_addr        = ucode_start_addr;
3268                 break;
3269         case TA_FW_TYPE_PSP_XGMI:
3270                 psp->xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3271                 psp->xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3272                 psp->xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;
3273                 break;
3274         case TA_FW_TYPE_PSP_RAS:
3275                 psp->ras_context.context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3276                 psp->ras_context.context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3277                 psp->ras_context.context.bin_desc.start_addr        = ucode_start_addr;
3278                 break;
3279         case TA_FW_TYPE_PSP_HDCP:
3280                 psp->hdcp_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3281                 psp->hdcp_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3282                 psp->hdcp_context.context.bin_desc.start_addr       = ucode_start_addr;
3283                 break;
3284         case TA_FW_TYPE_PSP_DTM:
3285                 psp->dtm_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3286                 psp->dtm_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3287                 psp->dtm_context.context.bin_desc.start_addr       = ucode_start_addr;
3288                 break;
3289         case TA_FW_TYPE_PSP_RAP:
3290                 psp->rap_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3291                 psp->rap_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3292                 psp->rap_context.context.bin_desc.start_addr       = ucode_start_addr;
3293                 break;
3294         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3295                 psp->securedisplay_context.context.bin_desc.fw_version =
3296                         le32_to_cpu(desc->fw_version);
3297                 psp->securedisplay_context.context.bin_desc.size_bytes =
3298                         le32_to_cpu(desc->size_bytes);
3299                 psp->securedisplay_context.context.bin_desc.start_addr =
3300                         ucode_start_addr;
3301                 break;
3302         default:
3303                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3304                 break;
3305         }
3306
3307         return 0;
3308 }
3309
3310 static int parse_ta_v1_microcode(struct psp_context *psp)
3311 {
3312         const struct ta_firmware_header_v1_0 *ta_hdr;
3313         struct amdgpu_device *adev = psp->adev;
3314
3315         ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
3316
3317         if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
3318                 return -EINVAL;
3319
3320         adev->psp.xgmi_context.context.bin_desc.fw_version =
3321                 le32_to_cpu(ta_hdr->xgmi.fw_version);
3322         adev->psp.xgmi_context.context.bin_desc.size_bytes =
3323                 le32_to_cpu(ta_hdr->xgmi.size_bytes);
3324         adev->psp.xgmi_context.context.bin_desc.start_addr =
3325                 (uint8_t *)ta_hdr +
3326                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3327
3328         adev->psp.ras_context.context.bin_desc.fw_version =
3329                 le32_to_cpu(ta_hdr->ras.fw_version);
3330         adev->psp.ras_context.context.bin_desc.size_bytes =
3331                 le32_to_cpu(ta_hdr->ras.size_bytes);
3332         adev->psp.ras_context.context.bin_desc.start_addr =
3333                 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
3334                 le32_to_cpu(ta_hdr->ras.offset_bytes);
3335
3336         adev->psp.hdcp_context.context.bin_desc.fw_version =
3337                 le32_to_cpu(ta_hdr->hdcp.fw_version);
3338         adev->psp.hdcp_context.context.bin_desc.size_bytes =
3339                 le32_to_cpu(ta_hdr->hdcp.size_bytes);
3340         adev->psp.hdcp_context.context.bin_desc.start_addr =
3341                 (uint8_t *)ta_hdr +
3342                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3343
3344         adev->psp.dtm_context.context.bin_desc.fw_version =
3345                 le32_to_cpu(ta_hdr->dtm.fw_version);
3346         adev->psp.dtm_context.context.bin_desc.size_bytes =
3347                 le32_to_cpu(ta_hdr->dtm.size_bytes);
3348         adev->psp.dtm_context.context.bin_desc.start_addr =
3349                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3350                 le32_to_cpu(ta_hdr->dtm.offset_bytes);
3351
3352         adev->psp.securedisplay_context.context.bin_desc.fw_version =
3353                 le32_to_cpu(ta_hdr->securedisplay.fw_version);
3354         adev->psp.securedisplay_context.context.bin_desc.size_bytes =
3355                 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
3356         adev->psp.securedisplay_context.context.bin_desc.start_addr =
3357                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3358                 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
3359
3360         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
3361
3362         return 0;
3363 }
3364
3365 static int parse_ta_v2_microcode(struct psp_context *psp)
3366 {
3367         const struct ta_firmware_header_v2_0 *ta_hdr;
3368         struct amdgpu_device *adev = psp->adev;
3369         int err = 0;
3370         int ta_index = 0;
3371
3372         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3373
3374         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
3375                 return -EINVAL;
3376
3377         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3378                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3379                 return -EINVAL;
3380         }
3381
3382         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3383                 err = parse_ta_bin_descriptor(psp,
3384                                               &ta_hdr->ta_fw_bin[ta_index],
3385                                               ta_hdr);
3386                 if (err)
3387                         return err;
3388         }
3389
3390         return 0;
3391 }
3392
3393 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
3394 {
3395         const struct common_firmware_header *hdr;
3396         struct amdgpu_device *adev = psp->adev;
3397         char fw_name[PSP_FW_NAME_LEN];
3398         int err;
3399
3400         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3401         err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name);
3402         if (err)
3403                 return err;
3404
3405         hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
3406         switch (le16_to_cpu(hdr->header_version_major)) {
3407         case 1:
3408                 err = parse_ta_v1_microcode(psp);
3409                 break;
3410         case 2:
3411                 err = parse_ta_v2_microcode(psp);
3412                 break;
3413         default:
3414                 dev_err(adev->dev, "unsupported TA header version\n");
3415                 err = -EINVAL;
3416         }
3417
3418         if (err)
3419                 amdgpu_ucode_release(&adev->psp.ta_fw);
3420
3421         return err;
3422 }
3423
3424 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
3425 {
3426         struct amdgpu_device *adev = psp->adev;
3427         char fw_name[PSP_FW_NAME_LEN];
3428         const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3429         struct amdgpu_firmware_info *info = NULL;
3430         int err = 0;
3431
3432         if (!amdgpu_sriov_vf(adev)) {
3433                 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3434                 return -EINVAL;
3435         }
3436
3437         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3438         err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name);
3439         if (err) {
3440                 if (err == -ENODEV) {
3441                         dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3442                         err = 0;
3443                         goto out;
3444                 }
3445                 dev_err(adev->dev, "fail to initialize cap microcode\n");
3446         }
3447
3448         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3449         info->ucode_id = AMDGPU_UCODE_ID_CAP;
3450         info->fw = adev->psp.cap_fw;
3451         cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3452                 adev->psp.cap_fw->data;
3453         adev->firmware.fw_size += ALIGN(
3454                         le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3455         adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3456         adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3457         adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3458
3459         return 0;
3460
3461 out:
3462         amdgpu_ucode_release(&adev->psp.cap_fw);
3463         return err;
3464 }
3465
3466 static int psp_set_clockgating_state(void *handle,
3467                                      enum amd_clockgating_state state)
3468 {
3469         return 0;
3470 }
3471
3472 static int psp_set_powergating_state(void *handle,
3473                                      enum amd_powergating_state state)
3474 {
3475         return 0;
3476 }
3477
3478 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3479                                          struct device_attribute *attr,
3480                                          char *buf)
3481 {
3482         struct drm_device *ddev = dev_get_drvdata(dev);
3483         struct amdgpu_device *adev = drm_to_adev(ddev);
3484         uint32_t fw_ver;
3485         int ret;
3486
3487         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3488                 DRM_INFO("PSP block is not ready yet.");
3489                 return -EBUSY;
3490         }
3491
3492         mutex_lock(&adev->psp.mutex);
3493         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3494         mutex_unlock(&adev->psp.mutex);
3495
3496         if (ret) {
3497                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3498                 return ret;
3499         }
3500
3501         return sysfs_emit(buf, "%x\n", fw_ver);
3502 }
3503
3504 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3505                                                        struct device_attribute *attr,
3506                                                        const char *buf,
3507                                                        size_t count)
3508 {
3509         struct drm_device *ddev = dev_get_drvdata(dev);
3510         struct amdgpu_device *adev = drm_to_adev(ddev);
3511         int ret, idx;
3512         char fw_name[100];
3513         const struct firmware *usbc_pd_fw;
3514         struct amdgpu_bo *fw_buf_bo = NULL;
3515         uint64_t fw_pri_mc_addr;
3516         void *fw_pri_cpu_addr;
3517
3518         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3519                 DRM_INFO("PSP block is not ready yet.");
3520                 return -EBUSY;
3521         }
3522
3523         if (!drm_dev_enter(ddev, &idx))
3524                 return -ENODEV;
3525
3526         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3527         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3528         if (ret)
3529                 goto fail;
3530
3531         /* LFB address which is aligned to 1MB boundary per PSP request */
3532         ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3533                                       AMDGPU_GEM_DOMAIN_VRAM |
3534                                       AMDGPU_GEM_DOMAIN_GTT,
3535                                       &fw_buf_bo, &fw_pri_mc_addr,
3536                                       &fw_pri_cpu_addr);
3537         if (ret)
3538                 goto rel_buf;
3539
3540         memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3541
3542         mutex_lock(&adev->psp.mutex);
3543         ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3544         mutex_unlock(&adev->psp.mutex);
3545
3546         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3547
3548 rel_buf:
3549         release_firmware(usbc_pd_fw);
3550 fail:
3551         if (ret) {
3552                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3553                 count = ret;
3554         }
3555
3556         drm_dev_exit(idx);
3557         return count;
3558 }
3559
3560 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3561 {
3562         int idx;
3563
3564         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3565                 return;
3566
3567         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3568         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3569
3570         drm_dev_exit(idx);
3571 }
3572
3573 static DEVICE_ATTR(usbc_pd_fw, 0644,
3574                    psp_usbc_pd_fw_sysfs_read,
3575                    psp_usbc_pd_fw_sysfs_write);
3576
3577 int is_psp_fw_valid(struct psp_bin_desc bin)
3578 {
3579         return bin.size_bytes;
3580 }
3581
3582 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3583                                         struct bin_attribute *bin_attr,
3584                                         char *buffer, loff_t pos, size_t count)
3585 {
3586         struct device *dev = kobj_to_dev(kobj);
3587         struct drm_device *ddev = dev_get_drvdata(dev);
3588         struct amdgpu_device *adev = drm_to_adev(ddev);
3589
3590         adev->psp.vbflash_done = false;
3591
3592         /* Safeguard against memory drain */
3593         if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3594                 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3595                 kvfree(adev->psp.vbflash_tmp_buf);
3596                 adev->psp.vbflash_tmp_buf = NULL;
3597                 adev->psp.vbflash_image_size = 0;
3598                 return -ENOMEM;
3599         }
3600
3601         /* TODO Just allocate max for now and optimize to realloc later if needed */
3602         if (!adev->psp.vbflash_tmp_buf) {
3603                 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3604                 if (!adev->psp.vbflash_tmp_buf)
3605                         return -ENOMEM;
3606         }
3607
3608         mutex_lock(&adev->psp.mutex);
3609         memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3610         adev->psp.vbflash_image_size += count;
3611         mutex_unlock(&adev->psp.mutex);
3612
3613         dev_dbg(adev->dev, "IFWI staged for update");
3614
3615         return count;
3616 }
3617
3618 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3619                                        struct bin_attribute *bin_attr, char *buffer,
3620                                        loff_t pos, size_t count)
3621 {
3622         struct device *dev = kobj_to_dev(kobj);
3623         struct drm_device *ddev = dev_get_drvdata(dev);
3624         struct amdgpu_device *adev = drm_to_adev(ddev);
3625         struct amdgpu_bo *fw_buf_bo = NULL;
3626         uint64_t fw_pri_mc_addr;
3627         void *fw_pri_cpu_addr;
3628         int ret;
3629
3630         if (adev->psp.vbflash_image_size == 0)
3631                 return -EINVAL;
3632
3633         dev_dbg(adev->dev, "PSP IFWI flash process initiated");
3634
3635         ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3636                                         AMDGPU_GPU_PAGE_SIZE,
3637                                         AMDGPU_GEM_DOMAIN_VRAM,
3638                                         &fw_buf_bo,
3639                                         &fw_pri_mc_addr,
3640                                         &fw_pri_cpu_addr);
3641         if (ret)
3642                 goto rel_buf;
3643
3644         memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3645
3646         mutex_lock(&adev->psp.mutex);
3647         ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3648         mutex_unlock(&adev->psp.mutex);
3649
3650         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3651
3652 rel_buf:
3653         kvfree(adev->psp.vbflash_tmp_buf);
3654         adev->psp.vbflash_tmp_buf = NULL;
3655         adev->psp.vbflash_image_size = 0;
3656
3657         if (ret) {
3658                 dev_err(adev->dev, "Failed to load IFWI, err = %d", ret);
3659                 return ret;
3660         }
3661
3662         dev_dbg(adev->dev, "PSP IFWI flash process done");
3663         return 0;
3664 }
3665
3666 static struct bin_attribute psp_vbflash_bin_attr = {
3667         .attr = {.name = "psp_vbflash", .mode = 0660},
3668         .size = 0,
3669         .write = amdgpu_psp_vbflash_write,
3670         .read = amdgpu_psp_vbflash_read,
3671 };
3672
3673 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3674                                          struct device_attribute *attr,
3675                                          char *buf)
3676 {
3677         struct drm_device *ddev = dev_get_drvdata(dev);
3678         struct amdgpu_device *adev = drm_to_adev(ddev);
3679         uint32_t vbflash_status;
3680
3681         vbflash_status = psp_vbflash_status(&adev->psp);
3682         if (!adev->psp.vbflash_done)
3683                 vbflash_status = 0;
3684         else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3685                 vbflash_status = 1;
3686
3687         return sysfs_emit(buf, "0x%x\n", vbflash_status);
3688 }
3689 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);
3690
3691 static struct attribute *flash_attrs[] = {
3692         &dev_attr_psp_vbflash_status.attr,
3693         &psp_vbflash_bin_attr.attr,
3694         &dev_attr_usbc_pd_fw.attr,
3695         NULL
3696 };
3697
3698 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
3699 {
3700         struct device *dev = kobj_to_dev(kobj);
3701         struct drm_device *ddev = dev_get_drvdata(dev);
3702         struct amdgpu_device *adev = drm_to_adev(ddev);
3703
3704         if (amdgpu_sriov_vf(adev))
3705                 return 0;
3706
3707         switch (adev->ip_versions[MP0_HWIP][0]) {
3708         case IP_VERSION(11, 0, 0):
3709         case IP_VERSION(11, 0, 7):
3710                 if (attr == &dev_attr_usbc_pd_fw.attr)
3711                         return 0660;
3712                 return 0;
3713         case IP_VERSION(13, 0, 0):
3714         case IP_VERSION(13, 0, 7):
3715                 if (attr == &dev_attr_usbc_pd_fw.attr)
3716                         return 0;
3717                 else if (attr == &psp_vbflash_bin_attr.attr)
3718                         return 0660;
3719                 return 0440;
3720         default:
3721                 return 0;
3722         }
3723 }
3724
3725 const struct attribute_group amdgpu_flash_attr_group = {
3726         .attrs = flash_attrs,
3727         .is_visible = amdgpu_flash_attr_is_visible,
3728 };
3729
3730 const struct amd_ip_funcs psp_ip_funcs = {
3731         .name = "psp",
3732         .early_init = psp_early_init,
3733         .late_init = NULL,
3734         .sw_init = psp_sw_init,
3735         .sw_fini = psp_sw_fini,
3736         .hw_init = psp_hw_init,
3737         .hw_fini = psp_hw_fini,
3738         .suspend = psp_suspend,
3739         .resume = psp_resume,
3740         .is_idle = NULL,
3741         .check_soft_reset = NULL,
3742         .wait_for_idle = NULL,
3743         .soft_reset = NULL,
3744         .set_clockgating_state = psp_set_clockgating_state,
3745         .set_powergating_state = psp_set_powergating_state,
3746 };
3747
3748 const struct amdgpu_ip_block_version psp_v3_1_ip_block = {
3749         .type = AMD_IP_BLOCK_TYPE_PSP,
3750         .major = 3,
3751         .minor = 1,
3752         .rev = 0,
3753         .funcs = &psp_ip_funcs,
3754 };
3755
3756 const struct amdgpu_ip_block_version psp_v10_0_ip_block = {
3757         .type = AMD_IP_BLOCK_TYPE_PSP,
3758         .major = 10,
3759         .minor = 0,
3760         .rev = 0,
3761         .funcs = &psp_ip_funcs,
3762 };
3763
3764 const struct amdgpu_ip_block_version psp_v11_0_ip_block = {
3765         .type = AMD_IP_BLOCK_TYPE_PSP,
3766         .major = 11,
3767         .minor = 0,
3768         .rev = 0,
3769         .funcs = &psp_ip_funcs,
3770 };
3771
3772 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3773         .type = AMD_IP_BLOCK_TYPE_PSP,
3774         .major = 11,
3775         .minor = 0,
3776         .rev = 8,
3777         .funcs = &psp_ip_funcs,
3778 };
3779
3780 const struct amdgpu_ip_block_version psp_v12_0_ip_block = {
3781         .type = AMD_IP_BLOCK_TYPE_PSP,
3782         .major = 12,
3783         .minor = 0,
3784         .rev = 0,
3785         .funcs = &psp_ip_funcs,
3786 };
3787
3788 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3789         .type = AMD_IP_BLOCK_TYPE_PSP,
3790         .major = 13,
3791         .minor = 0,
3792         .rev = 0,
3793         .funcs = &psp_ip_funcs,
3794 };
3795
3796 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3797         .type = AMD_IP_BLOCK_TYPE_PSP,
3798         .major = 13,
3799         .minor = 0,
3800         .rev = 4,
3801         .funcs = &psp_ip_funcs,
3802 };