drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33 #include "psp_v10_0.h"
  34 #include "psp_v11_0.h"
  35 #include "psp_v12_0.h"
  36
  37 #include "amdgpu_ras.h"
  38
  39 static void psp_set_funcs(struct amdgpu_device *adev);
  40
  41 static int psp_early_init(void *handle)
  42 {
  43         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  44         struct psp_context *psp = &adev->psp;
  45
  46         psp_set_funcs(adev);
  47
  48         switch (adev->asic_type) {
  49         case CHIP_VEGA10:
  50         case CHIP_VEGA12:
  51                 psp_v3_1_set_psp_funcs(psp);
  52                 psp->autoload_supported = false;
  53                 break;
  54         case CHIP_RAVEN:
  55                 psp_v10_0_set_psp_funcs(psp);
  56                 psp->autoload_supported = false;
  57                 break;
  58         case CHIP_VEGA20:
  59         case CHIP_ARCTURUS:
  60                 psp_v11_0_set_psp_funcs(psp);
  61                 psp->autoload_supported = false;
  62                 break;
  63         case CHIP_NAVI10:
  64         case CHIP_NAVI14:
  65         case CHIP_NAVI12:
  66                 psp_v11_0_set_psp_funcs(psp);
  67                 psp->autoload_supported = true;
  68                 break;
  69         case CHIP_RENOIR:
  70                 psp_v12_0_set_psp_funcs(psp);
  71                 break;
  72         default:
  73                 return -EINVAL;
  74         }
  75
  76         psp->adev = adev;
  77
  78         return 0;
  79 }
  80
  81 static int psp_sw_init(void *handle)
  82 {
  83         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  84         struct psp_context *psp = &adev->psp;
  85         int ret;
  86
  87         ret = psp_init_microcode(psp);
  88         if (ret) {
  89                 DRM_ERROR("Failed to load psp firmware!\n");
  90                 return ret;
  91         }
  92
  93         ret = psp_mem_training_init(psp);
  94         if (ret) {
  95                 DRM_ERROR("Failed to initialize memory training!\n");
  96                 return ret;
  97         }
  98         ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
  99         if (ret) {
 100                 DRM_ERROR("Failed to process memory training!\n");
 101                 return ret;
 102         }
 103
 104         return 0;
 105 }
 106
 107 static int psp_sw_fini(void *handle)
 108 {
 109         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 110
 111         psp_mem_training_fini(&adev->psp);
 112         release_firmware(adev->psp.sos_fw);
 113         adev->psp.sos_fw = NULL;
 114         release_firmware(adev->psp.asd_fw);
 115         adev->psp.asd_fw = NULL;
 116         if (adev->psp.ta_fw) {
 117                 release_firmware(adev->psp.ta_fw);
 118                 adev->psp.ta_fw = NULL;
 119         }
 120         return 0;
 121 }
 122
 123 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 124                  uint32_t reg_val, uint32_t mask, bool check_changed)
 125 {
 126         uint32_t val;
 127         int i;
 128         struct amdgpu_device *adev = psp->adev;
 129
 130         for (i = 0; i < adev->usec_timeout; i++) {
 131                 val = RREG32(reg_index);
 132                 if (check_changed) {
 133                         if (val != reg_val)
 134                                 return 0;
 135                 } else {
 136                         if ((val & mask) == reg_val)
 137                                 return 0;
 138                 }
 139                 udelay(1);
 140         }
 141
 142         return -ETIME;
 143 }
 144
 145 static int
 146 psp_cmd_submit_buf(struct psp_context *psp,
 147                    struct amdgpu_firmware_info *ucode,
 148                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 149 {
 150         int ret;
 151         int index;
 152         int timeout = 2000;
 153
 154         mutex_lock(&psp->mutex);
 155
 156         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 157
 158         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 159
 160         index = atomic_inc_return(&psp->fence_value);
 161         ret = psp_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 162         if (ret) {
 163                 atomic_dec(&psp->fence_value);
 164                 mutex_unlock(&psp->mutex);
 165                 return ret;
 166         }
 167
 168         amdgpu_asic_invalidate_hdp(psp->adev, NULL);
 169         while (*((unsigned int *)psp->fence_buf) != index) {
 170                 if (--timeout == 0)
 171                         break;
 172                 /*
 173                  * Shouldn't wait for timeout when err_event_athub occurs,
 174                  * because gpu reset thread triggered and lock resource should
 175                  * be released for psp resume sequence.
 176                  */
 177                 if (amdgpu_ras_intr_triggered())
 178                         break;
 179                 msleep(1);
 180                 amdgpu_asic_invalidate_hdp(psp->adev, NULL);
 181         }
 182
 183         /* In some cases, psp response status is not 0 even there is no
 184          * problem while the command is submitted. Some version of PSP FW
 185          * doesn't write 0 to that field.
 186          * So here we would like to only print a warning instead of an error
 187          * during psp initialization to avoid breaking hw_init and it doesn't
 188          * return -EINVAL.
 189          */
 190         if (psp->cmd_buf_mem->resp.status || !timeout) {
 191                 if (ucode)
 192                         DRM_WARN("failed to load ucode id (%d) ",
 193                                   ucode->ucode_id);
 194                 DRM_DEBUG_DRIVER("psp command (0x%X) failed and response status is (0x%X)\n",
 195                          psp->cmd_buf_mem->cmd_id,
 196                          psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK);
 197                 if (!timeout) {
 198                         mutex_unlock(&psp->mutex);
 199                         return -EINVAL;
 200                 }
 201         }
 202
 203         /* get xGMI session id from response buffer */
 204         cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
 205
 206         if (ucode) {
 207                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 208                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 209         }
 210         mutex_unlock(&psp->mutex);
 211
 212         return ret;
 213 }
 214
 215 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 216                                  struct psp_gfx_cmd_resp *cmd,
 217                                  uint64_t tmr_mc, uint32_t size)
 218 {
 219         if (psp_support_vmr_ring(psp))
 220                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 221         else
 222                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 223         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 224         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 225         cmd->cmd.cmd_setup_tmr.buf_size = size;
 226 }
 227
 228 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 229                                       uint64_t pri_buf_mc, uint32_t size)
 230 {
 231         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 232         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 233         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 234         cmd->cmd.cmd_load_toc.toc_size = size;
 235 }
 236
 237 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 238 static int psp_load_toc(struct psp_context *psp,
 239                         uint32_t *tmr_size)
 240 {
 241         int ret;
 242         struct psp_gfx_cmd_resp *cmd;
 243
 244         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 245         if (!cmd)
 246                 return -ENOMEM;
 247         /* Copy toc to psp firmware private buffer */
 248         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 249         memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
 250
 251         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
 252
 253         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 254                                  psp->fence_buf_mc_addr);
 255         if (!ret)
 256                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 257         kfree(cmd);
 258         return ret;
 259 }
 260
 261 /* Set up Trusted Memory Region */
 262 static int psp_tmr_init(struct psp_context *psp)
 263 {
 264         int ret;
 265         int tmr_size;
 266         void *tmr_buf;
 267         void **pptr;
 268
 269         /*
 270          * According to HW engineer, they prefer the TMR address be "naturally
 271          * aligned" , e.g. the start address be an integer divide of TMR size.
 272          *
 273          * Note: this memory need be reserved till the driver
 274          * uninitializes.
 275          */
 276         tmr_size = PSP_TMR_SIZE;
 277
 278         /* For ASICs support RLC autoload, psp will parse the toc
 279          * and calculate the total size of TMR needed */
 280         if (!amdgpu_sriov_vf(psp->adev) &&
 281             psp->toc_start_addr &&
 282             psp->toc_bin_size &&
 283             psp->fw_pri_buf) {
 284                 ret = psp_load_toc(psp, &tmr_size);
 285                 if (ret) {
 286                         DRM_ERROR("Failed to load toc\n");
 287                         return ret;
 288                 }
 289         }
 290
 291         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 292         ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
 293                                       AMDGPU_GEM_DOMAIN_VRAM,
 294                                       &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 295
 296         return ret;
 297 }
 298
 299 static int psp_tmr_load(struct psp_context *psp)
 300 {
 301         int ret;
 302         struct psp_gfx_cmd_resp *cmd;
 303
 304         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 305         if (!cmd)
 306                 return -ENOMEM;
 307
 308         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
 309                              amdgpu_bo_size(psp->tmr_bo));
 310         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 311                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 312
 313         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 314                                  psp->fence_buf_mc_addr);
 315
 316         kfree(cmd);
 317
 318         return ret;
 319 }
 320
 321 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 322                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 323                                  uint32_t size, uint32_t shared_size)
 324 {
 325         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 326         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 327         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 328         cmd->cmd.cmd_load_ta.app_len = size;
 329
 330         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 331         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 332         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 333 }
 334
 335 static int psp_asd_init(struct psp_context *psp)
 336 {
 337         int ret;
 338
 339         /*
 340          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 341          * physical) for shared ASD <-> Driver
 342          */
 343         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 344                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 345                                       &psp->asd_shared_bo,
 346                                       &psp->asd_shared_mc_addr,
 347                                       &psp->asd_shared_buf);
 348
 349         return ret;
 350 }
 351
 352 static int psp_asd_load(struct psp_context *psp)
 353 {
 354         int ret;
 355         struct psp_gfx_cmd_resp *cmd;
 356
 357         /* If PSP version doesn't match ASD version, asd loading will be failed.
 358          * add workaround to bypass it for sriov now.
 359          * TODO: add version check to make it common
 360          */
 361         if (amdgpu_sriov_vf(psp->adev))
 362                 return 0;
 363
 364         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 365         if (!cmd)
 366                 return -ENOMEM;
 367
 368         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 369         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 370
 371         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 372                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 373
 374         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 375                                  psp->fence_buf_mc_addr);
 376
 377         kfree(cmd);
 378
 379         return ret;
 380 }
 381
 382 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 383                 uint32_t id, uint32_t value)
 384 {
 385         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
 386         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
 387         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
 388 }
 389
 390 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 391                 uint32_t value)
 392 {
 393         struct psp_gfx_cmd_resp *cmd = NULL;
 394         int ret = 0;
 395
 396         if (reg >= PSP_REG_LAST)
 397                 return -EINVAL;
 398
 399         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 400         if (!cmd)
 401                 return -ENOMEM;
 402
 403         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 404         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 405
 406         kfree(cmd);
 407         return ret;
 408 }
 409
 410 static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 411                                           uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared,
 412                                           uint32_t xgmi_ta_size, uint32_t shared_size)
 413 {
 414         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 415         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc);
 416         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc);
 417         cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size;
 418
 419         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared);
 420         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared);
 421         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 422 }
 423
 424 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 425 {
 426         int ret;
 427
 428         /*
 429          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 430          * physical) for xgmi ta <-> Driver
 431          */
 432         ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
 433                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 434                                       &psp->xgmi_context.xgmi_shared_bo,
 435                                       &psp->xgmi_context.xgmi_shared_mc_addr,
 436                                       &psp->xgmi_context.xgmi_shared_buf);
 437
 438         return ret;
 439 }
 440
 441 static int psp_xgmi_load(struct psp_context *psp)
 442 {
 443         int ret;
 444         struct psp_gfx_cmd_resp *cmd;
 445
 446         /*
 447          * TODO: bypass the loading in sriov for now
 448          */
 449         if (amdgpu_sriov_vf(psp->adev))
 450                 return 0;
 451
 452         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 453         if (!cmd)
 454                 return -ENOMEM;
 455
 456         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 457         memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
 458
 459         psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 460                                       psp->xgmi_context.xgmi_shared_mc_addr,
 461                                       psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE);
 462
 463         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 464                                  psp->fence_buf_mc_addr);
 465
 466         if (!ret) {
 467                 psp->xgmi_context.initialized = 1;
 468                 psp->xgmi_context.session_id = cmd->resp.session_id;
 469         }
 470
 471         kfree(cmd);
 472
 473         return ret;
 474 }
 475
 476 static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 477                                             uint32_t xgmi_session_id)
 478 {
 479         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 480         cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id;
 481 }
 482
 483 static int psp_xgmi_unload(struct psp_context *psp)
 484 {
 485         int ret;
 486         struct psp_gfx_cmd_resp *cmd;
 487
 488         /*
 489          * TODO: bypass the unloading in sriov for now
 490          */
 491         if (amdgpu_sriov_vf(psp->adev))
 492                 return 0;
 493
 494         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 495         if (!cmd)
 496                 return -ENOMEM;
 497
 498         psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
 499
 500         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 501                                  psp->fence_buf_mc_addr);
 502
 503         kfree(cmd);
 504
 505         return ret;
 506 }
 507
 508 static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 509                                             uint32_t ta_cmd_id,
 510                                             uint32_t xgmi_session_id)
 511 {
 512         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 513         cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id;
 514         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 515         /* Note: cmd_invoke_cmd.buf is not used for now */
 516 }
 517
 518 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 519 {
 520         int ret;
 521         struct psp_gfx_cmd_resp *cmd;
 522
 523         /*
 524          * TODO: bypass the loading in sriov for now
 525         */
 526         if (amdgpu_sriov_vf(psp->adev))
 527                 return 0;
 528
 529         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 530         if (!cmd)
 531                 return -ENOMEM;
 532
 533         psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 534                                         psp->xgmi_context.session_id);
 535
 536         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 537                                  psp->fence_buf_mc_addr);
 538
 539         kfree(cmd);
 540
 541         return ret;
 542 }
 543
 544 static int psp_xgmi_terminate(struct psp_context *psp)
 545 {
 546         int ret;
 547
 548         if (!psp->xgmi_context.initialized)
 549                 return 0;
 550
 551         ret = psp_xgmi_unload(psp);
 552         if (ret)
 553                 return ret;
 554
 555         psp->xgmi_context.initialized = 0;
 556
 557         /* free xgmi shared memory */
 558         amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
 559                         &psp->xgmi_context.xgmi_shared_mc_addr,
 560                         &psp->xgmi_context.xgmi_shared_buf);
 561
 562         return 0;
 563 }
 564
 565 static int psp_xgmi_initialize(struct psp_context *psp)
 566 {
 567         struct ta_xgmi_shared_memory *xgmi_cmd;
 568         int ret;
 569
 570         if (!psp->adev->psp.ta_fw ||
 571             !psp->adev->psp.ta_xgmi_ucode_size ||
 572             !psp->adev->psp.ta_xgmi_start_addr)
 573                 return -ENOENT;
 574
 575         if (!psp->xgmi_context.initialized) {
 576                 ret = psp_xgmi_init_shared_buf(psp);
 577                 if (ret)
 578                         return ret;
 579         }
 580
 581         /* Load XGMI TA */
 582         ret = psp_xgmi_load(psp);
 583         if (ret)
 584                 return ret;
 585
 586         /* Initialize XGMI session */
 587         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
 588         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 589         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
 590
 591         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 592
 593         return ret;
 594 }
 595
 596 // ras begin
 597 static void psp_prep_ras_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 598                 uint64_t ras_ta_mc, uint64_t ras_mc_shared,
 599                 uint32_t ras_ta_size, uint32_t shared_size)
 600 {
 601         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 602         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ras_ta_mc);
 603         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ras_ta_mc);
 604         cmd->cmd.cmd_load_ta.app_len = ras_ta_size;
 605
 606         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ras_mc_shared);
 607         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ras_mc_shared);
 608         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 609 }
 610
 611 static int psp_ras_init_shared_buf(struct psp_context *psp)
 612 {
 613         int ret;
 614
 615         /*
 616          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 617          * physical) for ras ta <-> Driver
 618          */
 619         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
 620                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 621                         &psp->ras.ras_shared_bo,
 622                         &psp->ras.ras_shared_mc_addr,
 623                         &psp->ras.ras_shared_buf);
 624
 625         return ret;
 626 }
 627
 628 static int psp_ras_load(struct psp_context *psp)
 629 {
 630         int ret;
 631         struct psp_gfx_cmd_resp *cmd;
 632
 633         /*
 634          * TODO: bypass the loading in sriov for now
 635          */
 636         if (amdgpu_sriov_vf(psp->adev))
 637                 return 0;
 638
 639         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 640         if (!cmd)
 641                 return -ENOMEM;
 642
 643         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 644         memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
 645
 646         psp_prep_ras_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 647                         psp->ras.ras_shared_mc_addr,
 648                         psp->ta_ras_ucode_size, PSP_RAS_SHARED_MEM_SIZE);
 649
 650         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 651                         psp->fence_buf_mc_addr);
 652
 653         if (!ret) {
 654                 psp->ras.ras_initialized = 1;
 655                 psp->ras.session_id = cmd->resp.session_id;
 656         }
 657
 658         kfree(cmd);
 659
 660         return ret;
 661 }
 662
 663 static void psp_prep_ras_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 664                                                 uint32_t ras_session_id)
 665 {
 666         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 667         cmd->cmd.cmd_unload_ta.session_id = ras_session_id;
 668 }
 669
 670 static int psp_ras_unload(struct psp_context *psp)
 671 {
 672         int ret;
 673         struct psp_gfx_cmd_resp *cmd;
 674
 675         /*
 676          * TODO: bypass the unloading in sriov for now
 677          */
 678         if (amdgpu_sriov_vf(psp->adev))
 679                 return 0;
 680
 681         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 682         if (!cmd)
 683                 return -ENOMEM;
 684
 685         psp_prep_ras_ta_unload_cmd_buf(cmd, psp->ras.session_id);
 686
 687         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 688                         psp->fence_buf_mc_addr);
 689
 690         kfree(cmd);
 691
 692         return ret;
 693 }
 694
 695 static void psp_prep_ras_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 696                 uint32_t ta_cmd_id,
 697                 uint32_t ras_session_id)
 698 {
 699         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 700         cmd->cmd.cmd_invoke_cmd.session_id = ras_session_id;
 701         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 702         /* Note: cmd_invoke_cmd.buf is not used for now */
 703 }
 704
 705 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 706 {
 707         int ret;
 708         struct psp_gfx_cmd_resp *cmd;
 709
 710         /*
 711          * TODO: bypass the loading in sriov for now
 712          */
 713         if (amdgpu_sriov_vf(psp->adev))
 714                 return 0;
 715
 716         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 717         if (!cmd)
 718                 return -ENOMEM;
 719
 720         psp_prep_ras_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 721                         psp->ras.session_id);
 722
 723         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 724                         psp->fence_buf_mc_addr);
 725
 726         kfree(cmd);
 727
 728         return ret;
 729 }
 730
 731 int psp_ras_enable_features(struct psp_context *psp,
 732                 union ta_ras_cmd_input *info, bool enable)
 733 {
 734         struct ta_ras_shared_memory *ras_cmd;
 735         int ret;
 736
 737         if (!psp->ras.ras_initialized)
 738                 return -EINVAL;
 739
 740         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 741         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
 742
 743         if (enable)
 744                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
 745         else
 746                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
 747
 748         ras_cmd->ras_in_message = *info;
 749
 750         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
 751         if (ret)
 752                 return -EINVAL;
 753
 754         return ras_cmd->ras_status;
 755 }
 756
 757 static int psp_ras_terminate(struct psp_context *psp)
 758 {
 759         int ret;
 760
 761         /*
 762          * TODO: bypass the terminate in sriov for now
 763          */
 764         if (amdgpu_sriov_vf(psp->adev))
 765                 return 0;
 766
 767         if (!psp->ras.ras_initialized)
 768                 return 0;
 769
 770         ret = psp_ras_unload(psp);
 771         if (ret)
 772                 return ret;
 773
 774         psp->ras.ras_initialized = 0;
 775
 776         /* free ras shared memory */
 777         amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
 778                         &psp->ras.ras_shared_mc_addr,
 779                         &psp->ras.ras_shared_buf);
 780
 781         return 0;
 782 }
 783
 784 static int psp_ras_initialize(struct psp_context *psp)
 785 {
 786         int ret;
 787
 788         /*
 789          * TODO: bypass the initialize in sriov for now
 790          */
 791         if (amdgpu_sriov_vf(psp->adev))
 792                 return 0;
 793
 794         if (!psp->adev->psp.ta_ras_ucode_size ||
 795             !psp->adev->psp.ta_ras_start_addr) {
 796                 dev_warn(psp->adev->dev, "RAS: ras ta ucode is not available\n");
 797                 return 0;
 798         }
 799
 800         if (!psp->ras.ras_initialized) {
 801                 ret = psp_ras_init_shared_buf(psp);
 802                 if (ret)
 803                         return ret;
 804         }
 805
 806         ret = psp_ras_load(psp);
 807         if (ret)
 808                 return ret;
 809
 810         return 0;
 811 }
 812 // ras end
 813
 814 // HDCP start
 815 static void psp_prep_hdcp_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 816                                           uint64_t hdcp_ta_mc,
 817                                           uint64_t hdcp_mc_shared,
 818                                           uint32_t hdcp_ta_size,
 819                                           uint32_t shared_size)
 820 {
 821         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
 822         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(hdcp_ta_mc);
 823         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(hdcp_ta_mc);
 824         cmd->cmd.cmd_load_ta.app_len = hdcp_ta_size;
 825
 826         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
 827                 lower_32_bits(hdcp_mc_shared);
 828         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
 829                 upper_32_bits(hdcp_mc_shared);
 830         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 831 }
 832
 833 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
 834 {
 835         int ret;
 836
 837         /*
 838          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 839          * physical) for hdcp ta <-> Driver
 840          */
 841         ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
 842                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 843                                       &psp->hdcp_context.hdcp_shared_bo,
 844                                       &psp->hdcp_context.hdcp_shared_mc_addr,
 845                                       &psp->hdcp_context.hdcp_shared_buf);
 846
 847         return ret;
 848 }
 849
 850 static int psp_hdcp_load(struct psp_context *psp)
 851 {
 852         int ret;
 853         struct psp_gfx_cmd_resp *cmd;
 854
 855         /*
 856          * TODO: bypass the loading in sriov for now
 857          */
 858         if (amdgpu_sriov_vf(psp->adev))
 859                 return 0;
 860
 861         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 862         if (!cmd)
 863                 return -ENOMEM;
 864
 865         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 866         memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr,
 867                psp->ta_hdcp_ucode_size);
 868
 869         psp_prep_hdcp_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 870                                       psp->hdcp_context.hdcp_shared_mc_addr,
 871                                       psp->ta_hdcp_ucode_size,
 872                                       PSP_HDCP_SHARED_MEM_SIZE);
 873
 874         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 875
 876         if (!ret) {
 877                 psp->hdcp_context.hdcp_initialized = 1;
 878                 psp->hdcp_context.session_id = cmd->resp.session_id;
 879         }
 880
 881         kfree(cmd);
 882
 883         return ret;
 884 }
 885 static int psp_hdcp_initialize(struct psp_context *psp)
 886 {
 887         int ret;
 888
 889         /*
 890          * TODO: bypass the initialize in sriov for now
 891          */
 892         if (amdgpu_sriov_vf(psp->adev))
 893                 return 0;
 894
 895         if (!psp->adev->psp.ta_hdcp_ucode_size ||
 896             !psp->adev->psp.ta_hdcp_start_addr) {
 897                 dev_warn(psp->adev->dev, "HDCP: hdcp ta ucode is not available\n");
 898                 return 0;
 899         }
 900
 901         if (!psp->hdcp_context.hdcp_initialized) {
 902                 ret = psp_hdcp_init_shared_buf(psp);
 903                 if (ret)
 904                         return ret;
 905         }
 906
 907         ret = psp_hdcp_load(psp);
 908         if (ret)
 909                 return ret;
 910
 911         return 0;
 912 }
 913 static void psp_prep_hdcp_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 914                                             uint32_t hdcp_session_id)
 915 {
 916         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 917         cmd->cmd.cmd_unload_ta.session_id = hdcp_session_id;
 918 }
 919
 920 static int psp_hdcp_unload(struct psp_context *psp)
 921 {
 922         int ret;
 923         struct psp_gfx_cmd_resp *cmd;
 924
 925         /*
 926          * TODO: bypass the unloading in sriov for now
 927          */
 928         if (amdgpu_sriov_vf(psp->adev))
 929                 return 0;
 930
 931         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 932         if (!cmd)
 933                 return -ENOMEM;
 934
 935         psp_prep_hdcp_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);
 936
 937         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 938
 939         kfree(cmd);
 940
 941         return ret;
 942 }
 943
 944 static void psp_prep_hdcp_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 945                                             uint32_t ta_cmd_id,
 946                                             uint32_t hdcp_session_id)
 947 {
 948         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
 949         cmd->cmd.cmd_invoke_cmd.session_id = hdcp_session_id;
 950         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
 951         /* Note: cmd_invoke_cmd.buf is not used for now */
 952 }
 953
 954 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 955 {
 956         int ret;
 957         struct psp_gfx_cmd_resp *cmd;
 958
 959         /*
 960          * TODO: bypass the loading in sriov for now
 961          */
 962         if (amdgpu_sriov_vf(psp->adev))
 963                 return 0;
 964
 965         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 966         if (!cmd)
 967                 return -ENOMEM;
 968
 969         psp_prep_hdcp_ta_invoke_cmd_buf(cmd, ta_cmd_id,
 970                                         psp->hdcp_context.session_id);
 971
 972         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 973
 974         kfree(cmd);
 975
 976         return ret;
 977 }
 978
 979 static int psp_hdcp_terminate(struct psp_context *psp)
 980 {
 981         int ret;
 982
 983         /*
 984          * TODO: bypass the terminate in sriov for now
 985          */
 986         if (amdgpu_sriov_vf(psp->adev))
 987                 return 0;
 988
 989         if (!psp->hdcp_context.hdcp_initialized)
 990                 return 0;
 991
 992         ret = psp_hdcp_unload(psp);
 993         if (ret)
 994                 return ret;
 995
 996         psp->hdcp_context.hdcp_initialized = 0;
 997
 998         /* free hdcp shared memory */
 999         amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
1000                               &psp->hdcp_context.hdcp_shared_mc_addr,
1001                               &psp->hdcp_context.hdcp_shared_buf);
1002
1003         return 0;
1004 }
1005 // HDCP end
1006
1007 // DTM start
1008 static void psp_prep_dtm_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1009                                          uint64_t dtm_ta_mc,
1010                                          uint64_t dtm_mc_shared,
1011                                          uint32_t dtm_ta_size,
1012                                          uint32_t shared_size)
1013 {
1014         cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
1015         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(dtm_ta_mc);
1016         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(dtm_ta_mc);
1017         cmd->cmd.cmd_load_ta.app_len = dtm_ta_size;
1018
1019         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(dtm_mc_shared);
1020         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(dtm_mc_shared);
1021         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
1022 }
1023
1024 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1025 {
1026         int ret;
1027
1028         /*
1029          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1030          * physical) for dtm ta <-> Driver
1031          */
1032         ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
1033                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1034                                       &psp->dtm_context.dtm_shared_bo,
1035                                       &psp->dtm_context.dtm_shared_mc_addr,
1036                                       &psp->dtm_context.dtm_shared_buf);
1037
1038         return ret;
1039 }
1040
1041 static int psp_dtm_load(struct psp_context *psp)
1042 {
1043         int ret;
1044         struct psp_gfx_cmd_resp *cmd;
1045
1046         /*
1047          * TODO: bypass the loading in sriov for now
1048          */
1049         if (amdgpu_sriov_vf(psp->adev))
1050                 return 0;
1051
1052         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1053         if (!cmd)
1054                 return -ENOMEM;
1055
1056         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1057         memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
1058
1059         psp_prep_dtm_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
1060                                      psp->dtm_context.dtm_shared_mc_addr,
1061                                      psp->ta_dtm_ucode_size,
1062                                      PSP_DTM_SHARED_MEM_SIZE);
1063
1064         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1065
1066         if (!ret) {
1067                 psp->dtm_context.dtm_initialized = 1;
1068                 psp->dtm_context.session_id = cmd->resp.session_id;
1069         }
1070
1071         kfree(cmd);
1072
1073         return ret;
1074 }
1075
1076 static int psp_dtm_initialize(struct psp_context *psp)
1077 {
1078         int ret;
1079
1080         /*
1081          * TODO: bypass the initialize in sriov for now
1082          */
1083         if (amdgpu_sriov_vf(psp->adev))
1084                 return 0;
1085
1086         if (!psp->adev->psp.ta_dtm_ucode_size ||
1087             !psp->adev->psp.ta_dtm_start_addr) {
1088                 dev_warn(psp->adev->dev, "DTM: dtm ta ucode is not available\n");
1089                 return 0;
1090         }
1091
1092         if (!psp->dtm_context.dtm_initialized) {
1093                 ret = psp_dtm_init_shared_buf(psp);
1094                 if (ret)
1095                         return ret;
1096         }
1097
1098         ret = psp_dtm_load(psp);
1099         if (ret)
1100                 return ret;
1101
1102         return 0;
1103 }
1104
1105 static void psp_prep_dtm_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1106                                            uint32_t ta_cmd_id,
1107                                            uint32_t dtm_session_id)
1108 {
1109         cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1110         cmd->cmd.cmd_invoke_cmd.session_id = dtm_session_id;
1111         cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1112         /* Note: cmd_invoke_cmd.buf is not used for now */
1113 }
1114
1115 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1116 {
1117         int ret;
1118         struct psp_gfx_cmd_resp *cmd;
1119
1120         /*
1121          * TODO: bypass the loading in sriov for now
1122          */
1123         if (amdgpu_sriov_vf(psp->adev))
1124                 return 0;
1125
1126         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1127         if (!cmd)
1128                 return -ENOMEM;
1129
1130         psp_prep_dtm_ta_invoke_cmd_buf(cmd, ta_cmd_id,
1131                                        psp->dtm_context.session_id);
1132
1133         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1134
1135         kfree(cmd);
1136
1137         return ret;
1138 }
1139
1140 static int psp_dtm_terminate(struct psp_context *psp)
1141 {
1142         int ret;
1143
1144         /*
1145          * TODO: bypass the terminate in sriov for now
1146          */
1147         if (amdgpu_sriov_vf(psp->adev))
1148                 return 0;
1149
1150         if (!psp->dtm_context.dtm_initialized)
1151                 return 0;
1152
1153         ret = psp_hdcp_unload(psp);
1154         if (ret)
1155                 return ret;
1156
1157         psp->dtm_context.dtm_initialized = 0;
1158
1159         /* free hdcp shared memory */
1160         amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
1161                               &psp->dtm_context.dtm_shared_mc_addr,
1162                               &psp->dtm_context.dtm_shared_buf);
1163
1164         return 0;
1165 }
1166 // DTM end
1167
1168 static int psp_hw_start(struct psp_context *psp)
1169 {
1170         struct amdgpu_device *adev = psp->adev;
1171         int ret;
1172
1173         if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
1174                 if (psp->kdb_bin_size &&
1175                     (psp->funcs->bootloader_load_kdb != NULL)) {
1176                         ret = psp_bootloader_load_kdb(psp);
1177                         if (ret) {
1178                                 DRM_ERROR("PSP load kdb failed!\n");
1179                                 return ret;
1180                         }
1181                 }
1182
1183                 ret = psp_bootloader_load_sysdrv(psp);
1184                 if (ret) {
1185                         DRM_ERROR("PSP load sysdrv failed!\n");
1186                         return ret;
1187                 }
1188
1189                 ret = psp_bootloader_load_sos(psp);
1190                 if (ret) {
1191                         DRM_ERROR("PSP load sos failed!\n");
1192                         return ret;
1193                 }
1194         }
1195
1196         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
1197         if (ret) {
1198                 DRM_ERROR("PSP create ring failed!\n");
1199                 return ret;
1200         }
1201
1202         ret = psp_tmr_init(psp);
1203         if (ret) {
1204                 DRM_ERROR("PSP tmr init failed!\n");
1205                 return ret;
1206         }
1207
1208         ret = psp_tmr_load(psp);
1209         if (ret) {
1210                 DRM_ERROR("PSP load tmr failed!\n");
1211                 return ret;
1212         }
1213
1214         ret = psp_asd_init(psp);
1215         if (ret) {
1216                 DRM_ERROR("PSP asd init failed!\n");
1217                 return ret;
1218         }
1219
1220         ret = psp_asd_load(psp);
1221         if (ret) {
1222                 DRM_ERROR("PSP load asd failed!\n");
1223                 return ret;
1224         }
1225
1226         if (adev->gmc.xgmi.num_physical_nodes > 1) {
1227                 ret = psp_xgmi_initialize(psp);
1228                 /* Warning the XGMI seesion initialize failure
1229                  * Instead of stop driver initialization
1230                  */
1231                 if (ret)
1232                         dev_err(psp->adev->dev,
1233                                 "XGMI: Failed to initialize XGMI session\n");
1234         }
1235
1236         if (psp->adev->psp.ta_fw) {
1237                 ret = psp_ras_initialize(psp);
1238                 if (ret)
1239                         dev_err(psp->adev->dev,
1240                                         "RAS: Failed to initialize RAS\n");
1241
1242                 ret = psp_hdcp_initialize(psp);
1243                 if (ret)
1244                         dev_err(psp->adev->dev,
1245                                 "HDCP: Failed to initialize HDCP\n");
1246
1247                 ret = psp_dtm_initialize(psp);
1248                 if (ret)
1249                         dev_err(psp->adev->dev,
1250                                 "DTM: Failed to initialize DTM\n");
1251         }
1252
1253         return 0;
1254 }
1255
1256 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
1257                            enum psp_gfx_fw_type *type)
1258 {
1259         switch (ucode->ucode_id) {
1260         case AMDGPU_UCODE_ID_SDMA0:
1261                 *type = GFX_FW_TYPE_SDMA0;
1262                 break;
1263         case AMDGPU_UCODE_ID_SDMA1:
1264                 *type = GFX_FW_TYPE_SDMA1;
1265                 break;
1266         case AMDGPU_UCODE_ID_SDMA2:
1267                 *type = GFX_FW_TYPE_SDMA2;
1268                 break;
1269         case AMDGPU_UCODE_ID_SDMA3:
1270                 *type = GFX_FW_TYPE_SDMA3;
1271                 break;
1272         case AMDGPU_UCODE_ID_SDMA4:
1273                 *type = GFX_FW_TYPE_SDMA4;
1274                 break;
1275         case AMDGPU_UCODE_ID_SDMA5:
1276                 *type = GFX_FW_TYPE_SDMA5;
1277                 break;
1278         case AMDGPU_UCODE_ID_SDMA6:
1279                 *type = GFX_FW_TYPE_SDMA6;
1280                 break;
1281         case AMDGPU_UCODE_ID_SDMA7:
1282                 *type = GFX_FW_TYPE_SDMA7;
1283                 break;
1284         case AMDGPU_UCODE_ID_CP_CE:
1285                 *type = GFX_FW_TYPE_CP_CE;
1286                 break;
1287         case AMDGPU_UCODE_ID_CP_PFP:
1288                 *type = GFX_FW_TYPE_CP_PFP;
1289                 break;
1290         case AMDGPU_UCODE_ID_CP_ME:
1291                 *type = GFX_FW_TYPE_CP_ME;
1292                 break;
1293         case AMDGPU_UCODE_ID_CP_MEC1:
1294                 *type = GFX_FW_TYPE_CP_MEC;
1295                 break;
1296         case AMDGPU_UCODE_ID_CP_MEC1_JT:
1297                 *type = GFX_FW_TYPE_CP_MEC_ME1;
1298                 break;
1299         case AMDGPU_UCODE_ID_CP_MEC2:
1300                 *type = GFX_FW_TYPE_CP_MEC;
1301                 break;
1302         case AMDGPU_UCODE_ID_CP_MEC2_JT:
1303                 *type = GFX_FW_TYPE_CP_MEC_ME2;
1304                 break;
1305         case AMDGPU_UCODE_ID_RLC_G:
1306                 *type = GFX_FW_TYPE_RLC_G;
1307                 break;
1308         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
1309                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
1310                 break;
1311         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
1312                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
1313                 break;
1314         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
1315                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
1316                 break;
1317         case AMDGPU_UCODE_ID_SMC:
1318                 *type = GFX_FW_TYPE_SMU;
1319                 break;
1320         case AMDGPU_UCODE_ID_UVD:
1321                 *type = GFX_FW_TYPE_UVD;
1322                 break;
1323         case AMDGPU_UCODE_ID_UVD1:
1324                 *type = GFX_FW_TYPE_UVD1;
1325                 break;
1326         case AMDGPU_UCODE_ID_VCE:
1327                 *type = GFX_FW_TYPE_VCE;
1328                 break;
1329         case AMDGPU_UCODE_ID_VCN:
1330                 *type = GFX_FW_TYPE_VCN;
1331                 break;
1332         case AMDGPU_UCODE_ID_DMCU_ERAM:
1333                 *type = GFX_FW_TYPE_DMCU_ERAM;
1334                 break;
1335         case AMDGPU_UCODE_ID_DMCU_INTV:
1336                 *type = GFX_FW_TYPE_DMCU_ISR;
1337                 break;
1338         case AMDGPU_UCODE_ID_VCN0_RAM:
1339                 *type = GFX_FW_TYPE_VCN0_RAM;
1340                 break;
1341         case AMDGPU_UCODE_ID_VCN1_RAM:
1342                 *type = GFX_FW_TYPE_VCN1_RAM;
1343                 break;
1344         case AMDGPU_UCODE_ID_MAXIMUM:
1345         default:
1346                 return -EINVAL;
1347         }
1348
1349         return 0;
1350 }
1351
1352 static void psp_print_fw_hdr(struct psp_context *psp,
1353                              struct amdgpu_firmware_info *ucode)
1354 {
1355         struct amdgpu_device *adev = psp->adev;
1356         struct common_firmware_header *hdr;
1357
1358         switch (ucode->ucode_id) {
1359         case AMDGPU_UCODE_ID_SDMA0:
1360         case AMDGPU_UCODE_ID_SDMA1:
1361         case AMDGPU_UCODE_ID_SDMA2:
1362         case AMDGPU_UCODE_ID_SDMA3:
1363         case AMDGPU_UCODE_ID_SDMA4:
1364         case AMDGPU_UCODE_ID_SDMA5:
1365         case AMDGPU_UCODE_ID_SDMA6:
1366         case AMDGPU_UCODE_ID_SDMA7:
1367                 hdr = (struct common_firmware_header *)
1368                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
1369                 amdgpu_ucode_print_sdma_hdr(hdr);
1370                 break;
1371         case AMDGPU_UCODE_ID_CP_CE:
1372                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
1373                 amdgpu_ucode_print_gfx_hdr(hdr);
1374                 break;
1375         case AMDGPU_UCODE_ID_CP_PFP:
1376                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
1377                 amdgpu_ucode_print_gfx_hdr(hdr);
1378                 break;
1379         case AMDGPU_UCODE_ID_CP_ME:
1380                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
1381                 amdgpu_ucode_print_gfx_hdr(hdr);
1382                 break;
1383         case AMDGPU_UCODE_ID_CP_MEC1:
1384                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
1385                 amdgpu_ucode_print_gfx_hdr(hdr);
1386                 break;
1387         case AMDGPU_UCODE_ID_RLC_G:
1388                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
1389                 amdgpu_ucode_print_rlc_hdr(hdr);
1390                 break;
1391         case AMDGPU_UCODE_ID_SMC:
1392                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
1393                 amdgpu_ucode_print_smc_hdr(hdr);
1394                 break;
1395         default:
1396                 break;
1397         }
1398 }
1399
1400 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
1401                                        struct psp_gfx_cmd_resp *cmd)
1402 {
1403         int ret;
1404         uint64_t fw_mem_mc_addr = ucode->mc_addr;
1405
1406         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
1407
1408         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
1409         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
1410         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
1411         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
1412
1413         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
1414         if (ret)
1415                 DRM_ERROR("Unknown firmware type\n");
1416
1417         return ret;
1418 }
1419
1420 static int psp_execute_np_fw_load(struct psp_context *psp,
1421                                struct amdgpu_firmware_info *ucode)
1422 {
1423         int ret = 0;
1424
1425         ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
1426         if (ret)
1427                 return ret;
1428
1429         ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
1430                                  psp->fence_buf_mc_addr);
1431
1432         return ret;
1433 }
1434
1435 static int psp_np_fw_load(struct psp_context *psp)
1436 {
1437         int i, ret;
1438         struct amdgpu_firmware_info *ucode;
1439         struct amdgpu_device* adev = psp->adev;
1440
1441         if (psp->autoload_supported) {
1442                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
1443                 if (!ucode->fw)
1444                         goto out;
1445
1446                 ret = psp_execute_np_fw_load(psp, ucode);
1447                 if (ret)
1448                         return ret;
1449         }
1450
1451 out:
1452         for (i = 0; i < adev->firmware.max_ucodes; i++) {
1453                 ucode = &adev->firmware.ucode[i];
1454                 if (!ucode->fw)
1455                         continue;
1456
1457                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
1458                     (psp_smu_reload_quirk(psp) || psp->autoload_supported))
1459                         continue;
1460
1461                 if (amdgpu_sriov_vf(adev) &&
1462                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
1463                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
1464                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
1465                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
1466                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
1467                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
1468                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
1469                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
1470                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
1471                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
1472                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
1473                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM))
1474                         /*skip ucode loading in SRIOV VF */
1475                         continue;
1476
1477                 if (psp->autoload_supported &&
1478                     (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
1479                      ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
1480                         /* skip mec JT when autoload is enabled */
1481                         continue;
1482
1483                 psp_print_fw_hdr(psp, ucode);
1484
1485                 ret = psp_execute_np_fw_load(psp, ucode);
1486                 if (ret)
1487                         return ret;
1488
1489                 /* Start rlc autoload after psp recieved all the gfx firmware */
1490                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
1491                     AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
1492                         ret = psp_rlc_autoload(psp);
1493                         if (ret) {
1494                                 DRM_ERROR("Failed to start rlc autoload\n");
1495                                 return ret;
1496                         }
1497                 }
1498 #if 0
1499                 /* check if firmware loaded sucessfully */
1500                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
1501                         return -EINVAL;
1502 #endif
1503         }
1504
1505         return 0;
1506 }
1507
1508 static int psp_load_fw(struct amdgpu_device *adev)
1509 {
1510         int ret;
1511         struct psp_context *psp = &adev->psp;
1512
1513         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
1514                 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
1515                 goto skip_memalloc;
1516         }
1517
1518         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1519         if (!psp->cmd)
1520                 return -ENOMEM;
1521
1522         /* this fw pri bo is not used under SRIOV */
1523         if (!amdgpu_sriov_vf(psp->adev)) {
1524                 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
1525                                               AMDGPU_GEM_DOMAIN_GTT,
1526                                               &psp->fw_pri_bo,
1527                                               &psp->fw_pri_mc_addr,
1528                                               &psp->fw_pri_buf);
1529                 if (ret)
1530                         goto failed;
1531         }
1532
1533         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
1534                                         AMDGPU_GEM_DOMAIN_VRAM,
1535                                         &psp->fence_buf_bo,
1536                                         &psp->fence_buf_mc_addr,
1537                                         &psp->fence_buf);
1538         if (ret)
1539                 goto failed;
1540
1541         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
1542                                       AMDGPU_GEM_DOMAIN_VRAM,
1543                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1544                                       (void **)&psp->cmd_buf_mem);
1545         if (ret)
1546                 goto failed;
1547
1548         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
1549
1550         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
1551         if (ret) {
1552                 DRM_ERROR("PSP ring init failed!\n");
1553                 goto failed;
1554         }
1555
1556 skip_memalloc:
1557         ret = psp_hw_start(psp);
1558         if (ret)
1559                 goto failed;
1560
1561         ret = psp_np_fw_load(psp);
1562         if (ret)
1563                 goto failed;
1564
1565         return 0;
1566
1567 failed:
1568         /*
1569          * all cleanup jobs (xgmi terminate, ras terminate,
1570          * ring destroy, cmd/fence/fw buffers destory,
1571          * psp->cmd destory) are delayed to psp_hw_fini
1572          */
1573         return ret;
1574 }
1575
1576 static int psp_hw_init(void *handle)
1577 {
1578         int ret;
1579         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1580
1581         mutex_lock(&adev->firmware.mutex);
1582         /*
1583          * This sequence is just used on hw_init only once, no need on
1584          * resume.
1585          */
1586         ret = amdgpu_ucode_init_bo(adev);
1587         if (ret)
1588                 goto failed;
1589
1590         ret = psp_load_fw(adev);
1591         if (ret) {
1592                 DRM_ERROR("PSP firmware loading failed\n");
1593                 goto failed;
1594         }
1595
1596         mutex_unlock(&adev->firmware.mutex);
1597         return 0;
1598
1599 failed:
1600         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
1601         mutex_unlock(&adev->firmware.mutex);
1602         return -EINVAL;
1603 }
1604
1605 static int psp_hw_fini(void *handle)
1606 {
1607         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1608         struct psp_context *psp = &adev->psp;
1609         void *tmr_buf;
1610         void **pptr;
1611
1612         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1613             psp->xgmi_context.initialized == 1)
1614                 psp_xgmi_terminate(psp);
1615
1616         if (psp->adev->psp.ta_fw) {
1617                 psp_ras_terminate(psp);
1618                 psp_dtm_terminate(psp);
1619                 psp_hdcp_terminate(psp);
1620         }
1621
1622         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
1623
1624         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
1625         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
1626         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
1627                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
1628         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
1629                               &psp->fence_buf_mc_addr, &psp->fence_buf);
1630         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
1631                               &psp->asd_shared_buf);
1632         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1633                               (void **)&psp->cmd_buf_mem);
1634
1635         kfree(psp->cmd);
1636         psp->cmd = NULL;
1637
1638         return 0;
1639 }
1640
1641 static int psp_suspend(void *handle)
1642 {
1643         int ret;
1644         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1645         struct psp_context *psp = &adev->psp;
1646
1647         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1648             psp->xgmi_context.initialized == 1) {
1649                 ret = psp_xgmi_terminate(psp);
1650                 if (ret) {
1651                         DRM_ERROR("Failed to terminate xgmi ta\n");
1652                         return ret;
1653                 }
1654         }
1655
1656         if (psp->adev->psp.ta_fw) {
1657                 ret = psp_ras_terminate(psp);
1658                 if (ret) {
1659                         DRM_ERROR("Failed to terminate ras ta\n");
1660                         return ret;
1661                 }
1662                 ret = psp_hdcp_terminate(psp);
1663                 if (ret) {
1664                         DRM_ERROR("Failed to terminate hdcp ta\n");
1665                         return ret;
1666                 }
1667                 ret = psp_dtm_terminate(psp);
1668                 if (ret) {
1669                         DRM_ERROR("Failed to terminate dtm ta\n");
1670                         return ret;
1671                 }
1672         }
1673
1674         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
1675         if (ret) {
1676                 DRM_ERROR("PSP ring stop failed\n");
1677                 return ret;
1678         }
1679
1680         return 0;
1681 }
1682
1683 static int psp_resume(void *handle)
1684 {
1685         int ret;
1686         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1687         struct psp_context *psp = &adev->psp;
1688
1689         DRM_INFO("PSP is resuming...\n");
1690
1691         ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
1692         if (ret) {
1693                 DRM_ERROR("Failed to process memory training!\n");
1694                 return ret;
1695         }
1696
1697         mutex_lock(&adev->firmware.mutex);
1698
1699         ret = psp_hw_start(psp);
1700         if (ret)
1701                 goto failed;
1702
1703         ret = psp_np_fw_load(psp);
1704         if (ret)
1705                 goto failed;
1706
1707         mutex_unlock(&adev->firmware.mutex);
1708
1709         return 0;
1710
1711 failed:
1712         DRM_ERROR("PSP resume failed\n");
1713         mutex_unlock(&adev->firmware.mutex);
1714         return ret;
1715 }
1716
1717 int psp_gpu_reset(struct amdgpu_device *adev)
1718 {
1719         int ret;
1720
1721         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1722                 return 0;
1723
1724         mutex_lock(&adev->psp.mutex);
1725         ret = psp_mode1_reset(&adev->psp);
1726         mutex_unlock(&adev->psp.mutex);
1727
1728         return ret;
1729 }
1730
1731 int psp_rlc_autoload_start(struct psp_context *psp)
1732 {
1733         int ret;
1734         struct psp_gfx_cmd_resp *cmd;
1735
1736         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1737         if (!cmd)
1738                 return -ENOMEM;
1739
1740         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
1741
1742         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1743                                  psp->fence_buf_mc_addr);
1744         kfree(cmd);
1745         return ret;
1746 }
1747
1748 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
1749                         uint64_t cmd_gpu_addr, int cmd_size)
1750 {
1751         struct amdgpu_firmware_info ucode = {0};
1752
1753         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
1754                 AMDGPU_UCODE_ID_VCN0_RAM;
1755         ucode.mc_addr = cmd_gpu_addr;
1756         ucode.ucode_size = cmd_size;
1757
1758         return psp_execute_np_fw_load(&adev->psp, &ucode);
1759 }
1760
1761 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
1762                                         enum AMDGPU_UCODE_ID ucode_type)
1763 {
1764         struct amdgpu_firmware_info *ucode = NULL;
1765
1766         if (!adev->firmware.fw_size)
1767                 return false;
1768
1769         ucode = &adev->firmware.ucode[ucode_type];
1770         if (!ucode->fw || !ucode->ucode_size)
1771                 return false;
1772
1773         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
1774 }
1775
1776 static int psp_set_clockgating_state(void *handle,
1777                                      enum amd_clockgating_state state)
1778 {
1779         return 0;
1780 }
1781
1782 static int psp_set_powergating_state(void *handle,
1783                                      enum amd_powergating_state state)
1784 {
1785         return 0;
1786 }
1787
1788 const struct amd_ip_funcs psp_ip_funcs = {
1789         .name = "psp",
1790         .early_init = psp_early_init,
1791         .late_init = NULL,
1792         .sw_init = psp_sw_init,
1793         .sw_fini = psp_sw_fini,
1794         .hw_init = psp_hw_init,
1795         .hw_fini = psp_hw_fini,
1796         .suspend = psp_suspend,
1797         .resume = psp_resume,
1798         .is_idle = NULL,
1799         .check_soft_reset = NULL,
1800         .wait_for_idle = NULL,
1801         .soft_reset = NULL,
1802         .set_clockgating_state = psp_set_clockgating_state,
1803         .set_powergating_state = psp_set_powergating_state,
1804 };
1805
1806 static const struct amdgpu_psp_funcs psp_funcs = {
1807         .check_fw_loading_status = psp_check_fw_loading_status,
1808 };
1809
1810 static void psp_set_funcs(struct amdgpu_device *adev)
1811 {
1812         if (NULL == adev->firmware.funcs)
1813                 adev->firmware.funcs = &psp_funcs;
1814 }
1815
1816 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
1817 {
1818         .type = AMD_IP_BLOCK_TYPE_PSP,
1819         .major = 3,
1820         .minor = 1,
1821         .rev = 0,
1822         .funcs = &psp_ip_funcs,
1823 };
1824
1825 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
1826 {
1827         .type = AMD_IP_BLOCK_TYPE_PSP,
1828         .major = 10,
1829         .minor = 0,
1830         .rev = 0,
1831         .funcs = &psp_ip_funcs,
1832 };
1833
1834 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
1835 {
1836         .type = AMD_IP_BLOCK_TYPE_PSP,
1837         .major = 11,
1838         .minor = 0,
1839         .rev = 0,
1840         .funcs = &psp_ip_funcs,
1841 };
1842
1843 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
1844 {
1845         .type = AMD_IP_BLOCK_TYPE_PSP,
1846         .major = 12,
1847         .minor = 0,
1848         .rev = 0,
1849         .funcs = &psp_ip_funcs,
1850 };