drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drm_drv.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_xgmi.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v11_0_8.h"
  38 #include "psp_v12_0.h"
  39 #include "psp_v13_0.h"
  40 #include "psp_v13_0_4.h"
  41
  42 #include "amdgpu_ras.h"
  43 #include "amdgpu_securedisplay.h"
  44 #include "amdgpu_atomfirmware.h"
  45
  46 #define AMD_VBIOS_FILE_MAX_SIZE_B      (1024*1024*3)
  47
  48 static int psp_load_smu_fw(struct psp_context *psp);
  49 static int psp_rap_terminate(struct psp_context *psp);
  50 static int psp_securedisplay_terminate(struct psp_context *psp);
  51
  52 static int psp_ring_init(struct psp_context *psp,
  53                          enum psp_ring_type ring_type)
  54 {
  55         int ret = 0;
  56         struct psp_ring *ring;
  57         struct amdgpu_device *adev = psp->adev;
  58
  59         ring = &psp->km_ring;
  60
  61         ring->ring_type = ring_type;
  62
  63         /* allocate 4k Page of Local Frame Buffer memory for ring */
  64         ring->ring_size = 0x1000;
  65         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
  66                                       AMDGPU_GEM_DOMAIN_VRAM |
  67                                       AMDGPU_GEM_DOMAIN_GTT,
  68                                       &adev->firmware.rbuf,
  69                                       &ring->ring_mem_mc_addr,
  70                                       (void **)&ring->ring_mem);
  71         if (ret) {
  72                 ring->ring_size = 0;
  73                 return ret;
  74         }
  75
  76         return 0;
  77 }
  78
  79 /*
  80  * Due to DF Cstate management centralized to PMFW, the firmware
  81  * loading sequence will be updated as below:
  82  *   - Load KDB
  83  *   - Load SYS_DRV
  84  *   - Load tOS
  85  *   - Load PMFW
  86  *   - Setup TMR
  87  *   - Load other non-psp fw
  88  *   - Load ASD
  89  *   - Load XGMI/RAS/HDCP/DTM TA if any
  90  *
  91  * This new sequence is required for
  92  *   - Arcturus and onwards
  93  */
  94 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  95 {
  96         struct amdgpu_device *adev = psp->adev;
  97
  98         if (amdgpu_sriov_vf(adev)) {
  99                 psp->pmfw_centralized_cstate_management = false;
 100                 return;
 101         }
 102
 103         switch (adev->ip_versions[MP0_HWIP][0]) {
 104         case IP_VERSION(11, 0, 0):
 105         case IP_VERSION(11, 0, 4):
 106         case IP_VERSION(11, 0, 5):
 107         case IP_VERSION(11, 0, 7):
 108         case IP_VERSION(11, 0, 9):
 109         case IP_VERSION(11, 0, 11):
 110         case IP_VERSION(11, 0, 12):
 111         case IP_VERSION(11, 0, 13):
 112         case IP_VERSION(13, 0, 0):
 113         case IP_VERSION(13, 0, 2):
 114         case IP_VERSION(13, 0, 7):
 115                 psp->pmfw_centralized_cstate_management = true;
 116                 break;
 117         default:
 118                 psp->pmfw_centralized_cstate_management = false;
 119                 break;
 120         }
 121 }
 122
 123 static int psp_init_sriov_microcode(struct psp_context *psp)
 124 {
 125         struct amdgpu_device *adev = psp->adev;
 126         char ucode_prefix[30];
 127         int ret = 0;
 128
 129         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 130
 131         switch (adev->ip_versions[MP0_HWIP][0]) {
 132         case IP_VERSION(9, 0, 0):
 133         case IP_VERSION(11, 0, 7):
 134         case IP_VERSION(11, 0, 9):
 135                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 136                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 137                 break;
 138         case IP_VERSION(13, 0, 2):
 139                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 140                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 141                 ret &= psp_init_ta_microcode(psp, ucode_prefix);
 142                 break;
 143         case IP_VERSION(13, 0, 0):
 144                 adev->virt.autoload_ucode_id = 0;
 145                 break;
 146         case IP_VERSION(13, 0, 6):
 147                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 148                 break;
 149         case IP_VERSION(13, 0, 10):
 150                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
 151                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 152                 break;
 153         default:
 154                 return -EINVAL;
 155         }
 156         return ret;
 157 }
 158
 159 static int psp_early_init(void *handle)
 160 {
 161         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 162         struct psp_context *psp = &adev->psp;
 163
 164         switch (adev->ip_versions[MP0_HWIP][0]) {
 165         case IP_VERSION(9, 0, 0):
 166                 psp_v3_1_set_psp_funcs(psp);
 167                 psp->autoload_supported = false;
 168                 break;
 169         case IP_VERSION(10, 0, 0):
 170         case IP_VERSION(10, 0, 1):
 171                 psp_v10_0_set_psp_funcs(psp);
 172                 psp->autoload_supported = false;
 173                 break;
 174         case IP_VERSION(11, 0, 2):
 175         case IP_VERSION(11, 0, 4):
 176                 psp_v11_0_set_psp_funcs(psp);
 177                 psp->autoload_supported = false;
 178                 break;
 179         case IP_VERSION(11, 0, 0):
 180         case IP_VERSION(11, 0, 7):
 181                 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev);
 182                 fallthrough;
 183         case IP_VERSION(11, 0, 5):
 184         case IP_VERSION(11, 0, 9):
 185         case IP_VERSION(11, 0, 11):
 186         case IP_VERSION(11, 5, 0):
 187         case IP_VERSION(11, 0, 12):
 188         case IP_VERSION(11, 0, 13):
 189                 psp_v11_0_set_psp_funcs(psp);
 190                 psp->autoload_supported = true;
 191                 break;
 192         case IP_VERSION(11, 0, 3):
 193         case IP_VERSION(12, 0, 1):
 194                 psp_v12_0_set_psp_funcs(psp);
 195                 break;
 196         case IP_VERSION(13, 0, 2):
 197         case IP_VERSION(13, 0, 6):
 198                 psp_v13_0_set_psp_funcs(psp);
 199                 break;
 200         case IP_VERSION(13, 0, 1):
 201         case IP_VERSION(13, 0, 3):
 202         case IP_VERSION(13, 0, 5):
 203         case IP_VERSION(13, 0, 8):
 204         case IP_VERSION(13, 0, 11):
 205         case IP_VERSION(14, 0, 0):
 206                 psp_v13_0_set_psp_funcs(psp);
 207                 psp->autoload_supported = true;
 208                 break;
 209         case IP_VERSION(11, 0, 8):
 210                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 211                         psp_v11_0_8_set_psp_funcs(psp);
 212                         psp->autoload_supported = false;
 213                 }
 214                 break;
 215         case IP_VERSION(13, 0, 0):
 216         case IP_VERSION(13, 0, 7):
 217         case IP_VERSION(13, 0, 10):
 218                 psp_v13_0_set_psp_funcs(psp);
 219                 psp->autoload_supported = true;
 220                 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev);
 221                 break;
 222         case IP_VERSION(13, 0, 4):
 223                 psp_v13_0_4_set_psp_funcs(psp);
 224                 psp->autoload_supported = true;
 225                 break;
 226         default:
 227                 return -EINVAL;
 228         }
 229
 230         psp->adev = adev;
 231
 232         psp_check_pmfw_centralized_cstate_management(psp);
 233
 234         if (amdgpu_sriov_vf(adev))
 235                 return psp_init_sriov_microcode(psp);
 236         else
 237                 return psp_init_microcode(psp);
 238 }
 239
 240 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
 241 {
 242         amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
 243                               &mem_ctx->shared_buf);
 244         mem_ctx->shared_bo = NULL;
 245 }
 246
 247 static void psp_free_shared_bufs(struct psp_context *psp)
 248 {
 249         void *tmr_buf;
 250         void **pptr;
 251
 252         /* free TMR memory buffer */
 253         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 254         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 255         psp->tmr_bo = NULL;
 256
 257         /* free xgmi shared memory */
 258         psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
 259
 260         /* free ras shared memory */
 261         psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
 262
 263         /* free hdcp shared memory */
 264         psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
 265
 266         /* free dtm shared memory */
 267         psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
 268
 269         /* free rap shared memory */
 270         psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
 271
 272         /* free securedisplay shared memory */
 273         psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
 274
 275
 276 }
 277
 278 static void psp_memory_training_fini(struct psp_context *psp)
 279 {
 280         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 281
 282         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 283         kfree(ctx->sys_cache);
 284         ctx->sys_cache = NULL;
 285 }
 286
 287 static int psp_memory_training_init(struct psp_context *psp)
 288 {
 289         int ret;
 290         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 291
 292         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 293                 DRM_DEBUG("memory training is not supported!\n");
 294                 return 0;
 295         }
 296
 297         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 298         if (ctx->sys_cache == NULL) {
 299                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 300                 ret = -ENOMEM;
 301                 goto Err_out;
 302         }
 303
 304         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 305                   ctx->train_data_size,
 306                   ctx->p2c_train_data_offset,
 307                   ctx->c2p_train_data_offset);
 308         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 309         return 0;
 310
 311 Err_out:
 312         psp_memory_training_fini(psp);
 313         return ret;
 314 }
 315
 316 /*
 317  * Helper funciton to query psp runtime database entry
 318  *
 319  * @adev: amdgpu_device pointer
 320  * @entry_type: the type of psp runtime database entry
 321  * @db_entry: runtime database entry pointer
 322  *
 323  * Return false if runtime database doesn't exit or entry is invalid
 324  * or true if the specific database entry is found, and copy to @db_entry
 325  */
 326 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
 327                                      enum psp_runtime_entry_type entry_type,
 328                                      void *db_entry)
 329 {
 330         uint64_t db_header_pos, db_dir_pos;
 331         struct psp_runtime_data_header db_header = {0};
 332         struct psp_runtime_data_directory db_dir = {0};
 333         bool ret = false;
 334         int i;
 335
 336         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6))
 337                 return false;
 338
 339         db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
 340         db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
 341
 342         /* read runtime db header from vram */
 343         amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
 344                         sizeof(struct psp_runtime_data_header), false);
 345
 346         if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
 347                 /* runtime db doesn't exist, exit */
 348                 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
 349                 return false;
 350         }
 351
 352         /* read runtime database entry from vram */
 353         amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
 354                         sizeof(struct psp_runtime_data_directory), false);
 355
 356         if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
 357                 /* invalid db entry count, exit */
 358                 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
 359                 return false;
 360         }
 361
 362         /* look up for requested entry type */
 363         for (i = 0; i < db_dir.entry_count && !ret; i++) {
 364                 if (db_dir.entry_list[i].entry_type == entry_type) {
 365                         switch (entry_type) {
 366                         case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
 367                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
 368                                         /* invalid db entry size */
 369                                         dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
 370                                         return false;
 371                                 }
 372                                 /* read runtime database entry */
 373                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 374                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
 375                                 ret = true;
 376                                 break;
 377                         case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
 378                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
 379                                         /* invalid db entry size */
 380                                         dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
 381                                         return false;
 382                                 }
 383                                 /* read runtime database entry */
 384                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 385                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
 386                                 ret = true;
 387                                 break;
 388                         default:
 389                                 ret = false;
 390                                 break;
 391                         }
 392                 }
 393         }
 394
 395         return ret;
 396 }
 397
 398 static int psp_sw_init(void *handle)
 399 {
 400         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 401         struct psp_context *psp = &adev->psp;
 402         int ret;
 403         struct psp_runtime_boot_cfg_entry boot_cfg_entry;
 404         struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 405         struct psp_runtime_scpm_entry scpm_entry;
 406
 407         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 408         if (!psp->cmd) {
 409                 DRM_ERROR("Failed to allocate memory to command buffer!\n");
 410                 ret = -ENOMEM;
 411         }
 412
 413         adev->psp.xgmi_context.supports_extended_data =
 414                 !adev->gmc.xgmi.connected_to_cpu &&
 415                         adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
 416
 417         memset(&scpm_entry, 0, sizeof(scpm_entry));
 418         if ((psp_get_runtime_db_entry(adev,
 419                                 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
 420                                 &scpm_entry)) &&
 421             (scpm_entry.scpm_status != SCPM_DISABLE)) {
 422                 adev->scpm_enabled = true;
 423                 adev->scpm_status = scpm_entry.scpm_status;
 424         } else {
 425                 adev->scpm_enabled = false;
 426                 adev->scpm_status = SCPM_DISABLE;
 427         }
 428
 429         /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
 430
 431         memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
 432         if (psp_get_runtime_db_entry(adev,
 433                                 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
 434                                 &boot_cfg_entry)) {
 435                 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
 436                 if ((psp->boot_cfg_bitmask) &
 437                     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
 438                         /* If psp runtime database exists, then
 439                          * only enable two stage memory training
 440                          * when TWO_STAGE_DRAM_TRAINING bit is set
 441                          * in runtime database */
 442                         mem_training_ctx->enable_mem_training = true;
 443                 }
 444
 445         } else {
 446                 /* If psp runtime database doesn't exist or
 447                  * is invalid, force enable two stage memory
 448                  * training */
 449                 mem_training_ctx->enable_mem_training = true;
 450         }
 451
 452         if (mem_training_ctx->enable_mem_training) {
 453                 ret = psp_memory_training_init(psp);
 454                 if (ret) {
 455                         DRM_ERROR("Failed to initialize memory training!\n");
 456                         return ret;
 457                 }
 458
 459                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 460                 if (ret) {
 461                         DRM_ERROR("Failed to process memory training!\n");
 462                         return ret;
 463                 }
 464         }
 465
 466         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 467                                       amdgpu_sriov_vf(adev) ?
 468                                       AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 469                                       &psp->fw_pri_bo,
 470                                       &psp->fw_pri_mc_addr,
 471                                       &psp->fw_pri_buf);
 472         if (ret)
 473                 return ret;
 474
 475         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 476                                       AMDGPU_GEM_DOMAIN_VRAM |
 477                                       AMDGPU_GEM_DOMAIN_GTT,
 478                                       &psp->fence_buf_bo,
 479                                       &psp->fence_buf_mc_addr,
 480                                       &psp->fence_buf);
 481         if (ret)
 482                 goto failed1;
 483
 484         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 485                                       AMDGPU_GEM_DOMAIN_VRAM |
 486                                       AMDGPU_GEM_DOMAIN_GTT,
 487                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 488                                       (void **)&psp->cmd_buf_mem);
 489         if (ret)
 490                 goto failed2;
 491
 492         return 0;
 493
 494 failed2:
 495         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 496                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 497 failed1:
 498         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 499                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 500         return ret;
 501 }
 502
 503 static int psp_sw_fini(void *handle)
 504 {
 505         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 506         struct psp_context *psp = &adev->psp;
 507         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 508
 509         psp_memory_training_fini(psp);
 510
 511         amdgpu_ucode_release(&psp->sos_fw);
 512         amdgpu_ucode_release(&psp->asd_fw);
 513         amdgpu_ucode_release(&psp->ta_fw);
 514         amdgpu_ucode_release(&psp->cap_fw);
 515         amdgpu_ucode_release(&psp->toc_fw);
 516
 517         kfree(cmd);
 518         cmd = NULL;
 519
 520         psp_free_shared_bufs(psp);
 521
 522         if (psp->km_ring.ring_mem)
 523                 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 524                                       &psp->km_ring.ring_mem_mc_addr,
 525                                       (void **)&psp->km_ring.ring_mem);
 526
 527         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 528                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 529         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 530                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 531         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 532                               (void **)&psp->cmd_buf_mem);
 533
 534         return 0;
 535 }
 536
 537 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 538                  uint32_t reg_val, uint32_t mask, bool check_changed)
 539 {
 540         uint32_t val;
 541         int i;
 542         struct amdgpu_device *adev = psp->adev;
 543
 544         if (psp->adev->no_hw_access)
 545                 return 0;
 546
 547         for (i = 0; i < adev->usec_timeout; i++) {
 548                 val = RREG32(reg_index);
 549                 if (check_changed) {
 550                         if (val != reg_val)
 551                                 return 0;
 552                 } else {
 553                         if ((val & mask) == reg_val)
 554                                 return 0;
 555                 }
 556                 udelay(1);
 557         }
 558
 559         return -ETIME;
 560 }
 561
 562 int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
 563                                uint32_t reg_val, uint32_t mask, uint32_t msec_timeout)
 564 {
 565         uint32_t val;
 566         int i;
 567         struct amdgpu_device *adev = psp->adev;
 568
 569         if (psp->adev->no_hw_access)
 570                 return 0;
 571
 572         for (i = 0; i < msec_timeout; i++) {
 573                 val = RREG32(reg_index);
 574                 if ((val & mask) == reg_val)
 575                         return 0;
 576                 msleep(1);
 577         }
 578
 579         return -ETIME;
 580 }
 581
 582 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
 583 {
 584         switch (cmd_id) {
 585         case GFX_CMD_ID_LOAD_TA:
 586                 return "LOAD_TA";
 587         case GFX_CMD_ID_UNLOAD_TA:
 588                 return "UNLOAD_TA";
 589         case GFX_CMD_ID_INVOKE_CMD:
 590                 return "INVOKE_CMD";
 591         case GFX_CMD_ID_LOAD_ASD:
 592                 return "LOAD_ASD";
 593         case GFX_CMD_ID_SETUP_TMR:
 594                 return "SETUP_TMR";
 595         case GFX_CMD_ID_LOAD_IP_FW:
 596                 return "LOAD_IP_FW";
 597         case GFX_CMD_ID_DESTROY_TMR:
 598                 return "DESTROY_TMR";
 599         case GFX_CMD_ID_SAVE_RESTORE:
 600                 return "SAVE_RESTORE_IP_FW";
 601         case GFX_CMD_ID_SETUP_VMR:
 602                 return "SETUP_VMR";
 603         case GFX_CMD_ID_DESTROY_VMR:
 604                 return "DESTROY_VMR";
 605         case GFX_CMD_ID_PROG_REG:
 606                 return "PROG_REG";
 607         case GFX_CMD_ID_GET_FW_ATTESTATION:
 608                 return "GET_FW_ATTESTATION";
 609         case GFX_CMD_ID_LOAD_TOC:
 610                 return "ID_LOAD_TOC";
 611         case GFX_CMD_ID_AUTOLOAD_RLC:
 612                 return "AUTOLOAD_RLC";
 613         case GFX_CMD_ID_BOOT_CFG:
 614                 return "BOOT_CFG";
 615         default:
 616                 return "UNKNOWN CMD";
 617         }
 618 }
 619
 620 static int
 621 psp_cmd_submit_buf(struct psp_context *psp,
 622                    struct amdgpu_firmware_info *ucode,
 623                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 624 {
 625         int ret;
 626         int index;
 627         int timeout = 20000;
 628         bool ras_intr = false;
 629         bool skip_unsupport = false;
 630
 631         if (psp->adev->no_hw_access)
 632                 return 0;
 633
 634         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 635
 636         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 637
 638         index = atomic_inc_return(&psp->fence_value);
 639         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 640         if (ret) {
 641                 atomic_dec(&psp->fence_value);
 642                 goto exit;
 643         }
 644
 645         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 646         while (*((unsigned int *)psp->fence_buf) != index) {
 647                 if (--timeout == 0)
 648                         break;
 649                 /*
 650                  * Shouldn't wait for timeout when err_event_athub occurs,
 651                  * because gpu reset thread triggered and lock resource should
 652                  * be released for psp resume sequence.
 653                  */
 654                 ras_intr = amdgpu_ras_intr_triggered();
 655                 if (ras_intr)
 656                         break;
 657                 usleep_range(10, 100);
 658                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 659         }
 660
 661         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 662         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 663                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 664
 665         memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 666
 667         /* In some cases, psp response status is not 0 even there is no
 668          * problem while the command is submitted. Some version of PSP FW
 669          * doesn't write 0 to that field.
 670          * So here we would like to only print a warning instead of an error
 671          * during psp initialization to avoid breaking hw_init and it doesn't
 672          * return -EINVAL.
 673          */
 674         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 675                 if (ucode)
 676                         DRM_WARN("failed to load ucode %s(0x%X) ",
 677                                   amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
 678                 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
 679                          psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
 680                          psp->cmd_buf_mem->resp.status);
 681                 /* If any firmware (including CAP) load fails under SRIOV, it should
 682                  * return failure to stop the VF from initializing.
 683                  * Also return failure in case of timeout
 684                  */
 685                 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
 686                         ret = -EINVAL;
 687                         goto exit;
 688                 }
 689         }
 690
 691         if (ucode) {
 692                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 693                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 694         }
 695
 696 exit:
 697         return ret;
 698 }
 699
 700 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
 701 {
 702         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 703
 704         mutex_lock(&psp->mutex);
 705
 706         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 707
 708         return cmd;
 709 }
 710
 711 static void release_psp_cmd_buf(struct psp_context *psp)
 712 {
 713         mutex_unlock(&psp->mutex);
 714 }
 715
 716 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 717                                  struct psp_gfx_cmd_resp *cmd,
 718                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 719 {
 720         struct amdgpu_device *adev = psp->adev;
 721         uint32_t size = 0;
 722         uint64_t tmr_pa = 0;
 723
 724         if (tmr_bo) {
 725                 size = amdgpu_bo_size(tmr_bo);
 726                 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 727         }
 728
 729         if (amdgpu_sriov_vf(psp->adev))
 730                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 731         else
 732                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 733         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 734         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 735         cmd->cmd.cmd_setup_tmr.buf_size = size;
 736         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 737         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 738         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 739 }
 740
 741 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 742                                       uint64_t pri_buf_mc, uint32_t size)
 743 {
 744         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 745         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 746         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 747         cmd->cmd.cmd_load_toc.toc_size = size;
 748 }
 749
 750 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 751 static int psp_load_toc(struct psp_context *psp,
 752                         uint32_t *tmr_size)
 753 {
 754         int ret;
 755         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 756
 757         /* Copy toc to psp firmware private buffer */
 758         psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
 759
 760         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
 761
 762         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 763                                  psp->fence_buf_mc_addr);
 764         if (!ret)
 765                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 766
 767         release_psp_cmd_buf(psp);
 768
 769         return ret;
 770 }
 771
 772 static bool psp_boottime_tmr(struct psp_context *psp)
 773 {
 774         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 775         case IP_VERSION(13, 0, 6):
 776                 return true;
 777         default:
 778                 return false;
 779         }
 780 }
 781
 782 /* Set up Trusted Memory Region */
 783 static int psp_tmr_init(struct psp_context *psp)
 784 {
 785         int ret = 0;
 786         int tmr_size;
 787         void *tmr_buf;
 788         void **pptr;
 789
 790         /*
 791          * According to HW engineer, they prefer the TMR address be "naturally
 792          * aligned" , e.g. the start address be an integer divide of TMR size.
 793          *
 794          * Note: this memory need be reserved till the driver
 795          * uninitializes.
 796          */
 797         tmr_size = PSP_TMR_SIZE(psp->adev);
 798
 799         /* For ASICs support RLC autoload, psp will parse the toc
 800          * and calculate the total size of TMR needed */
 801         if (!amdgpu_sriov_vf(psp->adev) &&
 802             psp->toc.start_addr &&
 803             psp->toc.size_bytes &&
 804             psp->fw_pri_buf) {
 805                 ret = psp_load_toc(psp, &tmr_size);
 806                 if (ret) {
 807                         DRM_ERROR("Failed to load toc\n");
 808                         return ret;
 809                 }
 810         }
 811
 812         if (!psp->tmr_bo) {
 813                 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 814                 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
 815                                               PSP_TMR_ALIGNMENT,
 816                                               AMDGPU_HAS_VRAM(psp->adev) ?
 817                                               AMDGPU_GEM_DOMAIN_VRAM :
 818                                               AMDGPU_GEM_DOMAIN_GTT,
 819                                               &psp->tmr_bo, &psp->tmr_mc_addr,
 820                                               pptr);
 821         }
 822
 823         return ret;
 824 }
 825
 826 static bool psp_skip_tmr(struct psp_context *psp)
 827 {
 828         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 829         case IP_VERSION(11, 0, 9):
 830         case IP_VERSION(11, 0, 7):
 831         case IP_VERSION(13, 0, 2):
 832         case IP_VERSION(13, 0, 6):
 833         case IP_VERSION(13, 0, 10):
 834                 return true;
 835         default:
 836                 return false;
 837         }
 838 }
 839
 840 static int psp_tmr_load(struct psp_context *psp)
 841 {
 842         int ret;
 843         struct psp_gfx_cmd_resp *cmd;
 844
 845         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 846          * Already set up by host driver.
 847          */
 848         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 849                 return 0;
 850
 851         cmd = acquire_psp_cmd_buf(psp);
 852
 853         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 854         if (psp->tmr_bo)
 855                 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 856                          amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 857
 858         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 859                                  psp->fence_buf_mc_addr);
 860
 861         release_psp_cmd_buf(psp);
 862
 863         return ret;
 864 }
 865
 866 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 867                                         struct psp_gfx_cmd_resp *cmd)
 868 {
 869         if (amdgpu_sriov_vf(psp->adev))
 870                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 871         else
 872                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 873 }
 874
 875 static int psp_tmr_unload(struct psp_context *psp)
 876 {
 877         int ret;
 878         struct psp_gfx_cmd_resp *cmd;
 879
 880         /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV,
 881          * as TMR is not loaded at all
 882          */
 883         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 884                 return 0;
 885
 886         cmd = acquire_psp_cmd_buf(psp);
 887
 888         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 889         dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
 890
 891         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 892                                  psp->fence_buf_mc_addr);
 893
 894         release_psp_cmd_buf(psp);
 895
 896         return ret;
 897 }
 898
 899 static int psp_tmr_terminate(struct psp_context *psp)
 900 {
 901         return psp_tmr_unload(psp);
 902 }
 903
 904 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 905                                         uint64_t *output_ptr)
 906 {
 907         int ret;
 908         struct psp_gfx_cmd_resp *cmd;
 909
 910         if (!output_ptr)
 911                 return -EINVAL;
 912
 913         if (amdgpu_sriov_vf(psp->adev))
 914                 return 0;
 915
 916         cmd = acquire_psp_cmd_buf(psp);
 917
 918         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 919
 920         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 921                                  psp->fence_buf_mc_addr);
 922
 923         if (!ret) {
 924                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 925                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 926         }
 927
 928         release_psp_cmd_buf(psp);
 929
 930         return ret;
 931 }
 932
 933 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 934 {
 935         struct psp_context *psp = &adev->psp;
 936         struct psp_gfx_cmd_resp *cmd;
 937         int ret;
 938
 939         if (amdgpu_sriov_vf(adev))
 940                 return 0;
 941
 942         cmd = acquire_psp_cmd_buf(psp);
 943
 944         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 945         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 946
 947         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 948         if (!ret) {
 949                 *boot_cfg =
 950                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 951         }
 952
 953         release_psp_cmd_buf(psp);
 954
 955         return ret;
 956 }
 957
 958 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 959 {
 960         int ret;
 961         struct psp_context *psp = &adev->psp;
 962         struct psp_gfx_cmd_resp *cmd;
 963
 964         if (amdgpu_sriov_vf(adev))
 965                 return 0;
 966
 967         cmd = acquire_psp_cmd_buf(psp);
 968
 969         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 970         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 971         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 972         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 973
 974         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 975
 976         release_psp_cmd_buf(psp);
 977
 978         return ret;
 979 }
 980
 981 static int psp_rl_load(struct amdgpu_device *adev)
 982 {
 983         int ret;
 984         struct psp_context *psp = &adev->psp;
 985         struct psp_gfx_cmd_resp *cmd;
 986
 987         if (!is_psp_fw_valid(psp->rl))
 988                 return 0;
 989
 990         cmd = acquire_psp_cmd_buf(psp);
 991
 992         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 993         memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
 994
 995         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 996         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 997         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 998         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
 999         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
1000
1001         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1002
1003         release_psp_cmd_buf(psp);
1004
1005         return ret;
1006 }
1007
1008 int psp_spatial_partition(struct psp_context *psp, int mode)
1009 {
1010         struct psp_gfx_cmd_resp *cmd;
1011         int ret;
1012
1013         if (amdgpu_sriov_vf(psp->adev))
1014                 return 0;
1015
1016         cmd = acquire_psp_cmd_buf(psp);
1017
1018         cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART;
1019         cmd->cmd.cmd_spatial_part.mode = mode;
1020
1021         dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode);
1022         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1023
1024         release_psp_cmd_buf(psp);
1025
1026         return ret;
1027 }
1028
1029 static int psp_asd_initialize(struct psp_context *psp)
1030 {
1031         int ret;
1032
1033         /* If PSP version doesn't match ASD version, asd loading will be failed.
1034          * add workaround to bypass it for sriov now.
1035          * TODO: add version check to make it common
1036          */
1037         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
1038                 return 0;
1039
1040         psp->asd_context.mem_context.shared_mc_addr  = 0;
1041         psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
1042         psp->asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;
1043
1044         ret = psp_ta_load(psp, &psp->asd_context);
1045         if (!ret)
1046                 psp->asd_context.initialized = true;
1047
1048         return ret;
1049 }
1050
1051 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1052                                        uint32_t session_id)
1053 {
1054         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
1055         cmd->cmd.cmd_unload_ta.session_id = session_id;
1056 }
1057
1058 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
1059 {
1060         int ret;
1061         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1062
1063         psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
1064
1065         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1066
1067         context->resp_status = cmd->resp.status;
1068
1069         release_psp_cmd_buf(psp);
1070
1071         return ret;
1072 }
1073
1074 static int psp_asd_terminate(struct psp_context *psp)
1075 {
1076         int ret;
1077
1078         if (amdgpu_sriov_vf(psp->adev))
1079                 return 0;
1080
1081         if (!psp->asd_context.initialized)
1082                 return 0;
1083
1084         ret = psp_ta_unload(psp, &psp->asd_context);
1085         if (!ret)
1086                 psp->asd_context.initialized = false;
1087
1088         return ret;
1089 }
1090
1091 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1092                 uint32_t id, uint32_t value)
1093 {
1094         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1095         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1096         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1097 }
1098
1099 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1100                 uint32_t value)
1101 {
1102         struct psp_gfx_cmd_resp *cmd;
1103         int ret = 0;
1104
1105         if (reg >= PSP_REG_LAST)
1106                 return -EINVAL;
1107
1108         cmd = acquire_psp_cmd_buf(psp);
1109
1110         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1111         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1112         if (ret)
1113                 DRM_ERROR("PSP failed to program reg id %d", reg);
1114
1115         release_psp_cmd_buf(psp);
1116
1117         return ret;
1118 }
1119
1120 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1121                                      uint64_t ta_bin_mc,
1122                                      struct ta_context *context)
1123 {
1124         cmd->cmd_id                             = context->ta_load_type;
1125         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
1126         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
1127         cmd->cmd.cmd_load_ta.app_len            = context->bin_desc.size_bytes;
1128
1129         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1130                 lower_32_bits(context->mem_context.shared_mc_addr);
1131         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1132                 upper_32_bits(context->mem_context.shared_mc_addr);
1133         cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1134 }
1135
1136 int psp_ta_init_shared_buf(struct psp_context *psp,
1137                                   struct ta_mem_context *mem_ctx)
1138 {
1139         /*
1140         * Allocate 16k memory aligned to 4k from Frame Buffer (local
1141         * physical) for ta to host memory
1142         */
1143         return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1144                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1145                                       AMDGPU_GEM_DOMAIN_GTT,
1146                                       &mem_ctx->shared_bo,
1147                                       &mem_ctx->shared_mc_addr,
1148                                       &mem_ctx->shared_buf);
1149 }
1150
1151 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1152                                        uint32_t ta_cmd_id,
1153                                        uint32_t session_id)
1154 {
1155         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
1156         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
1157         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
1158 }
1159
1160 int psp_ta_invoke(struct psp_context *psp,
1161                   uint32_t ta_cmd_id,
1162                   struct ta_context *context)
1163 {
1164         int ret;
1165         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1166
1167         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1168
1169         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1170                                  psp->fence_buf_mc_addr);
1171
1172         context->resp_status = cmd->resp.status;
1173
1174         release_psp_cmd_buf(psp);
1175
1176         return ret;
1177 }
1178
1179 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1180 {
1181         int ret;
1182         struct psp_gfx_cmd_resp *cmd;
1183
1184         cmd = acquire_psp_cmd_buf(psp);
1185
1186         psp_copy_fw(psp, context->bin_desc.start_addr,
1187                     context->bin_desc.size_bytes);
1188
1189         psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1190
1191         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1192                                  psp->fence_buf_mc_addr);
1193
1194         context->resp_status = cmd->resp.status;
1195
1196         if (!ret)
1197                 context->session_id = cmd->resp.session_id;
1198
1199         release_psp_cmd_buf(psp);
1200
1201         return ret;
1202 }
1203
1204 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1205 {
1206         return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1207 }
1208
1209 int psp_xgmi_terminate(struct psp_context *psp)
1210 {
1211         int ret;
1212         struct amdgpu_device *adev = psp->adev;
1213
1214         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1215         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1216             (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1217              adev->gmc.xgmi.connected_to_cpu))
1218                 return 0;
1219
1220         if (!psp->xgmi_context.context.initialized)
1221                 return 0;
1222
1223         ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1224
1225         psp->xgmi_context.context.initialized = false;
1226
1227         return ret;
1228 }
1229
1230 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1231 {
1232         struct ta_xgmi_shared_memory *xgmi_cmd;
1233         int ret;
1234
1235         if (!psp->ta_fw ||
1236             !psp->xgmi_context.context.bin_desc.size_bytes ||
1237             !psp->xgmi_context.context.bin_desc.start_addr)
1238                 return -ENOENT;
1239
1240         if (!load_ta)
1241                 goto invoke;
1242
1243         psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1244         psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1245
1246         if (!psp->xgmi_context.context.mem_context.shared_buf) {
1247                 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1248                 if (ret)
1249                         return ret;
1250         }
1251
1252         /* Load XGMI TA */
1253         ret = psp_ta_load(psp, &psp->xgmi_context.context);
1254         if (!ret)
1255                 psp->xgmi_context.context.initialized = true;
1256         else
1257                 return ret;
1258
1259 invoke:
1260         /* Initialize XGMI session */
1261         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1262         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1263         xgmi_cmd->flag_extend_link_record = set_extended_data;
1264         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1265
1266         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1267
1268         return ret;
1269 }
1270
1271 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1272 {
1273         struct ta_xgmi_shared_memory *xgmi_cmd;
1274         int ret;
1275
1276         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1277         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1278
1279         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1280
1281         /* Invoke xgmi ta to get hive id */
1282         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1283         if (ret)
1284                 return ret;
1285
1286         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1287
1288         return 0;
1289 }
1290
1291 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1292 {
1293         struct ta_xgmi_shared_memory *xgmi_cmd;
1294         int ret;
1295
1296         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1297         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1298
1299         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1300
1301         /* Invoke xgmi ta to get the node id */
1302         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1303         if (ret)
1304                 return ret;
1305
1306         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1307
1308         return 0;
1309 }
1310
1311 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1312 {
1313         return (psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1314                 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) ||
1315                 psp->adev->ip_versions[MP0_HWIP][0] >= IP_VERSION(13, 0, 6);
1316 }
1317
1318 /*
1319  * Chips that support extended topology information require the driver to
1320  * reflect topology information in the opposite direction.  This is
1321  * because the TA has already exceeded its link record limit and if the
1322  * TA holds bi-directional information, the driver would have to do
1323  * multiple fetches instead of just two.
1324  */
1325 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1326                                         struct psp_xgmi_node_info node_info)
1327 {
1328         struct amdgpu_device *mirror_adev;
1329         struct amdgpu_hive_info *hive;
1330         uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1331         uint64_t dst_node_id = node_info.node_id;
1332         uint8_t dst_num_hops = node_info.num_hops;
1333         uint8_t dst_num_links = node_info.num_links;
1334
1335         hive = amdgpu_get_xgmi_hive(psp->adev);
1336         list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1337                 struct psp_xgmi_topology_info *mirror_top_info;
1338                 int j;
1339
1340                 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1341                         continue;
1342
1343                 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1344                 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1345                         if (mirror_top_info->nodes[j].node_id != src_node_id)
1346                                 continue;
1347
1348                         mirror_top_info->nodes[j].num_hops = dst_num_hops;
1349                         /*
1350                          * prevent 0 num_links value re-reflection since reflection
1351                          * criteria is based on num_hops (direct or indirect).
1352                          *
1353                          */
1354                         if (dst_num_links)
1355                                 mirror_top_info->nodes[j].num_links = dst_num_links;
1356
1357                         break;
1358                 }
1359
1360                 break;
1361         }
1362
1363         amdgpu_put_xgmi_hive(hive);
1364 }
1365
1366 int psp_xgmi_get_topology_info(struct psp_context *psp,
1367                                int number_devices,
1368                                struct psp_xgmi_topology_info *topology,
1369                                bool get_extended_data)
1370 {
1371         struct ta_xgmi_shared_memory *xgmi_cmd;
1372         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1373         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1374         int i;
1375         int ret;
1376
1377         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1378                 return -EINVAL;
1379
1380         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1381         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1382         xgmi_cmd->flag_extend_link_record = get_extended_data;
1383
1384         /* Fill in the shared memory with topology information as input */
1385         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1386         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1387         topology_info_input->num_nodes = number_devices;
1388
1389         for (i = 0; i < topology_info_input->num_nodes; i++) {
1390                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1391                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1392                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1393                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1394         }
1395
1396         /* Invoke xgmi ta to get the topology information */
1397         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1398         if (ret)
1399                 return ret;
1400
1401         /* Read the output topology information from the shared memory */
1402         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1403         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1404         for (i = 0; i < topology->num_nodes; i++) {
1405                 /* extended data will either be 0 or equal to non-extended data */
1406                 if (topology_info_output->nodes[i].num_hops)
1407                         topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1408
1409                 /* non-extended data gets everything here so no need to update */
1410                 if (!get_extended_data) {
1411                         topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1412                         topology->nodes[i].is_sharing_enabled =
1413                                         topology_info_output->nodes[i].is_sharing_enabled;
1414                         topology->nodes[i].sdma_engine =
1415                                         topology_info_output->nodes[i].sdma_engine;
1416                 }
1417
1418         }
1419
1420         /* Invoke xgmi ta again to get the link information */
1421         if (psp_xgmi_peer_link_info_supported(psp)) {
1422                 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1423                 bool requires_reflection =
1424                         (psp->xgmi_context.supports_extended_data && get_extended_data) ||
1425                                 psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6);
1426
1427                 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1428
1429                 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1430
1431                 if (ret)
1432                         return ret;
1433
1434                 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1435                 for (i = 0; i < topology->num_nodes; i++) {
1436                         /* accumulate num_links on extended data */
1437                         topology->nodes[i].num_links = get_extended_data ?
1438                                         topology->nodes[i].num_links +
1439                                                         link_info_output->nodes[i].num_links :
1440                                         ((requires_reflection && topology->nodes[i].num_links) ? topology->nodes[i].num_links :
1441                                          link_info_output->nodes[i].num_links);
1442
1443                         /* reflect the topology information for bi-directionality */
1444                         if (requires_reflection && topology->nodes[i].num_hops)
1445                                 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1446                 }
1447         }
1448
1449         return 0;
1450 }
1451
1452 int psp_xgmi_set_topology_info(struct psp_context *psp,
1453                                int number_devices,
1454                                struct psp_xgmi_topology_info *topology)
1455 {
1456         struct ta_xgmi_shared_memory *xgmi_cmd;
1457         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1458         int i;
1459
1460         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1461                 return -EINVAL;
1462
1463         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1464         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1465
1466         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1467         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1468         topology_info_input->num_nodes = number_devices;
1469
1470         for (i = 0; i < topology_info_input->num_nodes; i++) {
1471                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1472                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1473                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1474                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1475         }
1476
1477         /* Invoke xgmi ta to set topology information */
1478         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1479 }
1480
1481 // ras begin
1482 static void psp_ras_ta_check_status(struct psp_context *psp)
1483 {
1484         struct ta_ras_shared_memory *ras_cmd =
1485                 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1486
1487         switch (ras_cmd->ras_status) {
1488         case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1489                 dev_warn(psp->adev->dev,
1490                                 "RAS WARNING: cmd failed due to unsupported ip\n");
1491                 break;
1492         case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1493                 dev_warn(psp->adev->dev,
1494                                 "RAS WARNING: cmd failed due to unsupported error injection\n");
1495                 break;
1496         case TA_RAS_STATUS__SUCCESS:
1497                 break;
1498         case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1499                 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1500                         dev_warn(psp->adev->dev,
1501                                         "RAS WARNING: Inject error to critical region is not allowed\n");
1502                 break;
1503         default:
1504                 dev_warn(psp->adev->dev,
1505                                 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1506                 break;
1507         }
1508 }
1509
1510 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1511 {
1512         struct ta_ras_shared_memory *ras_cmd;
1513         int ret;
1514
1515         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1516
1517         /*
1518          * TODO: bypass the loading in sriov for now
1519          */
1520         if (amdgpu_sriov_vf(psp->adev))
1521                 return 0;
1522
1523         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1524
1525         if (amdgpu_ras_intr_triggered())
1526                 return ret;
1527
1528         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) {
1529                 DRM_WARN("RAS: Unsupported Interface");
1530                 return -EINVAL;
1531         }
1532
1533         if (!ret) {
1534                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1535                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1536
1537                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1538                 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1539                         dev_warn(psp->adev->dev,
1540                                  "RAS internal register access blocked\n");
1541
1542                 psp_ras_ta_check_status(psp);
1543         }
1544
1545         return ret;
1546 }
1547
1548 int psp_ras_enable_features(struct psp_context *psp,
1549                 union ta_ras_cmd_input *info, bool enable)
1550 {
1551         struct ta_ras_shared_memory *ras_cmd;
1552         int ret;
1553
1554         if (!psp->ras_context.context.initialized)
1555                 return -EINVAL;
1556
1557         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1558         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1559
1560         if (enable)
1561                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1562         else
1563                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1564
1565         ras_cmd->ras_in_message = *info;
1566
1567         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1568         if (ret)
1569                 return -EINVAL;
1570
1571         return 0;
1572 }
1573
1574 int psp_ras_terminate(struct psp_context *psp)
1575 {
1576         int ret;
1577
1578         /*
1579          * TODO: bypass the terminate in sriov for now
1580          */
1581         if (amdgpu_sriov_vf(psp->adev))
1582                 return 0;
1583
1584         if (!psp->ras_context.context.initialized)
1585                 return 0;
1586
1587         ret = psp_ta_unload(psp, &psp->ras_context.context);
1588
1589         psp->ras_context.context.initialized = false;
1590
1591         return ret;
1592 }
1593
1594 int psp_ras_initialize(struct psp_context *psp)
1595 {
1596         int ret;
1597         uint32_t boot_cfg = 0xFF;
1598         struct amdgpu_device *adev = psp->adev;
1599         struct ta_ras_shared_memory *ras_cmd;
1600
1601         /*
1602          * TODO: bypass the initialize in sriov for now
1603          */
1604         if (amdgpu_sriov_vf(adev))
1605                 return 0;
1606
1607         if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1608             !adev->psp.ras_context.context.bin_desc.start_addr) {
1609                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1610                 return 0;
1611         }
1612
1613         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1614                 /* query GECC enablement status from boot config
1615                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1616                  */
1617                 ret = psp_boot_config_get(adev, &boot_cfg);
1618                 if (ret)
1619                         dev_warn(adev->dev, "PSP get boot config failed\n");
1620
1621                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1622                         if (!boot_cfg) {
1623                                 dev_info(adev->dev, "GECC is disabled\n");
1624                         } else {
1625                                 /* disable GECC in next boot cycle if ras is
1626                                  * disabled by module parameter amdgpu_ras_enable
1627                                  * and/or amdgpu_ras_mask, or boot_config_get call
1628                                  * is failed
1629                                  */
1630                                 ret = psp_boot_config_set(adev, 0);
1631                                 if (ret)
1632                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1633                                 else
1634                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1635                         }
1636                 } else {
1637                         if (boot_cfg == 1) {
1638                                 dev_info(adev->dev, "GECC is enabled\n");
1639                         } else {
1640                                 /* enable GECC in next boot cycle if it is disabled
1641                                  * in boot config, or force enable GECC if failed to
1642                                  * get boot configuration
1643                                  */
1644                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1645                                 if (ret)
1646                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1647                                 else
1648                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1649                         }
1650                 }
1651         }
1652
1653         psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1654         psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1655
1656         if (!psp->ras_context.context.mem_context.shared_buf) {
1657                 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1658                 if (ret)
1659                         return ret;
1660         }
1661
1662         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1663         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1664
1665         if (amdgpu_ras_is_poison_mode_supported(adev))
1666                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1667         if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
1668                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1669         ras_cmd->ras_in_message.init_flags.xcc_mask =
1670                 adev->gfx.xcc_mask;
1671         ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2;
1672
1673         ret = psp_ta_load(psp, &psp->ras_context.context);
1674
1675         if (!ret && !ras_cmd->ras_status)
1676                 psp->ras_context.context.initialized = true;
1677         else {
1678                 if (ras_cmd->ras_status)
1679                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1680
1681                 /* fail to load RAS TA */
1682                 psp->ras_context.context.initialized = false;
1683         }
1684
1685         return ret;
1686 }
1687
1688 int psp_ras_trigger_error(struct psp_context *psp,
1689                           struct ta_ras_trigger_error_input *info, uint32_t instance_mask)
1690 {
1691         struct ta_ras_shared_memory *ras_cmd;
1692         struct amdgpu_device *adev = psp->adev;
1693         int ret;
1694         uint32_t dev_mask;
1695
1696         if (!psp->ras_context.context.initialized)
1697                 return -EINVAL;
1698
1699         switch (info->block_id) {
1700         case TA_RAS_BLOCK__GFX:
1701                 dev_mask = GET_MASK(GC, instance_mask);
1702                 break;
1703         case TA_RAS_BLOCK__SDMA:
1704                 dev_mask = GET_MASK(SDMA0, instance_mask);
1705                 break;
1706         case TA_RAS_BLOCK__VCN:
1707         case TA_RAS_BLOCK__JPEG:
1708                 dev_mask = GET_MASK(VCN, instance_mask);
1709                 break;
1710         default:
1711                 dev_mask = instance_mask;
1712                 break;
1713         }
1714
1715         /* reuse sub_block_index for backward compatibility */
1716         dev_mask <<= AMDGPU_RAS_INST_SHIFT;
1717         dev_mask &= AMDGPU_RAS_INST_MASK;
1718         info->sub_block_index |= dev_mask;
1719
1720         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1721         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1722
1723         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1724         ras_cmd->ras_in_message.trigger_error = *info;
1725
1726         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1727         if (ret)
1728                 return -EINVAL;
1729
1730         /* If err_event_athub occurs error inject was successful, however
1731            return status from TA is no long reliable */
1732         if (amdgpu_ras_intr_triggered())
1733                 return 0;
1734
1735         if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1736                 return -EACCES;
1737         else if (ras_cmd->ras_status)
1738                 return -EINVAL;
1739
1740         return 0;
1741 }
1742 // ras end
1743
1744 // HDCP start
1745 static int psp_hdcp_initialize(struct psp_context *psp)
1746 {
1747         int ret;
1748
1749         /*
1750          * TODO: bypass the initialize in sriov for now
1751          */
1752         if (amdgpu_sriov_vf(psp->adev))
1753                 return 0;
1754
1755         if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1756             !psp->hdcp_context.context.bin_desc.start_addr) {
1757                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1758                 return 0;
1759         }
1760
1761         psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1762         psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1763
1764         if (!psp->hdcp_context.context.mem_context.shared_buf) {
1765                 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1766                 if (ret)
1767                         return ret;
1768         }
1769
1770         ret = psp_ta_load(psp, &psp->hdcp_context.context);
1771         if (!ret) {
1772                 psp->hdcp_context.context.initialized = true;
1773                 mutex_init(&psp->hdcp_context.mutex);
1774         }
1775
1776         return ret;
1777 }
1778
1779 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1780 {
1781         /*
1782          * TODO: bypass the loading in sriov for now
1783          */
1784         if (amdgpu_sriov_vf(psp->adev))
1785                 return 0;
1786
1787         return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1788 }
1789
1790 static int psp_hdcp_terminate(struct psp_context *psp)
1791 {
1792         int ret;
1793
1794         /*
1795          * TODO: bypass the terminate in sriov for now
1796          */
1797         if (amdgpu_sriov_vf(psp->adev))
1798                 return 0;
1799
1800         if (!psp->hdcp_context.context.initialized)
1801                 return 0;
1802
1803         ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1804
1805         psp->hdcp_context.context.initialized = false;
1806
1807         return ret;
1808 }
1809 // HDCP end
1810
1811 // DTM start
1812 static int psp_dtm_initialize(struct psp_context *psp)
1813 {
1814         int ret;
1815
1816         /*
1817          * TODO: bypass the initialize in sriov for now
1818          */
1819         if (amdgpu_sriov_vf(psp->adev))
1820                 return 0;
1821
1822         if (!psp->dtm_context.context.bin_desc.size_bytes ||
1823             !psp->dtm_context.context.bin_desc.start_addr) {
1824                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1825                 return 0;
1826         }
1827
1828         psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1829         psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1830
1831         if (!psp->dtm_context.context.mem_context.shared_buf) {
1832                 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1833                 if (ret)
1834                         return ret;
1835         }
1836
1837         ret = psp_ta_load(psp, &psp->dtm_context.context);
1838         if (!ret) {
1839                 psp->dtm_context.context.initialized = true;
1840                 mutex_init(&psp->dtm_context.mutex);
1841         }
1842
1843         return ret;
1844 }
1845
1846 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1847 {
1848         /*
1849          * TODO: bypass the loading in sriov for now
1850          */
1851         if (amdgpu_sriov_vf(psp->adev))
1852                 return 0;
1853
1854         return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1855 }
1856
1857 static int psp_dtm_terminate(struct psp_context *psp)
1858 {
1859         int ret;
1860
1861         /*
1862          * TODO: bypass the terminate in sriov for now
1863          */
1864         if (amdgpu_sriov_vf(psp->adev))
1865                 return 0;
1866
1867         if (!psp->dtm_context.context.initialized)
1868                 return 0;
1869
1870         ret = psp_ta_unload(psp, &psp->dtm_context.context);
1871
1872         psp->dtm_context.context.initialized = false;
1873
1874         return ret;
1875 }
1876 // DTM end
1877
1878 // RAP start
1879 static int psp_rap_initialize(struct psp_context *psp)
1880 {
1881         int ret;
1882         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1883
1884         /*
1885          * TODO: bypass the initialize in sriov for now
1886          */
1887         if (amdgpu_sriov_vf(psp->adev))
1888                 return 0;
1889
1890         if (!psp->rap_context.context.bin_desc.size_bytes ||
1891             !psp->rap_context.context.bin_desc.start_addr) {
1892                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1893                 return 0;
1894         }
1895
1896         psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1897         psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1898
1899         if (!psp->rap_context.context.mem_context.shared_buf) {
1900                 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1901                 if (ret)
1902                         return ret;
1903         }
1904
1905         ret = psp_ta_load(psp, &psp->rap_context.context);
1906         if (!ret) {
1907                 psp->rap_context.context.initialized = true;
1908                 mutex_init(&psp->rap_context.mutex);
1909         } else
1910                 return ret;
1911
1912         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1913         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1914                 psp_rap_terminate(psp);
1915                 /* free rap shared memory */
1916                 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1917
1918                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1919                          ret, status);
1920
1921                 return ret;
1922         }
1923
1924         return 0;
1925 }
1926
1927 static int psp_rap_terminate(struct psp_context *psp)
1928 {
1929         int ret;
1930
1931         if (!psp->rap_context.context.initialized)
1932                 return 0;
1933
1934         ret = psp_ta_unload(psp, &psp->rap_context.context);
1935
1936         psp->rap_context.context.initialized = false;
1937
1938         return ret;
1939 }
1940
1941 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1942 {
1943         struct ta_rap_shared_memory *rap_cmd;
1944         int ret = 0;
1945
1946         if (!psp->rap_context.context.initialized)
1947                 return 0;
1948
1949         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1950             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1951                 return -EINVAL;
1952
1953         mutex_lock(&psp->rap_context.mutex);
1954
1955         rap_cmd = (struct ta_rap_shared_memory *)
1956                   psp->rap_context.context.mem_context.shared_buf;
1957         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1958
1959         rap_cmd->cmd_id = ta_cmd_id;
1960         rap_cmd->validation_method_id = METHOD_A;
1961
1962         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1963         if (ret)
1964                 goto out_unlock;
1965
1966         if (status)
1967                 *status = rap_cmd->rap_status;
1968
1969 out_unlock:
1970         mutex_unlock(&psp->rap_context.mutex);
1971
1972         return ret;
1973 }
1974 // RAP end
1975
1976 /* securedisplay start */
1977 static int psp_securedisplay_initialize(struct psp_context *psp)
1978 {
1979         int ret;
1980         struct ta_securedisplay_cmd *securedisplay_cmd;
1981
1982         /*
1983          * TODO: bypass the initialize in sriov for now
1984          */
1985         if (amdgpu_sriov_vf(psp->adev))
1986                 return 0;
1987
1988         if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1989             !psp->securedisplay_context.context.bin_desc.start_addr) {
1990                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1991                 return 0;
1992         }
1993
1994         psp->securedisplay_context.context.mem_context.shared_mem_size =
1995                 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1996         psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1997
1998         if (!psp->securedisplay_context.context.initialized) {
1999                 ret = psp_ta_init_shared_buf(psp,
2000                                              &psp->securedisplay_context.context.mem_context);
2001                 if (ret)
2002                         return ret;
2003         }
2004
2005         ret = psp_ta_load(psp, &psp->securedisplay_context.context);
2006         if (!ret) {
2007                 psp->securedisplay_context.context.initialized = true;
2008                 mutex_init(&psp->securedisplay_context.mutex);
2009         } else
2010                 return ret;
2011
2012         mutex_lock(&psp->securedisplay_context.mutex);
2013
2014         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
2015                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2016
2017         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2018
2019         mutex_unlock(&psp->securedisplay_context.mutex);
2020
2021         if (ret) {
2022                 psp_securedisplay_terminate(psp);
2023                 /* free securedisplay shared memory */
2024                 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
2025                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
2026                 return -EINVAL;
2027         }
2028
2029         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
2030                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
2031                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
2032                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
2033                 /* don't try again */
2034                 psp->securedisplay_context.context.bin_desc.size_bytes = 0;
2035         }
2036
2037         return 0;
2038 }
2039
2040 static int psp_securedisplay_terminate(struct psp_context *psp)
2041 {
2042         int ret;
2043
2044         /*
2045          * TODO:bypass the terminate in sriov for now
2046          */
2047         if (amdgpu_sriov_vf(psp->adev))
2048                 return 0;
2049
2050         if (!psp->securedisplay_context.context.initialized)
2051                 return 0;
2052
2053         ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
2054
2055         psp->securedisplay_context.context.initialized = false;
2056
2057         return ret;
2058 }
2059
2060 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2061 {
2062         int ret;
2063
2064         if (!psp->securedisplay_context.context.initialized)
2065                 return -EINVAL;
2066
2067         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2068             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
2069                 return -EINVAL;
2070
2071         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
2072
2073         return ret;
2074 }
2075 /* SECUREDISPLAY end */
2076
2077 static int psp_hw_start(struct psp_context *psp)
2078 {
2079         struct amdgpu_device *adev = psp->adev;
2080         int ret;
2081
2082         if (!amdgpu_sriov_vf(adev)) {
2083                 if ((is_psp_fw_valid(psp->kdb)) &&
2084                     (psp->funcs->bootloader_load_kdb != NULL)) {
2085                         ret = psp_bootloader_load_kdb(psp);
2086                         if (ret) {
2087                                 DRM_ERROR("PSP load kdb failed!\n");
2088                                 return ret;
2089                         }
2090                 }
2091
2092                 if ((is_psp_fw_valid(psp->spl)) &&
2093                     (psp->funcs->bootloader_load_spl != NULL)) {
2094                         ret = psp_bootloader_load_spl(psp);
2095                         if (ret) {
2096                                 DRM_ERROR("PSP load spl failed!\n");
2097                                 return ret;
2098                         }
2099                 }
2100
2101                 if ((is_psp_fw_valid(psp->sys)) &&
2102                     (psp->funcs->bootloader_load_sysdrv != NULL)) {
2103                         ret = psp_bootloader_load_sysdrv(psp);
2104                         if (ret) {
2105                                 DRM_ERROR("PSP load sys drv failed!\n");
2106                                 return ret;
2107                         }
2108                 }
2109
2110                 if ((is_psp_fw_valid(psp->soc_drv)) &&
2111                     (psp->funcs->bootloader_load_soc_drv != NULL)) {
2112                         ret = psp_bootloader_load_soc_drv(psp);
2113                         if (ret) {
2114                                 DRM_ERROR("PSP load soc drv failed!\n");
2115                                 return ret;
2116                         }
2117                 }
2118
2119                 if ((is_psp_fw_valid(psp->intf_drv)) &&
2120                     (psp->funcs->bootloader_load_intf_drv != NULL)) {
2121                         ret = psp_bootloader_load_intf_drv(psp);
2122                         if (ret) {
2123                                 DRM_ERROR("PSP load intf drv failed!\n");
2124                                 return ret;
2125                         }
2126                 }
2127
2128                 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2129                     (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2130                         ret = psp_bootloader_load_dbg_drv(psp);
2131                         if (ret) {
2132                                 DRM_ERROR("PSP load dbg drv failed!\n");
2133                                 return ret;
2134                         }
2135                 }
2136
2137                 if ((is_psp_fw_valid(psp->ras_drv)) &&
2138                     (psp->funcs->bootloader_load_ras_drv != NULL)) {
2139                         ret = psp_bootloader_load_ras_drv(psp);
2140                         if (ret) {
2141                                 DRM_ERROR("PSP load ras_drv failed!\n");
2142                                 return ret;
2143                         }
2144                 }
2145
2146                 if ((is_psp_fw_valid(psp->sos)) &&
2147                     (psp->funcs->bootloader_load_sos != NULL)) {
2148                         ret = psp_bootloader_load_sos(psp);
2149                         if (ret) {
2150                                 DRM_ERROR("PSP load sos failed!\n");
2151                                 return ret;
2152                         }
2153                 }
2154         }
2155
2156         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2157         if (ret) {
2158                 DRM_ERROR("PSP create ring failed!\n");
2159                 return ret;
2160         }
2161
2162         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2163                 goto skip_pin_bo;
2164
2165         if (!psp_boottime_tmr(psp)) {
2166                 ret = psp_tmr_init(psp);
2167                 if (ret) {
2168                         DRM_ERROR("PSP tmr init failed!\n");
2169                         return ret;
2170                 }
2171         }
2172
2173 skip_pin_bo:
2174         /*
2175          * For ASICs with DF Cstate management centralized
2176          * to PMFW, TMR setup should be performed after PMFW
2177          * loaded and before other non-psp firmware loaded.
2178          */
2179         if (psp->pmfw_centralized_cstate_management) {
2180                 ret = psp_load_smu_fw(psp);
2181                 if (ret)
2182                         return ret;
2183         }
2184
2185         ret = psp_tmr_load(psp);
2186         if (ret) {
2187                 DRM_ERROR("PSP load tmr failed!\n");
2188                 return ret;
2189         }
2190
2191         return 0;
2192 }
2193
2194 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2195                            enum psp_gfx_fw_type *type)
2196 {
2197         switch (ucode->ucode_id) {
2198         case AMDGPU_UCODE_ID_CAP:
2199                 *type = GFX_FW_TYPE_CAP;
2200                 break;
2201         case AMDGPU_UCODE_ID_SDMA0:
2202                 *type = GFX_FW_TYPE_SDMA0;
2203                 break;
2204         case AMDGPU_UCODE_ID_SDMA1:
2205                 *type = GFX_FW_TYPE_SDMA1;
2206                 break;
2207         case AMDGPU_UCODE_ID_SDMA2:
2208                 *type = GFX_FW_TYPE_SDMA2;
2209                 break;
2210         case AMDGPU_UCODE_ID_SDMA3:
2211                 *type = GFX_FW_TYPE_SDMA3;
2212                 break;
2213         case AMDGPU_UCODE_ID_SDMA4:
2214                 *type = GFX_FW_TYPE_SDMA4;
2215                 break;
2216         case AMDGPU_UCODE_ID_SDMA5:
2217                 *type = GFX_FW_TYPE_SDMA5;
2218                 break;
2219         case AMDGPU_UCODE_ID_SDMA6:
2220                 *type = GFX_FW_TYPE_SDMA6;
2221                 break;
2222         case AMDGPU_UCODE_ID_SDMA7:
2223                 *type = GFX_FW_TYPE_SDMA7;
2224                 break;
2225         case AMDGPU_UCODE_ID_CP_MES:
2226                 *type = GFX_FW_TYPE_CP_MES;
2227                 break;
2228         case AMDGPU_UCODE_ID_CP_MES_DATA:
2229                 *type = GFX_FW_TYPE_MES_STACK;
2230                 break;
2231         case AMDGPU_UCODE_ID_CP_MES1:
2232                 *type = GFX_FW_TYPE_CP_MES_KIQ;
2233                 break;
2234         case AMDGPU_UCODE_ID_CP_MES1_DATA:
2235                 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2236                 break;
2237         case AMDGPU_UCODE_ID_CP_CE:
2238                 *type = GFX_FW_TYPE_CP_CE;
2239                 break;
2240         case AMDGPU_UCODE_ID_CP_PFP:
2241                 *type = GFX_FW_TYPE_CP_PFP;
2242                 break;
2243         case AMDGPU_UCODE_ID_CP_ME:
2244                 *type = GFX_FW_TYPE_CP_ME;
2245                 break;
2246         case AMDGPU_UCODE_ID_CP_MEC1:
2247                 *type = GFX_FW_TYPE_CP_MEC;
2248                 break;
2249         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2250                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2251                 break;
2252         case AMDGPU_UCODE_ID_CP_MEC2:
2253                 *type = GFX_FW_TYPE_CP_MEC;
2254                 break;
2255         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2256                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2257                 break;
2258         case AMDGPU_UCODE_ID_RLC_P:
2259                 *type = GFX_FW_TYPE_RLC_P;
2260                 break;
2261         case AMDGPU_UCODE_ID_RLC_V:
2262                 *type = GFX_FW_TYPE_RLC_V;
2263                 break;
2264         case AMDGPU_UCODE_ID_RLC_G:
2265                 *type = GFX_FW_TYPE_RLC_G;
2266                 break;
2267         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2268                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2269                 break;
2270         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2271                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2272                 break;
2273         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2274                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2275                 break;
2276         case AMDGPU_UCODE_ID_RLC_IRAM:
2277                 *type = GFX_FW_TYPE_RLC_IRAM;
2278                 break;
2279         case AMDGPU_UCODE_ID_RLC_DRAM:
2280                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2281                 break;
2282         case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2283                 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2284                 break;
2285         case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2286                 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2287                 break;
2288         case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2289                 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2290                 break;
2291         case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2292                 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2293                 break;
2294         case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2295                 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2296                 break;
2297         case AMDGPU_UCODE_ID_SMC:
2298                 *type = GFX_FW_TYPE_SMU;
2299                 break;
2300         case AMDGPU_UCODE_ID_PPTABLE:
2301                 *type = GFX_FW_TYPE_PPTABLE;
2302                 break;
2303         case AMDGPU_UCODE_ID_UVD:
2304                 *type = GFX_FW_TYPE_UVD;
2305                 break;
2306         case AMDGPU_UCODE_ID_UVD1:
2307                 *type = GFX_FW_TYPE_UVD1;
2308                 break;
2309         case AMDGPU_UCODE_ID_VCE:
2310                 *type = GFX_FW_TYPE_VCE;
2311                 break;
2312         case AMDGPU_UCODE_ID_VCN:
2313                 *type = GFX_FW_TYPE_VCN;
2314                 break;
2315         case AMDGPU_UCODE_ID_VCN1:
2316                 *type = GFX_FW_TYPE_VCN1;
2317                 break;
2318         case AMDGPU_UCODE_ID_DMCU_ERAM:
2319                 *type = GFX_FW_TYPE_DMCU_ERAM;
2320                 break;
2321         case AMDGPU_UCODE_ID_DMCU_INTV:
2322                 *type = GFX_FW_TYPE_DMCU_ISR;
2323                 break;
2324         case AMDGPU_UCODE_ID_VCN0_RAM:
2325                 *type = GFX_FW_TYPE_VCN0_RAM;
2326                 break;
2327         case AMDGPU_UCODE_ID_VCN1_RAM:
2328                 *type = GFX_FW_TYPE_VCN1_RAM;
2329                 break;
2330         case AMDGPU_UCODE_ID_DMCUB:
2331                 *type = GFX_FW_TYPE_DMUB;
2332                 break;
2333         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2334                 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2335                 break;
2336         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2337                 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2338                 break;
2339         case AMDGPU_UCODE_ID_IMU_I:
2340                 *type = GFX_FW_TYPE_IMU_I;
2341                 break;
2342         case AMDGPU_UCODE_ID_IMU_D:
2343                 *type = GFX_FW_TYPE_IMU_D;
2344                 break;
2345         case AMDGPU_UCODE_ID_CP_RS64_PFP:
2346                 *type = GFX_FW_TYPE_RS64_PFP;
2347                 break;
2348         case AMDGPU_UCODE_ID_CP_RS64_ME:
2349                 *type = GFX_FW_TYPE_RS64_ME;
2350                 break;
2351         case AMDGPU_UCODE_ID_CP_RS64_MEC:
2352                 *type = GFX_FW_TYPE_RS64_MEC;
2353                 break;
2354         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2355                 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2356                 break;
2357         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2358                 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2359                 break;
2360         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2361                 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2362                 break;
2363         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2364                 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2365                 break;
2366         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2367                 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2368                 break;
2369         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2370                 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2371                 break;
2372         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2373                 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2374                 break;
2375         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2376                 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2377                 break;
2378         case AMDGPU_UCODE_ID_MAXIMUM:
2379         default:
2380                 return -EINVAL;
2381         }
2382
2383         return 0;
2384 }
2385
2386 static void psp_print_fw_hdr(struct psp_context *psp,
2387                              struct amdgpu_firmware_info *ucode)
2388 {
2389         struct amdgpu_device *adev = psp->adev;
2390         struct common_firmware_header *hdr;
2391
2392         switch (ucode->ucode_id) {
2393         case AMDGPU_UCODE_ID_SDMA0:
2394         case AMDGPU_UCODE_ID_SDMA1:
2395         case AMDGPU_UCODE_ID_SDMA2:
2396         case AMDGPU_UCODE_ID_SDMA3:
2397         case AMDGPU_UCODE_ID_SDMA4:
2398         case AMDGPU_UCODE_ID_SDMA5:
2399         case AMDGPU_UCODE_ID_SDMA6:
2400         case AMDGPU_UCODE_ID_SDMA7:
2401                 hdr = (struct common_firmware_header *)
2402                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2403                 amdgpu_ucode_print_sdma_hdr(hdr);
2404                 break;
2405         case AMDGPU_UCODE_ID_CP_CE:
2406                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2407                 amdgpu_ucode_print_gfx_hdr(hdr);
2408                 break;
2409         case AMDGPU_UCODE_ID_CP_PFP:
2410                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2411                 amdgpu_ucode_print_gfx_hdr(hdr);
2412                 break;
2413         case AMDGPU_UCODE_ID_CP_ME:
2414                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2415                 amdgpu_ucode_print_gfx_hdr(hdr);
2416                 break;
2417         case AMDGPU_UCODE_ID_CP_MEC1:
2418                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2419                 amdgpu_ucode_print_gfx_hdr(hdr);
2420                 break;
2421         case AMDGPU_UCODE_ID_RLC_G:
2422                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2423                 amdgpu_ucode_print_rlc_hdr(hdr);
2424                 break;
2425         case AMDGPU_UCODE_ID_SMC:
2426                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2427                 amdgpu_ucode_print_smc_hdr(hdr);
2428                 break;
2429         default:
2430                 break;
2431         }
2432 }
2433
2434 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2435                                        struct psp_gfx_cmd_resp *cmd)
2436 {
2437         int ret;
2438         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2439
2440         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2441         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2442         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2443         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2444
2445         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2446         if (ret)
2447                 DRM_ERROR("Unknown firmware type\n");
2448
2449         return ret;
2450 }
2451
2452 int psp_execute_ip_fw_load(struct psp_context *psp,
2453                            struct amdgpu_firmware_info *ucode)
2454 {
2455         int ret = 0;
2456         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2457
2458         ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2459         if (!ret) {
2460                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2461                                          psp->fence_buf_mc_addr);
2462         }
2463
2464         release_psp_cmd_buf(psp);
2465
2466         return ret;
2467 }
2468
2469 static int psp_load_smu_fw(struct psp_context *psp)
2470 {
2471         int ret;
2472         struct amdgpu_device *adev = psp->adev;
2473         struct amdgpu_firmware_info *ucode =
2474                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2475         struct amdgpu_ras *ras = psp->ras_context.ras;
2476
2477         /*
2478          * Skip SMU FW reloading in case of using BACO for runpm only,
2479          * as SMU is always alive.
2480          */
2481         if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2482                 return 0;
2483
2484         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2485                 return 0;
2486
2487         if ((amdgpu_in_reset(adev) &&
2488              ras && adev->ras_enabled &&
2489              (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2490               adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2491                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2492                 if (ret)
2493                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2494         }
2495
2496         ret = psp_execute_ip_fw_load(psp, ucode);
2497
2498         if (ret)
2499                 DRM_ERROR("PSP load smu failed!\n");
2500
2501         return ret;
2502 }
2503
2504 static bool fw_load_skip_check(struct psp_context *psp,
2505                                struct amdgpu_firmware_info *ucode)
2506 {
2507         if (!ucode->fw || !ucode->ucode_size)
2508                 return true;
2509
2510         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2511             (psp_smu_reload_quirk(psp) ||
2512              psp->autoload_supported ||
2513              psp->pmfw_centralized_cstate_management))
2514                 return true;
2515
2516         if (amdgpu_sriov_vf(psp->adev) &&
2517             amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2518                 return true;
2519
2520         if (psp->autoload_supported &&
2521             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2522              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2523                 /* skip mec JT when autoload is enabled */
2524                 return true;
2525
2526         return false;
2527 }
2528
2529 int psp_load_fw_list(struct psp_context *psp,
2530                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2531 {
2532         int ret = 0, i;
2533         struct amdgpu_firmware_info *ucode;
2534
2535         for (i = 0; i < ucode_count; ++i) {
2536                 ucode = ucode_list[i];
2537                 psp_print_fw_hdr(psp, ucode);
2538                 ret = psp_execute_ip_fw_load(psp, ucode);
2539                 if (ret)
2540                         return ret;
2541         }
2542         return ret;
2543 }
2544
2545 static int psp_load_non_psp_fw(struct psp_context *psp)
2546 {
2547         int i, ret;
2548         struct amdgpu_firmware_info *ucode;
2549         struct amdgpu_device *adev = psp->adev;
2550
2551         if (psp->autoload_supported &&
2552             !psp->pmfw_centralized_cstate_management) {
2553                 ret = psp_load_smu_fw(psp);
2554                 if (ret)
2555                         return ret;
2556         }
2557
2558         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2559                 ucode = &adev->firmware.ucode[i];
2560
2561                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2562                     !fw_load_skip_check(psp, ucode)) {
2563                         ret = psp_load_smu_fw(psp);
2564                         if (ret)
2565                                 return ret;
2566                         continue;
2567                 }
2568
2569                 if (fw_load_skip_check(psp, ucode))
2570                         continue;
2571
2572                 if (psp->autoload_supported &&
2573                     (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2574                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2575                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2576                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2577                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2578                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2579                         /* PSP only receive one SDMA fw for sienna_cichlid,
2580                          * as all four sdma fw are same */
2581                         continue;
2582
2583                 psp_print_fw_hdr(psp, ucode);
2584
2585                 ret = psp_execute_ip_fw_load(psp, ucode);
2586                 if (ret)
2587                         return ret;
2588
2589                 /* Start rlc autoload after psp recieved all the gfx firmware */
2590                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2591                     adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2592                         ret = psp_rlc_autoload_start(psp);
2593                         if (ret) {
2594                                 DRM_ERROR("Failed to start rlc autoload\n");
2595                                 return ret;
2596                         }
2597                 }
2598         }
2599
2600         return 0;
2601 }
2602
2603 static int psp_load_fw(struct amdgpu_device *adev)
2604 {
2605         int ret;
2606         struct psp_context *psp = &adev->psp;
2607
2608         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2609                 /* should not destroy ring, only stop */
2610                 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2611         } else {
2612                 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2613
2614                 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2615                 if (ret) {
2616                         DRM_ERROR("PSP ring init failed!\n");
2617                         goto failed;
2618                 }
2619         }
2620
2621         ret = psp_hw_start(psp);
2622         if (ret)
2623                 goto failed;
2624
2625         ret = psp_load_non_psp_fw(psp);
2626         if (ret)
2627                 goto failed1;
2628
2629         ret = psp_asd_initialize(psp);
2630         if (ret) {
2631                 DRM_ERROR("PSP load asd failed!\n");
2632                 goto failed1;
2633         }
2634
2635         ret = psp_rl_load(adev);
2636         if (ret) {
2637                 DRM_ERROR("PSP load RL failed!\n");
2638                 goto failed1;
2639         }
2640
2641         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2642                 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2643                         ret = psp_xgmi_initialize(psp, false, true);
2644                         /* Warning the XGMI seesion initialize failure
2645                         * Instead of stop driver initialization
2646                         */
2647                         if (ret)
2648                                 dev_err(psp->adev->dev,
2649                                         "XGMI: Failed to initialize XGMI session\n");
2650                 }
2651         }
2652
2653         if (psp->ta_fw) {
2654                 ret = psp_ras_initialize(psp);
2655                 if (ret)
2656                         dev_err(psp->adev->dev,
2657                                         "RAS: Failed to initialize RAS\n");
2658
2659                 ret = psp_hdcp_initialize(psp);
2660                 if (ret)
2661                         dev_err(psp->adev->dev,
2662                                 "HDCP: Failed to initialize HDCP\n");
2663
2664                 ret = psp_dtm_initialize(psp);
2665                 if (ret)
2666                         dev_err(psp->adev->dev,
2667                                 "DTM: Failed to initialize DTM\n");
2668
2669                 ret = psp_rap_initialize(psp);
2670                 if (ret)
2671                         dev_err(psp->adev->dev,
2672                                 "RAP: Failed to initialize RAP\n");
2673
2674                 ret = psp_securedisplay_initialize(psp);
2675                 if (ret)
2676                         dev_err(psp->adev->dev,
2677                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2678         }
2679
2680         return 0;
2681
2682 failed1:
2683         psp_free_shared_bufs(psp);
2684 failed:
2685         /*
2686          * all cleanup jobs (xgmi terminate, ras terminate,
2687          * ring destroy, cmd/fence/fw buffers destory,
2688          * psp->cmd destory) are delayed to psp_hw_fini
2689          */
2690         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2691         return ret;
2692 }
2693
2694 static int psp_hw_init(void *handle)
2695 {
2696         int ret;
2697         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2698
2699         mutex_lock(&adev->firmware.mutex);
2700         /*
2701          * This sequence is just used on hw_init only once, no need on
2702          * resume.
2703          */
2704         ret = amdgpu_ucode_init_bo(adev);
2705         if (ret)
2706                 goto failed;
2707
2708         ret = psp_load_fw(adev);
2709         if (ret) {
2710                 DRM_ERROR("PSP firmware loading failed\n");
2711                 goto failed;
2712         }
2713
2714         mutex_unlock(&adev->firmware.mutex);
2715         return 0;
2716
2717 failed:
2718         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2719         mutex_unlock(&adev->firmware.mutex);
2720         return -EINVAL;
2721 }
2722
2723 static int psp_hw_fini(void *handle)
2724 {
2725         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2726         struct psp_context *psp = &adev->psp;
2727
2728         if (psp->ta_fw) {
2729                 psp_ras_terminate(psp);
2730                 psp_securedisplay_terminate(psp);
2731                 psp_rap_terminate(psp);
2732                 psp_dtm_terminate(psp);
2733                 psp_hdcp_terminate(psp);
2734
2735                 if (adev->gmc.xgmi.num_physical_nodes > 1)
2736                         psp_xgmi_terminate(psp);
2737         }
2738
2739         psp_asd_terminate(psp);
2740         psp_tmr_terminate(psp);
2741
2742         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2743
2744         return 0;
2745 }
2746
2747 static int psp_suspend(void *handle)
2748 {
2749         int ret = 0;
2750         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2751         struct psp_context *psp = &adev->psp;
2752
2753         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2754             psp->xgmi_context.context.initialized) {
2755                 ret = psp_xgmi_terminate(psp);
2756                 if (ret) {
2757                         DRM_ERROR("Failed to terminate xgmi ta\n");
2758                         goto out;
2759                 }
2760         }
2761
2762         if (psp->ta_fw) {
2763                 ret = psp_ras_terminate(psp);
2764                 if (ret) {
2765                         DRM_ERROR("Failed to terminate ras ta\n");
2766                         goto out;
2767                 }
2768                 ret = psp_hdcp_terminate(psp);
2769                 if (ret) {
2770                         DRM_ERROR("Failed to terminate hdcp ta\n");
2771                         goto out;
2772                 }
2773                 ret = psp_dtm_terminate(psp);
2774                 if (ret) {
2775                         DRM_ERROR("Failed to terminate dtm ta\n");
2776                         goto out;
2777                 }
2778                 ret = psp_rap_terminate(psp);
2779                 if (ret) {
2780                         DRM_ERROR("Failed to terminate rap ta\n");
2781                         goto out;
2782                 }
2783                 ret = psp_securedisplay_terminate(psp);
2784                 if (ret) {
2785                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2786                         goto out;
2787                 }
2788         }
2789
2790         ret = psp_asd_terminate(psp);
2791         if (ret) {
2792                 DRM_ERROR("Failed to terminate asd\n");
2793                 goto out;
2794         }
2795
2796         ret = psp_tmr_terminate(psp);
2797         if (ret) {
2798                 DRM_ERROR("Failed to terminate tmr\n");
2799                 goto out;
2800         }
2801
2802         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2803         if (ret)
2804                 DRM_ERROR("PSP ring stop failed\n");
2805
2806 out:
2807         return ret;
2808 }
2809
2810 static int psp_resume(void *handle)
2811 {
2812         int ret;
2813         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2814         struct psp_context *psp = &adev->psp;
2815
2816         DRM_INFO("PSP is resuming...\n");
2817
2818         if (psp->mem_train_ctx.enable_mem_training) {
2819                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2820                 if (ret) {
2821                         DRM_ERROR("Failed to process memory training!\n");
2822                         return ret;
2823                 }
2824         }
2825
2826         mutex_lock(&adev->firmware.mutex);
2827
2828         ret = psp_hw_start(psp);
2829         if (ret)
2830                 goto failed;
2831
2832         ret = psp_load_non_psp_fw(psp);
2833         if (ret)
2834                 goto failed;
2835
2836         ret = psp_asd_initialize(psp);
2837         if (ret) {
2838                 DRM_ERROR("PSP load asd failed!\n");
2839                 goto failed;
2840         }
2841
2842         ret = psp_rl_load(adev);
2843         if (ret) {
2844                 dev_err(adev->dev, "PSP load RL failed!\n");
2845                 goto failed;
2846         }
2847
2848         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2849                 ret = psp_xgmi_initialize(psp, false, true);
2850                 /* Warning the XGMI seesion initialize failure
2851                  * Instead of stop driver initialization
2852                  */
2853                 if (ret)
2854                         dev_err(psp->adev->dev,
2855                                 "XGMI: Failed to initialize XGMI session\n");
2856         }
2857
2858         if (psp->ta_fw) {
2859                 ret = psp_ras_initialize(psp);
2860                 if (ret)
2861                         dev_err(psp->adev->dev,
2862                                         "RAS: Failed to initialize RAS\n");
2863
2864                 ret = psp_hdcp_initialize(psp);
2865                 if (ret)
2866                         dev_err(psp->adev->dev,
2867                                 "HDCP: Failed to initialize HDCP\n");
2868
2869                 ret = psp_dtm_initialize(psp);
2870                 if (ret)
2871                         dev_err(psp->adev->dev,
2872                                 "DTM: Failed to initialize DTM\n");
2873
2874                 ret = psp_rap_initialize(psp);
2875                 if (ret)
2876                         dev_err(psp->adev->dev,
2877                                 "RAP: Failed to initialize RAP\n");
2878
2879                 ret = psp_securedisplay_initialize(psp);
2880                 if (ret)
2881                         dev_err(psp->adev->dev,
2882                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2883         }
2884
2885         mutex_unlock(&adev->firmware.mutex);
2886
2887         return 0;
2888
2889 failed:
2890         DRM_ERROR("PSP resume failed\n");
2891         mutex_unlock(&adev->firmware.mutex);
2892         return ret;
2893 }
2894
2895 int psp_gpu_reset(struct amdgpu_device *adev)
2896 {
2897         int ret;
2898
2899         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2900                 return 0;
2901
2902         mutex_lock(&adev->psp.mutex);
2903         ret = psp_mode1_reset(&adev->psp);
2904         mutex_unlock(&adev->psp.mutex);
2905
2906         return ret;
2907 }
2908
2909 int psp_rlc_autoload_start(struct psp_context *psp)
2910 {
2911         int ret;
2912         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2913
2914         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2915
2916         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2917                                  psp->fence_buf_mc_addr);
2918
2919         release_psp_cmd_buf(psp);
2920
2921         return ret;
2922 }
2923
2924 int psp_ring_cmd_submit(struct psp_context *psp,
2925                         uint64_t cmd_buf_mc_addr,
2926                         uint64_t fence_mc_addr,
2927                         int index)
2928 {
2929         unsigned int psp_write_ptr_reg = 0;
2930         struct psp_gfx_rb_frame *write_frame;
2931         struct psp_ring *ring = &psp->km_ring;
2932         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2933         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2934                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2935         struct amdgpu_device *adev = psp->adev;
2936         uint32_t ring_size_dw = ring->ring_size / 4;
2937         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2938
2939         /* KM (GPCOM) prepare write pointer */
2940         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2941
2942         /* Update KM RB frame pointer to new frame */
2943         /* write_frame ptr increments by size of rb_frame in bytes */
2944         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2945         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2946                 write_frame = ring_buffer_start;
2947         else
2948                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2949         /* Check invalid write_frame ptr address */
2950         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2951                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2952                           ring_buffer_start, ring_buffer_end, write_frame);
2953                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2954                 return -EINVAL;
2955         }
2956
2957         /* Initialize KM RB frame */
2958         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2959
2960         /* Update KM RB frame */
2961         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2962         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2963         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2964         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2965         write_frame->fence_value = index;
2966         amdgpu_device_flush_hdp(adev, NULL);
2967
2968         /* Update the write Pointer in DWORDs */
2969         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2970         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2971         return 0;
2972 }
2973
2974 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
2975 {
2976         struct amdgpu_device *adev = psp->adev;
2977         char fw_name[PSP_FW_NAME_LEN];
2978         const struct psp_firmware_header_v1_0 *asd_hdr;
2979         int err = 0;
2980
2981         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2982         err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name);
2983         if (err)
2984                 goto out;
2985
2986         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2987         adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2988         adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2989         adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2990         adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2991                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2992         return 0;
2993 out:
2994         amdgpu_ucode_release(&adev->psp.asd_fw);
2995         return err;
2996 }
2997
2998 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
2999 {
3000         struct amdgpu_device *adev = psp->adev;
3001         char fw_name[PSP_FW_NAME_LEN];
3002         const struct psp_firmware_header_v1_0 *toc_hdr;
3003         int err = 0;
3004
3005         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
3006         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
3007         if (err)
3008                 goto out;
3009
3010         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
3011         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
3012         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
3013         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
3014         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
3015                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
3016         return 0;
3017 out:
3018         amdgpu_ucode_release(&adev->psp.toc_fw);
3019         return err;
3020 }
3021
3022 static int parse_sos_bin_descriptor(struct psp_context *psp,
3023                                    const struct psp_fw_bin_desc *desc,
3024                                    const struct psp_firmware_header_v2_0 *sos_hdr)
3025 {
3026         uint8_t *ucode_start_addr  = NULL;
3027
3028         if (!psp || !desc || !sos_hdr)
3029                 return -EINVAL;
3030
3031         ucode_start_addr  = (uint8_t *)sos_hdr +
3032                             le32_to_cpu(desc->offset_bytes) +
3033                             le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3034
3035         switch (desc->fw_type) {
3036         case PSP_FW_TYPE_PSP_SOS:
3037                 psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
3038                 psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
3039                 psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
3040                 psp->sos.start_addr        = ucode_start_addr;
3041                 break;
3042         case PSP_FW_TYPE_PSP_SYS_DRV:
3043                 psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
3044                 psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
3045                 psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
3046                 psp->sys.start_addr        = ucode_start_addr;
3047                 break;
3048         case PSP_FW_TYPE_PSP_KDB:
3049                 psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
3050                 psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
3051                 psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
3052                 psp->kdb.start_addr        = ucode_start_addr;
3053                 break;
3054         case PSP_FW_TYPE_PSP_TOC:
3055                 psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
3056                 psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
3057                 psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
3058                 psp->toc.start_addr        = ucode_start_addr;
3059                 break;
3060         case PSP_FW_TYPE_PSP_SPL:
3061                 psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
3062                 psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
3063                 psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
3064                 psp->spl.start_addr        = ucode_start_addr;
3065                 break;
3066         case PSP_FW_TYPE_PSP_RL:
3067                 psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
3068                 psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
3069                 psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
3070                 psp->rl.start_addr         = ucode_start_addr;
3071                 break;
3072         case PSP_FW_TYPE_PSP_SOC_DRV:
3073                 psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
3074                 psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
3075                 psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3076                 psp->soc_drv.start_addr         = ucode_start_addr;
3077                 break;
3078         case PSP_FW_TYPE_PSP_INTF_DRV:
3079                 psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
3080                 psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
3081                 psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
3082                 psp->intf_drv.start_addr        = ucode_start_addr;
3083                 break;
3084         case PSP_FW_TYPE_PSP_DBG_DRV:
3085                 psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
3086                 psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
3087                 psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3088                 psp->dbg_drv.start_addr         = ucode_start_addr;
3089                 break;
3090         case PSP_FW_TYPE_PSP_RAS_DRV:
3091                 psp->ras_drv.fw_version         = le32_to_cpu(desc->fw_version);
3092                 psp->ras_drv.feature_version    = le32_to_cpu(desc->fw_version);
3093                 psp->ras_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3094                 psp->ras_drv.start_addr         = ucode_start_addr;
3095                 break;
3096         default:
3097                 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3098                 break;
3099         }
3100
3101         return 0;
3102 }
3103
3104 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3105 {
3106         const struct psp_firmware_header_v1_0 *sos_hdr;
3107         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3108         uint8_t *ucode_array_start_addr;
3109
3110         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3111         ucode_array_start_addr = (uint8_t *)sos_hdr +
3112                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3113
3114         if (adev->gmc.xgmi.connected_to_cpu ||
3115             (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3116                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3117                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3118
3119                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3120                 adev->psp.sys.start_addr = ucode_array_start_addr;
3121
3122                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3123                 adev->psp.sos.start_addr = ucode_array_start_addr +
3124                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
3125         } else {
3126                 /* Load alternate PSP SOS FW */
3127                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3128
3129                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3130                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3131
3132                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3133                 adev->psp.sys.start_addr = ucode_array_start_addr +
3134                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3135
3136                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3137                 adev->psp.sos.start_addr = ucode_array_start_addr +
3138                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3139         }
3140
3141         if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3142                 dev_warn(adev->dev, "PSP SOS FW not available");
3143                 return -EINVAL;
3144         }
3145
3146         return 0;
3147 }
3148
3149 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
3150 {
3151         struct amdgpu_device *adev = psp->adev;
3152         char fw_name[PSP_FW_NAME_LEN];
3153         const struct psp_firmware_header_v1_0 *sos_hdr;
3154         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3155         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3156         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3157         const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3158         int err = 0;
3159         uint8_t *ucode_array_start_addr;
3160         int fw_index = 0;
3161
3162         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3163         err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name);
3164         if (err)
3165                 goto out;
3166
3167         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3168         ucode_array_start_addr = (uint8_t *)sos_hdr +
3169                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3170         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3171
3172         switch (sos_hdr->header.header_version_major) {
3173         case 1:
3174                 err = psp_init_sos_base_fw(adev);
3175                 if (err)
3176                         goto out;
3177
3178                 if (sos_hdr->header.header_version_minor == 1) {
3179                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3180                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3181                         adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3182                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3183                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3184                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3185                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3186                 }
3187                 if (sos_hdr->header.header_version_minor == 2) {
3188                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3189                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3190                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3191                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3192                 }
3193                 if (sos_hdr->header.header_version_minor == 3) {
3194                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3195                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3196                         adev->psp.toc.start_addr = ucode_array_start_addr +
3197                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3198                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3199                         adev->psp.kdb.start_addr = ucode_array_start_addr +
3200                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3201                         adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3202                         adev->psp.spl.start_addr = ucode_array_start_addr +
3203                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3204                         adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3205                         adev->psp.rl.start_addr = ucode_array_start_addr +
3206                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3207                 }
3208                 break;
3209         case 2:
3210                 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3211
3212                 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3213                         dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3214                         err = -EINVAL;
3215                         goto out;
3216                 }
3217
3218                 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3219                         err = parse_sos_bin_descriptor(psp,
3220                                                        &sos_hdr_v2_0->psp_fw_bin[fw_index],
3221                                                        sos_hdr_v2_0);
3222                         if (err)
3223                                 goto out;
3224                 }
3225                 break;
3226         default:
3227                 dev_err(adev->dev,
3228                         "unsupported psp sos firmware\n");
3229                 err = -EINVAL;
3230                 goto out;
3231         }
3232
3233         return 0;
3234 out:
3235         amdgpu_ucode_release(&adev->psp.sos_fw);
3236
3237         return err;
3238 }
3239
3240 static int parse_ta_bin_descriptor(struct psp_context *psp,
3241                                    const struct psp_fw_bin_desc *desc,
3242                                    const struct ta_firmware_header_v2_0 *ta_hdr)
3243 {
3244         uint8_t *ucode_start_addr  = NULL;
3245
3246         if (!psp || !desc || !ta_hdr)
3247                 return -EINVAL;
3248
3249         ucode_start_addr  = (uint8_t *)ta_hdr +
3250                             le32_to_cpu(desc->offset_bytes) +
3251                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3252
3253         switch (desc->fw_type) {
3254         case TA_FW_TYPE_PSP_ASD:
3255                 psp->asd_context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3256                 psp->asd_context.bin_desc.feature_version   = le32_to_cpu(desc->fw_version);
3257                 psp->asd_context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3258                 psp->asd_context.bin_desc.start_addr        = ucode_start_addr;
3259                 break;
3260         case TA_FW_TYPE_PSP_XGMI:
3261                 psp->xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3262                 psp->xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3263                 psp->xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;
3264                 break;
3265         case TA_FW_TYPE_PSP_RAS:
3266                 psp->ras_context.context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3267                 psp->ras_context.context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3268                 psp->ras_context.context.bin_desc.start_addr        = ucode_start_addr;
3269                 break;
3270         case TA_FW_TYPE_PSP_HDCP:
3271                 psp->hdcp_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3272                 psp->hdcp_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3273                 psp->hdcp_context.context.bin_desc.start_addr       = ucode_start_addr;
3274                 break;
3275         case TA_FW_TYPE_PSP_DTM:
3276                 psp->dtm_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3277                 psp->dtm_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3278                 psp->dtm_context.context.bin_desc.start_addr       = ucode_start_addr;
3279                 break;
3280         case TA_FW_TYPE_PSP_RAP:
3281                 psp->rap_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3282                 psp->rap_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3283                 psp->rap_context.context.bin_desc.start_addr       = ucode_start_addr;
3284                 break;
3285         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3286                 psp->securedisplay_context.context.bin_desc.fw_version =
3287                         le32_to_cpu(desc->fw_version);
3288                 psp->securedisplay_context.context.bin_desc.size_bytes =
3289                         le32_to_cpu(desc->size_bytes);
3290                 psp->securedisplay_context.context.bin_desc.start_addr =
3291                         ucode_start_addr;
3292                 break;
3293         default:
3294                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3295                 break;
3296         }
3297
3298         return 0;
3299 }
3300
3301 static int parse_ta_v1_microcode(struct psp_context *psp)
3302 {
3303         const struct ta_firmware_header_v1_0 *ta_hdr;
3304         struct amdgpu_device *adev = psp->adev;
3305
3306         ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
3307
3308         if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
3309                 return -EINVAL;
3310
3311         adev->psp.xgmi_context.context.bin_desc.fw_version =
3312                 le32_to_cpu(ta_hdr->xgmi.fw_version);
3313         adev->psp.xgmi_context.context.bin_desc.size_bytes =
3314                 le32_to_cpu(ta_hdr->xgmi.size_bytes);
3315         adev->psp.xgmi_context.context.bin_desc.start_addr =
3316                 (uint8_t *)ta_hdr +
3317                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3318
3319         adev->psp.ras_context.context.bin_desc.fw_version =
3320                 le32_to_cpu(ta_hdr->ras.fw_version);
3321         adev->psp.ras_context.context.bin_desc.size_bytes =
3322                 le32_to_cpu(ta_hdr->ras.size_bytes);
3323         adev->psp.ras_context.context.bin_desc.start_addr =
3324                 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
3325                 le32_to_cpu(ta_hdr->ras.offset_bytes);
3326
3327         adev->psp.hdcp_context.context.bin_desc.fw_version =
3328                 le32_to_cpu(ta_hdr->hdcp.fw_version);
3329         adev->psp.hdcp_context.context.bin_desc.size_bytes =
3330                 le32_to_cpu(ta_hdr->hdcp.size_bytes);
3331         adev->psp.hdcp_context.context.bin_desc.start_addr =
3332                 (uint8_t *)ta_hdr +
3333                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3334
3335         adev->psp.dtm_context.context.bin_desc.fw_version =
3336                 le32_to_cpu(ta_hdr->dtm.fw_version);
3337         adev->psp.dtm_context.context.bin_desc.size_bytes =
3338                 le32_to_cpu(ta_hdr->dtm.size_bytes);
3339         adev->psp.dtm_context.context.bin_desc.start_addr =
3340                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3341                 le32_to_cpu(ta_hdr->dtm.offset_bytes);
3342
3343         adev->psp.securedisplay_context.context.bin_desc.fw_version =
3344                 le32_to_cpu(ta_hdr->securedisplay.fw_version);
3345         adev->psp.securedisplay_context.context.bin_desc.size_bytes =
3346                 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
3347         adev->psp.securedisplay_context.context.bin_desc.start_addr =
3348                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3349                 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
3350
3351         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
3352
3353         return 0;
3354 }
3355
3356 static int parse_ta_v2_microcode(struct psp_context *psp)
3357 {
3358         const struct ta_firmware_header_v2_0 *ta_hdr;
3359         struct amdgpu_device *adev = psp->adev;
3360         int err = 0;
3361         int ta_index = 0;
3362
3363         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3364
3365         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
3366                 return -EINVAL;
3367
3368         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3369                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3370                 return -EINVAL;
3371         }
3372
3373         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3374                 err = parse_ta_bin_descriptor(psp,
3375                                               &ta_hdr->ta_fw_bin[ta_index],
3376                                               ta_hdr);
3377                 if (err)
3378                         return err;
3379         }
3380
3381         return 0;
3382 }
3383
3384 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
3385 {
3386         const struct common_firmware_header *hdr;
3387         struct amdgpu_device *adev = psp->adev;
3388         char fw_name[PSP_FW_NAME_LEN];
3389         int err;
3390
3391         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3392         err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name);
3393         if (err)
3394                 return err;
3395
3396         hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
3397         switch (le16_to_cpu(hdr->header_version_major)) {
3398         case 1:
3399                 err = parse_ta_v1_microcode(psp);
3400                 break;
3401         case 2:
3402                 err = parse_ta_v2_microcode(psp);
3403                 break;
3404         default:
3405                 dev_err(adev->dev, "unsupported TA header version\n");
3406                 err = -EINVAL;
3407         }
3408
3409         if (err)
3410                 amdgpu_ucode_release(&adev->psp.ta_fw);
3411
3412         return err;
3413 }
3414
3415 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
3416 {
3417         struct amdgpu_device *adev = psp->adev;
3418         char fw_name[PSP_FW_NAME_LEN];
3419         const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3420         struct amdgpu_firmware_info *info = NULL;
3421         int err = 0;
3422
3423         if (!amdgpu_sriov_vf(adev)) {
3424                 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3425                 return -EINVAL;
3426         }
3427
3428         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3429         err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name);
3430         if (err) {
3431                 if (err == -ENODEV) {
3432                         dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3433                         err = 0;
3434                         goto out;
3435                 }
3436                 dev_err(adev->dev, "fail to initialize cap microcode\n");
3437         }
3438
3439         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3440         info->ucode_id = AMDGPU_UCODE_ID_CAP;
3441         info->fw = adev->psp.cap_fw;
3442         cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3443                 adev->psp.cap_fw->data;
3444         adev->firmware.fw_size += ALIGN(
3445                         le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3446         adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3447         adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3448         adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3449
3450         return 0;
3451
3452 out:
3453         amdgpu_ucode_release(&adev->psp.cap_fw);
3454         return err;
3455 }
3456
3457 static int psp_set_clockgating_state(void *handle,
3458                                      enum amd_clockgating_state state)
3459 {
3460         return 0;
3461 }
3462
3463 static int psp_set_powergating_state(void *handle,
3464                                      enum amd_powergating_state state)
3465 {
3466         return 0;
3467 }
3468
3469 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3470                                          struct device_attribute *attr,
3471                                          char *buf)
3472 {
3473         struct drm_device *ddev = dev_get_drvdata(dev);
3474         struct amdgpu_device *adev = drm_to_adev(ddev);
3475         uint32_t fw_ver;
3476         int ret;
3477
3478         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3479                 DRM_INFO("PSP block is not ready yet.");
3480                 return -EBUSY;
3481         }
3482
3483         mutex_lock(&adev->psp.mutex);
3484         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3485         mutex_unlock(&adev->psp.mutex);
3486
3487         if (ret) {
3488                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3489                 return ret;
3490         }
3491
3492         return sysfs_emit(buf, "%x\n", fw_ver);
3493 }
3494
3495 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3496                                                        struct device_attribute *attr,
3497                                                        const char *buf,
3498                                                        size_t count)
3499 {
3500         struct drm_device *ddev = dev_get_drvdata(dev);
3501         struct amdgpu_device *adev = drm_to_adev(ddev);
3502         int ret, idx;
3503         char fw_name[100];
3504         const struct firmware *usbc_pd_fw;
3505         struct amdgpu_bo *fw_buf_bo = NULL;
3506         uint64_t fw_pri_mc_addr;
3507         void *fw_pri_cpu_addr;
3508
3509         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3510                 DRM_INFO("PSP block is not ready yet.");
3511                 return -EBUSY;
3512         }
3513
3514         if (!drm_dev_enter(ddev, &idx))
3515                 return -ENODEV;
3516
3517         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3518         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3519         if (ret)
3520                 goto fail;
3521
3522         /* LFB address which is aligned to 1MB boundary per PSP request */
3523         ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3524                                       AMDGPU_GEM_DOMAIN_VRAM |
3525                                       AMDGPU_GEM_DOMAIN_GTT,
3526                                       &fw_buf_bo, &fw_pri_mc_addr,
3527                                       &fw_pri_cpu_addr);
3528         if (ret)
3529                 goto rel_buf;
3530
3531         memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3532
3533         mutex_lock(&adev->psp.mutex);
3534         ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3535         mutex_unlock(&adev->psp.mutex);
3536
3537         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3538
3539 rel_buf:
3540         release_firmware(usbc_pd_fw);
3541 fail:
3542         if (ret) {
3543                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3544                 count = ret;
3545         }
3546
3547         drm_dev_exit(idx);
3548         return count;
3549 }
3550
3551 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3552 {
3553         int idx;
3554
3555         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3556                 return;
3557
3558         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3559         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3560
3561         drm_dev_exit(idx);
3562 }
3563
3564 /**
3565  * DOC: usbc_pd_fw
3566  * Reading from this file will retrieve the USB-C PD firmware version. Writing to
3567  * this file will trigger the update process.
3568  */
3569 static DEVICE_ATTR(usbc_pd_fw, 0644,
3570                    psp_usbc_pd_fw_sysfs_read,
3571                    psp_usbc_pd_fw_sysfs_write);
3572
3573 int is_psp_fw_valid(struct psp_bin_desc bin)
3574 {
3575         return bin.size_bytes;
3576 }
3577
3578 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3579                                         struct bin_attribute *bin_attr,
3580                                         char *buffer, loff_t pos, size_t count)
3581 {
3582         struct device *dev = kobj_to_dev(kobj);
3583         struct drm_device *ddev = dev_get_drvdata(dev);
3584         struct amdgpu_device *adev = drm_to_adev(ddev);
3585
3586         adev->psp.vbflash_done = false;
3587
3588         /* Safeguard against memory drain */
3589         if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3590                 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3591                 kvfree(adev->psp.vbflash_tmp_buf);
3592                 adev->psp.vbflash_tmp_buf = NULL;
3593                 adev->psp.vbflash_image_size = 0;
3594                 return -ENOMEM;
3595         }
3596
3597         /* TODO Just allocate max for now and optimize to realloc later if needed */
3598         if (!adev->psp.vbflash_tmp_buf) {
3599                 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3600                 if (!adev->psp.vbflash_tmp_buf)
3601                         return -ENOMEM;
3602         }
3603
3604         mutex_lock(&adev->psp.mutex);
3605         memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3606         adev->psp.vbflash_image_size += count;
3607         mutex_unlock(&adev->psp.mutex);
3608
3609         dev_dbg(adev->dev, "IFWI staged for update");
3610
3611         return count;
3612 }
3613
3614 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3615                                        struct bin_attribute *bin_attr, char *buffer,
3616                                        loff_t pos, size_t count)
3617 {
3618         struct device *dev = kobj_to_dev(kobj);
3619         struct drm_device *ddev = dev_get_drvdata(dev);
3620         struct amdgpu_device *adev = drm_to_adev(ddev);
3621         struct amdgpu_bo *fw_buf_bo = NULL;
3622         uint64_t fw_pri_mc_addr;
3623         void *fw_pri_cpu_addr;
3624         int ret;
3625
3626         if (adev->psp.vbflash_image_size == 0)
3627                 return -EINVAL;
3628
3629         dev_dbg(adev->dev, "PSP IFWI flash process initiated");
3630
3631         ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3632                                         AMDGPU_GPU_PAGE_SIZE,
3633                                         AMDGPU_GEM_DOMAIN_VRAM,
3634                                         &fw_buf_bo,
3635                                         &fw_pri_mc_addr,
3636                                         &fw_pri_cpu_addr);
3637         if (ret)
3638                 goto rel_buf;
3639
3640         memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3641
3642         mutex_lock(&adev->psp.mutex);
3643         ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3644         mutex_unlock(&adev->psp.mutex);
3645
3646         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3647
3648 rel_buf:
3649         kvfree(adev->psp.vbflash_tmp_buf);
3650         adev->psp.vbflash_tmp_buf = NULL;
3651         adev->psp.vbflash_image_size = 0;
3652
3653         if (ret) {
3654                 dev_err(adev->dev, "Failed to load IFWI, err = %d", ret);
3655                 return ret;
3656         }
3657
3658         dev_dbg(adev->dev, "PSP IFWI flash process done");
3659         return 0;
3660 }
3661
3662 /**
3663  * DOC: psp_vbflash
3664  * Writing to this file will stage an IFWI for update. Reading from this file
3665  * will trigger the update process.
3666  */
3667 static struct bin_attribute psp_vbflash_bin_attr = {
3668         .attr = {.name = "psp_vbflash", .mode = 0660},
3669         .size = 0,
3670         .write = amdgpu_psp_vbflash_write,
3671         .read = amdgpu_psp_vbflash_read,
3672 };
3673
3674 /**
3675  * DOC: psp_vbflash_status
3676  * The status of the flash process.
3677  * 0: IFWI flash not complete.
3678  * 1: IFWI flash complete.
3679  */
3680 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3681                                          struct device_attribute *attr,
3682                                          char *buf)
3683 {
3684         struct drm_device *ddev = dev_get_drvdata(dev);
3685         struct amdgpu_device *adev = drm_to_adev(ddev);
3686         uint32_t vbflash_status;
3687
3688         vbflash_status = psp_vbflash_status(&adev->psp);
3689         if (!adev->psp.vbflash_done)
3690                 vbflash_status = 0;
3691         else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3692                 vbflash_status = 1;
3693
3694         return sysfs_emit(buf, "0x%x\n", vbflash_status);
3695 }
3696 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);
3697
3698 static struct bin_attribute *bin_flash_attrs[] = {
3699         &psp_vbflash_bin_attr,
3700         NULL
3701 };
3702
3703 static struct attribute *flash_attrs[] = {
3704         &dev_attr_psp_vbflash_status.attr,
3705         &dev_attr_usbc_pd_fw.attr,
3706         NULL
3707 };
3708
3709 static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
3710 {
3711         struct device *dev = kobj_to_dev(kobj);
3712         struct drm_device *ddev = dev_get_drvdata(dev);
3713         struct amdgpu_device *adev = drm_to_adev(ddev);
3714
3715         if (attr == &dev_attr_usbc_pd_fw.attr)
3716                 return adev->psp.sup_pd_fw_up ? 0660 : 0;
3717
3718         return adev->psp.sup_ifwi_up ? 0440 : 0;
3719 }
3720
3721 static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj,
3722                                                 struct bin_attribute *attr,
3723                                                 int idx)
3724 {
3725         struct device *dev = kobj_to_dev(kobj);
3726         struct drm_device *ddev = dev_get_drvdata(dev);
3727         struct amdgpu_device *adev = drm_to_adev(ddev);
3728
3729         return adev->psp.sup_ifwi_up ? 0660 : 0;
3730 }
3731
3732 const struct attribute_group amdgpu_flash_attr_group = {
3733         .attrs = flash_attrs,
3734         .bin_attrs = bin_flash_attrs,
3735         .is_bin_visible = amdgpu_bin_flash_attr_is_visible,
3736         .is_visible = amdgpu_flash_attr_is_visible,
3737 };
3738
3739 const struct amd_ip_funcs psp_ip_funcs = {
3740         .name = "psp",
3741         .early_init = psp_early_init,
3742         .late_init = NULL,
3743         .sw_init = psp_sw_init,
3744         .sw_fini = psp_sw_fini,
3745         .hw_init = psp_hw_init,
3746         .hw_fini = psp_hw_fini,
3747         .suspend = psp_suspend,
3748         .resume = psp_resume,
3749         .is_idle = NULL,
3750         .check_soft_reset = NULL,
3751         .wait_for_idle = NULL,
3752         .soft_reset = NULL,
3753         .set_clockgating_state = psp_set_clockgating_state,
3754         .set_powergating_state = psp_set_powergating_state,
3755 };
3756
3757 const struct amdgpu_ip_block_version psp_v3_1_ip_block = {
3758         .type = AMD_IP_BLOCK_TYPE_PSP,
3759         .major = 3,
3760         .minor = 1,
3761         .rev = 0,
3762         .funcs = &psp_ip_funcs,
3763 };
3764
3765 const struct amdgpu_ip_block_version psp_v10_0_ip_block = {
3766         .type = AMD_IP_BLOCK_TYPE_PSP,
3767         .major = 10,
3768         .minor = 0,
3769         .rev = 0,
3770         .funcs = &psp_ip_funcs,
3771 };
3772
3773 const struct amdgpu_ip_block_version psp_v11_0_ip_block = {
3774         .type = AMD_IP_BLOCK_TYPE_PSP,
3775         .major = 11,
3776         .minor = 0,
3777         .rev = 0,
3778         .funcs = &psp_ip_funcs,
3779 };
3780
3781 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3782         .type = AMD_IP_BLOCK_TYPE_PSP,
3783         .major = 11,
3784         .minor = 0,
3785         .rev = 8,
3786         .funcs = &psp_ip_funcs,
3787 };
3788
3789 const struct amdgpu_ip_block_version psp_v12_0_ip_block = {
3790         .type = AMD_IP_BLOCK_TYPE_PSP,
3791         .major = 12,
3792         .minor = 0,
3793         .rev = 0,
3794         .funcs = &psp_ip_funcs,
3795 };
3796
3797 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3798         .type = AMD_IP_BLOCK_TYPE_PSP,
3799         .major = 13,
3800         .minor = 0,
3801         .rev = 0,
3802         .funcs = &psp_ip_funcs,
3803 };
3804
3805 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3806         .type = AMD_IP_BLOCK_TYPE_PSP,
3807         .major = 13,
3808         .minor = 0,
3809         .rev = 4,
3810         .funcs = &psp_ip_funcs,
3811 };