2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <linux/dma-buf.h>
36 #include <drm/amdgpu_drm.h>
37 #include <drm/drm_cache.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_amdkfd.h"
45 * This defines the interfaces to operate on an &amdgpu_bo buffer object which
46 * represents memory used by driver (VRAM, system memory, etc.). The driver
47 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces
48 * to create/destroy/set buffer object which are then managed by the kernel TTM
50 * The interfaces are also used internally by kernel clients, including gfx,
51 * uvd, etc. for kernel managed allocations used by the GPU.
56 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting
58 * @bo: &amdgpu_bo buffer object
60 * This function is called when a BO stops being pinned, and updates the
61 * &amdgpu_device pin_size values accordingly.
63 static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo)
65 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
67 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
68 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
69 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
70 &adev->visible_pin_size);
71 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
72 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
76 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
78 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
79 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
81 if (bo->tbo.pin_count > 0)
82 amdgpu_bo_subtract_pin_size(bo);
86 if (bo->tbo.base.import_attach)
87 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
88 drm_gem_object_release(&bo->tbo.base);
89 /* in case amdgpu_device_recover_vram got NULL of bo->parent */
90 if (!list_empty(&bo->shadow_list)) {
91 mutex_lock(&adev->shadow_list_lock);
92 list_del_init(&bo->shadow_list);
93 mutex_unlock(&adev->shadow_list_lock);
95 amdgpu_bo_unref(&bo->parent);
102 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo
103 * @bo: buffer object to be checked
105 * Uses destroy function associated with the object to determine if this is
109 * true if the object belongs to &amdgpu_bo, false if not.
111 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
113 if (bo->destroy == &amdgpu_bo_destroy)
119 * amdgpu_bo_placement_from_domain - set buffer's placement
120 * @abo: &amdgpu_bo buffer object whose placement is to be set
121 * @domain: requested domain
123 * Sets buffer's placement according to requested domain and the buffer's
126 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
128 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
129 struct ttm_placement *placement = &abo->placement;
130 struct ttm_place *places = abo->placements;
131 u64 flags = abo->flags;
134 if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
135 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
139 places[c].mem_type = TTM_PL_VRAM;
142 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
143 places[c].lpfn = visible_pfn;
145 places[c].flags |= TTM_PL_FLAG_TOPDOWN;
147 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
148 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
152 if (domain & AMDGPU_GEM_DOMAIN_GTT) {
155 places[c].mem_type = TTM_PL_TT;
160 if (domain & AMDGPU_GEM_DOMAIN_CPU) {
163 places[c].mem_type = TTM_PL_SYSTEM;
168 if (domain & AMDGPU_GEM_DOMAIN_GDS) {
171 places[c].mem_type = AMDGPU_PL_GDS;
176 if (domain & AMDGPU_GEM_DOMAIN_GWS) {
179 places[c].mem_type = AMDGPU_PL_GWS;
184 if (domain & AMDGPU_GEM_DOMAIN_OA) {
187 places[c].mem_type = AMDGPU_PL_OA;
195 places[c].mem_type = TTM_PL_SYSTEM;
200 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS);
202 placement->num_placement = c;
203 placement->placement = places;
205 placement->num_busy_placement = c;
206 placement->busy_placement = places;
210 * amdgpu_bo_create_reserved - create reserved BO for kernel use
212 * @adev: amdgpu device object
213 * @size: size for the new BO
214 * @align: alignment for the new BO
215 * @domain: where to place it
216 * @bo_ptr: used to initialize BOs in structures
217 * @gpu_addr: GPU addr of the pinned BO
218 * @cpu_addr: optional CPU address mapping
220 * Allocates and pins a BO for kernel internal use, and returns it still
223 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
226 * 0 on success, negative error code otherwise.
228 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
229 unsigned long size, int align,
230 u32 domain, struct amdgpu_bo **bo_ptr,
231 u64 *gpu_addr, void **cpu_addr)
233 struct amdgpu_bo_param bp;
238 amdgpu_bo_unref(bo_ptr);
242 memset(&bp, 0, sizeof(bp));
244 bp.byte_align = align;
246 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
247 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
248 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
249 bp.type = ttm_bo_type_kernel;
253 r = amdgpu_bo_create(adev, &bp, bo_ptr);
255 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
262 r = amdgpu_bo_reserve(*bo_ptr, false);
264 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
268 r = amdgpu_bo_pin(*bo_ptr, domain);
270 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
271 goto error_unreserve;
274 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo);
276 dev_err(adev->dev, "%p bind failed\n", *bo_ptr);
281 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr);
284 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
286 dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
294 amdgpu_bo_unpin(*bo_ptr);
296 amdgpu_bo_unreserve(*bo_ptr);
300 amdgpu_bo_unref(bo_ptr);
306 * amdgpu_bo_create_kernel - create BO for kernel use
308 * @adev: amdgpu device object
309 * @size: size for the new BO
310 * @align: alignment for the new BO
311 * @domain: where to place it
312 * @bo_ptr: used to initialize BOs in structures
313 * @gpu_addr: GPU addr of the pinned BO
314 * @cpu_addr: optional CPU address mapping
316 * Allocates and pins a BO for kernel internal use.
318 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
321 * 0 on success, negative error code otherwise.
323 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
324 unsigned long size, int align,
325 u32 domain, struct amdgpu_bo **bo_ptr,
326 u64 *gpu_addr, void **cpu_addr)
330 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
337 amdgpu_bo_unreserve(*bo_ptr);
343 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
345 * @adev: amdgpu device object
346 * @offset: offset of the BO
347 * @size: size of the BO
348 * @domain: where to place it
349 * @bo_ptr: used to initialize BOs in structures
350 * @cpu_addr: optional CPU address mapping
352 * Creates a kernel BO at a specific offset in the address space of the domain.
355 * 0 on success, negative error code otherwise.
357 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
358 uint64_t offset, uint64_t size, uint32_t domain,
359 struct amdgpu_bo **bo_ptr, void **cpu_addr)
361 struct ttm_operation_ctx ctx = { false, false };
366 size = ALIGN(size, PAGE_SIZE);
368 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr,
373 if ((*bo_ptr) == NULL)
377 * Remove the original mem node and create a new one at the request
381 amdgpu_bo_kunmap(*bo_ptr);
383 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem);
385 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
386 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
387 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
389 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
390 &(*bo_ptr)->tbo.mem, &ctx);
395 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
400 amdgpu_bo_unreserve(*bo_ptr);
404 amdgpu_bo_unreserve(*bo_ptr);
405 amdgpu_bo_unref(bo_ptr);
410 * amdgpu_bo_free_kernel - free BO for kernel use
412 * @bo: amdgpu BO to free
413 * @gpu_addr: pointer to where the BO's GPU memory space address was stored
414 * @cpu_addr: pointer to where the BO's CPU memory space address was stored
416 * unmaps and unpin a BO for kernel internal use.
418 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
424 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
426 amdgpu_bo_kunmap(*bo);
428 amdgpu_bo_unpin(*bo);
429 amdgpu_bo_unreserve(*bo);
440 /* Validate bo size is bit bigger then the request domain */
441 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
442 unsigned long size, u32 domain)
444 struct ttm_resource_manager *man = NULL;
447 * If GTT is part of requested domains the check must succeed to
448 * allow fall back to GTT
450 if (domain & AMDGPU_GEM_DOMAIN_GTT) {
451 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
453 if (size < (man->size << PAGE_SHIFT))
459 if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
460 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
462 if (size < (man->size << PAGE_SHIFT))
469 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
473 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
474 man->size << PAGE_SHIFT);
478 bool amdgpu_bo_support_uswc(u64 bo_flags)
482 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
483 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
486 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
487 /* Don't try to enable write-combining when it can't work, or things
489 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
492 #ifndef CONFIG_COMPILE_TEST
493 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
494 thanks to write-combining
497 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
498 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
499 "better performance thanks to write-combining\n");
502 /* For architectures that don't support WC memory,
503 * mask out the WC flag from the BO
505 if (!drm_arch_can_wc_memory())
512 static int amdgpu_bo_do_create(struct amdgpu_device *adev,
513 struct amdgpu_bo_param *bp,
514 struct amdgpu_bo **bo_ptr)
516 struct ttm_operation_ctx ctx = {
517 .interruptible = (bp->type != ttm_bo_type_kernel),
518 .no_wait_gpu = bp->no_wait_gpu,
519 /* We opt to avoid OOM on system pages allocations */
520 .gfp_retry_mayfail = true,
521 .allow_res_evict = bp->type != ttm_bo_type_kernel,
524 struct amdgpu_bo *bo;
525 unsigned long page_align, size = bp->size;
529 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
530 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
531 /* GWS and OA don't need any alignment. */
532 page_align = bp->byte_align;
534 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
535 /* Both size and alignment must be a multiple of 4. */
536 page_align = ALIGN(bp->byte_align, 4);
537 size = ALIGN(size, 4) << PAGE_SHIFT;
539 /* Memory should be aligned at least to a page size. */
540 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
541 size = ALIGN(size, PAGE_SIZE);
544 if (!amdgpu_bo_validate_size(adev, size, bp->domain))
549 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
550 sizeof(struct amdgpu_bo));
552 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
555 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
556 INIT_LIST_HEAD(&bo->shadow_list);
558 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
560 bo->allowed_domains = bo->preferred_domains;
561 if (bp->type != ttm_bo_type_kernel &&
562 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
563 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
565 bo->flags = bp->flags;
567 if (!amdgpu_bo_support_uswc(bo->flags))
568 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
570 bo->tbo.bdev = &adev->mman.bdev;
571 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
572 AMDGPU_GEM_DOMAIN_GDS))
573 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
575 amdgpu_bo_placement_from_domain(bo, bp->domain);
576 if (bp->type == ttm_bo_type_kernel)
577 bo->tbo.priority = 1;
579 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type,
580 &bo->placement, page_align, &ctx, acc_size,
581 NULL, bp->resv, &amdgpu_bo_destroy);
582 if (unlikely(r != 0))
585 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
586 bo->tbo.mem.mem_type == TTM_PL_VRAM &&
587 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
588 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
591 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
593 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
594 bo->tbo.mem.mem_type == TTM_PL_VRAM) {
595 struct dma_fence *fence;
597 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence);
601 amdgpu_bo_fence(bo, fence, false);
602 dma_fence_put(bo->tbo.moving);
603 bo->tbo.moving = dma_fence_get(fence);
604 dma_fence_put(fence);
607 amdgpu_bo_unreserve(bo);
610 trace_amdgpu_bo_create(bo);
612 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
613 if (bp->type == ttm_bo_type_device)
614 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
620 dma_resv_unlock(bo->tbo.base.resv);
621 amdgpu_bo_unref(&bo);
625 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
627 struct amdgpu_bo *bo)
629 struct amdgpu_bo_param bp;
635 memset(&bp, 0, sizeof(bp));
637 bp.domain = AMDGPU_GEM_DOMAIN_GTT;
638 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC |
639 AMDGPU_GEM_CREATE_SHADOW;
640 bp.type = ttm_bo_type_kernel;
641 bp.resv = bo->tbo.base.resv;
643 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow);
645 bo->shadow->parent = amdgpu_bo_ref(bo);
646 mutex_lock(&adev->shadow_list_lock);
647 list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list);
648 mutex_unlock(&adev->shadow_list_lock);
655 * amdgpu_bo_create - create an &amdgpu_bo buffer object
656 * @adev: amdgpu device object
657 * @bp: parameters to be used for the buffer object
658 * @bo_ptr: pointer to the buffer object pointer
660 * Creates an &amdgpu_bo buffer object; and if requested, also creates a
662 * Shadow object is used to backup the original buffer object, and is always
666 * 0 for success or a negative error code on failure.
668 int amdgpu_bo_create(struct amdgpu_device *adev,
669 struct amdgpu_bo_param *bp,
670 struct amdgpu_bo **bo_ptr)
672 u64 flags = bp->flags;
675 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
676 r = amdgpu_bo_do_create(adev, bp, bo_ptr);
680 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) {
682 WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv,
685 r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr);
688 dma_resv_unlock((*bo_ptr)->tbo.base.resv);
691 amdgpu_bo_unref(bo_ptr);
698 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
699 * @bo: pointer to the buffer object
701 * Sets placement according to domain; and changes placement and caching
702 * policy of the buffer object according to the placement.
703 * This is used for validating shadow bos. It calls ttm_bo_validate() to
704 * make sure the buffer is resident where it needs to be.
707 * 0 for success or a negative error code on failure.
709 int amdgpu_bo_validate(struct amdgpu_bo *bo)
711 struct ttm_operation_ctx ctx = { false, false };
715 if (bo->tbo.pin_count)
718 domain = bo->preferred_domains;
721 amdgpu_bo_placement_from_domain(bo, domain);
722 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
723 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
724 domain = bo->allowed_domains;
732 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow
734 * @shadow: &amdgpu_bo shadow to be restored
735 * @fence: dma_fence associated with the operation
737 * Copies a buffer object's shadow content back to the object.
738 * This is used for recovering a buffer from its shadow in case of a gpu
739 * reset where vram context may be lost.
742 * 0 for success or a negative error code on failure.
744 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence)
747 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev);
748 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
749 uint64_t shadow_addr, parent_addr;
751 shadow_addr = amdgpu_bo_gpu_offset(shadow);
752 parent_addr = amdgpu_bo_gpu_offset(shadow->parent);
754 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr,
755 amdgpu_bo_size(shadow), NULL, fence,
760 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object
761 * @bo: &amdgpu_bo buffer object to be mapped
762 * @ptr: kernel virtual address to be returned
764 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls
765 * amdgpu_bo_kptr() to get the kernel virtual address.
768 * 0 for success or a negative error code on failure.
770 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
775 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
778 kptr = amdgpu_bo_kptr(bo);
785 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false, false,
786 MAX_SCHEDULE_TIMEOUT);
790 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.mem.num_pages, &bo->kmap);
795 *ptr = amdgpu_bo_kptr(bo);
801 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object
802 * @bo: &amdgpu_bo buffer object
804 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address
807 * the virtual address of a buffer object area.
809 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
813 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
817 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object
818 * @bo: &amdgpu_bo buffer object to be unmapped
820 * Unmaps a kernel map set up by amdgpu_bo_kmap().
822 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
825 ttm_bo_kunmap(&bo->kmap);
829 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object
830 * @bo: &amdgpu_bo buffer object
832 * References the contained &ttm_buffer_object.
835 * a refcounted pointer to the &amdgpu_bo buffer object.
837 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
842 ttm_bo_get(&bo->tbo);
847 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object
848 * @bo: &amdgpu_bo buffer object
850 * Unreferences the contained &ttm_buffer_object and clear the pointer
852 void amdgpu_bo_unref(struct amdgpu_bo **bo)
854 struct ttm_buffer_object *tbo;
865 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object
866 * @bo: &amdgpu_bo buffer object to be pinned
867 * @domain: domain to be pinned to
868 * @min_offset: the start of requested address range
869 * @max_offset: the end of requested address range
871 * Pins the buffer object according to requested domain and address range. If
872 * the memory is unbound gart memory, binds the pages into gart table. Adjusts
873 * pin_count and pin_size accordingly.
875 * Pinning means to lock pages in memory along with keeping them at a fixed
876 * offset. It is required when a buffer can not be moved, for example, when
877 * a display buffer is being scanned out.
879 * Compared with amdgpu_bo_pin(), this function gives more flexibility on
880 * where to pin a buffer if there are specific restrictions on where a buffer
884 * 0 for success or a negative error code on failure.
886 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
887 u64 min_offset, u64 max_offset)
889 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
890 struct ttm_operation_ctx ctx = { false, false };
893 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
896 if (WARN_ON_ONCE(min_offset > max_offset))
899 /* A shared bo cannot be migrated to VRAM */
900 if (bo->prime_shared_count || bo->tbo.base.import_attach) {
901 if (domain & AMDGPU_GEM_DOMAIN_GTT)
902 domain = AMDGPU_GEM_DOMAIN_GTT;
907 /* This assumes only APU display buffers are pinned with (VRAM|GTT).
908 * See function amdgpu_display_supported_domains()
910 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain);
912 if (bo->tbo.pin_count) {
913 uint32_t mem_type = bo->tbo.mem.mem_type;
914 uint32_t mem_flags = bo->tbo.mem.placement;
916 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
919 if ((mem_type == TTM_PL_VRAM) &&
920 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) &&
921 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS))
924 ttm_bo_pin(&bo->tbo);
926 if (max_offset != 0) {
927 u64 domain_start = amdgpu_ttm_domain_start(adev,
929 WARN_ON_ONCE(max_offset <
930 (amdgpu_bo_gpu_offset(bo) - domain_start));
936 if (bo->tbo.base.import_attach)
937 dma_buf_pin(bo->tbo.base.import_attach);
939 /* force to pin into visible video ram */
940 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
941 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
942 amdgpu_bo_placement_from_domain(bo, domain);
943 for (i = 0; i < bo->placement.num_placement; i++) {
946 fpfn = min_offset >> PAGE_SHIFT;
947 lpfn = max_offset >> PAGE_SHIFT;
949 if (fpfn > bo->placements[i].fpfn)
950 bo->placements[i].fpfn = fpfn;
951 if (!bo->placements[i].lpfn ||
952 (lpfn && lpfn < bo->placements[i].lpfn))
953 bo->placements[i].lpfn = lpfn;
956 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
958 dev_err(adev->dev, "%p pin failed\n", bo);
962 ttm_bo_pin(&bo->tbo);
964 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
965 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
966 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size);
967 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo),
968 &adev->visible_pin_size);
969 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
970 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size);
978 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object
979 * @bo: &amdgpu_bo buffer object to be pinned
980 * @domain: domain to be pinned to
982 * A simple wrapper to amdgpu_bo_pin_restricted().
983 * Provides a simpler API for buffers that do not have any strict restrictions
984 * on where a buffer must be located.
987 * 0 for success or a negative error code on failure.
989 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)
991 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
992 return amdgpu_bo_pin_restricted(bo, domain, 0, 0);
996 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object
997 * @bo: &amdgpu_bo buffer object to be unpinned
999 * Decreases the pin_count, and clears the flags if pin_count reaches 0.
1000 * Changes placement and pin size accordingly.
1003 * 0 for success or a negative error code on failure.
1005 void amdgpu_bo_unpin(struct amdgpu_bo *bo)
1007 ttm_bo_unpin(&bo->tbo);
1008 if (bo->tbo.pin_count)
1011 amdgpu_bo_subtract_pin_size(bo);
1013 if (bo->tbo.base.import_attach)
1014 dma_buf_unpin(bo->tbo.base.import_attach);
1018 * amdgpu_bo_evict_vram - evict VRAM buffers
1019 * @adev: amdgpu device object
1021 * Evicts all VRAM buffers on the lru list of the memory type.
1022 * Mainly used for evicting vram at suspend time.
1025 * 0 for success or a negative error code on failure.
1027 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
1029 struct ttm_resource_manager *man;
1031 if (adev->in_s3 && (adev->flags & AMD_IS_APU)) {
1032 /* No need to evict vram on APUs for suspend to ram */
1036 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1037 return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
1040 static const char *amdgpu_vram_names[] = {
1055 * amdgpu_bo_init - initialize memory manager
1056 * @adev: amdgpu device object
1058 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager.
1061 * 0 for success or a negative error code on failure.
1063 int amdgpu_bo_init(struct amdgpu_device *adev)
1065 /* reserve PAT memory space to WC for VRAM */
1066 arch_io_reserve_memtype_wc(adev->gmc.aper_base,
1067 adev->gmc.aper_size);
1069 /* Add an MTRR for the VRAM */
1070 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
1071 adev->gmc.aper_size);
1072 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
1073 adev->gmc.mc_vram_size >> 20,
1074 (unsigned long long)adev->gmc.aper_size >> 20);
1075 DRM_INFO("RAM width %dbits %s\n",
1076 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
1077 return amdgpu_ttm_init(adev);
1081 * amdgpu_bo_fini - tear down memory manager
1082 * @adev: amdgpu device object
1084 * Reverses amdgpu_bo_init() to tear down memory manager.
1086 void amdgpu_bo_fini(struct amdgpu_device *adev)
1088 amdgpu_ttm_fini(adev);
1089 arch_phys_wc_del(adev->gmc.vram_mtrr);
1090 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
1094 * amdgpu_bo_fbdev_mmap - mmap fbdev memory
1095 * @bo: &amdgpu_bo buffer object
1096 * @vma: vma as input from the fbdev mmap method
1098 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo.
1101 * 0 for success or a negative error code on failure.
1103 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
1104 struct vm_area_struct *vma)
1106 if (vma->vm_pgoff != 0)
1109 return ttm_bo_mmap_obj(vma, &bo->tbo);
1113 * amdgpu_bo_set_tiling_flags - set tiling flags
1114 * @bo: &amdgpu_bo buffer object
1115 * @tiling_flags: new flags
1117 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or
1118 * kernel driver to set the tiling flags on a buffer.
1121 * 0 for success or a negative error code on failure.
1123 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
1125 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1127 if (adev->family <= AMDGPU_FAMILY_CZ &&
1128 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
1131 bo->tiling_flags = tiling_flags;
1136 * amdgpu_bo_get_tiling_flags - get tiling flags
1137 * @bo: &amdgpu_bo buffer object
1138 * @tiling_flags: returned flags
1140 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to
1141 * set the tiling flags on a buffer.
1143 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
1145 dma_resv_assert_held(bo->tbo.base.resv);
1148 *tiling_flags = bo->tiling_flags;
1152 * amdgpu_bo_set_metadata - set metadata
1153 * @bo: &amdgpu_bo buffer object
1154 * @metadata: new metadata
1155 * @metadata_size: size of the new metadata
1156 * @flags: flags of the new metadata
1158 * Sets buffer object's metadata, its size and flags.
1159 * Used via GEM ioctl.
1162 * 0 for success or a negative error code on failure.
1164 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
1165 uint32_t metadata_size, uint64_t flags)
1169 if (!metadata_size) {
1170 if (bo->metadata_size) {
1171 kfree(bo->metadata);
1172 bo->metadata = NULL;
1173 bo->metadata_size = 0;
1178 if (metadata == NULL)
1181 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
1185 kfree(bo->metadata);
1186 bo->metadata_flags = flags;
1187 bo->metadata = buffer;
1188 bo->metadata_size = metadata_size;
1194 * amdgpu_bo_get_metadata - get metadata
1195 * @bo: &amdgpu_bo buffer object
1196 * @buffer: returned metadata
1197 * @buffer_size: size of the buffer
1198 * @metadata_size: size of the returned metadata
1199 * @flags: flags of the returned metadata
1201 * Gets buffer object's metadata, its size and flags. buffer_size shall not be
1202 * less than metadata_size.
1203 * Used via GEM ioctl.
1206 * 0 for success or a negative error code on failure.
1208 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
1209 size_t buffer_size, uint32_t *metadata_size,
1212 if (!buffer && !metadata_size)
1216 if (buffer_size < bo->metadata_size)
1219 if (bo->metadata_size)
1220 memcpy(buffer, bo->metadata, bo->metadata_size);
1224 *metadata_size = bo->metadata_size;
1226 *flags = bo->metadata_flags;
1232 * amdgpu_bo_move_notify - notification about a memory move
1233 * @bo: pointer to a buffer object
1234 * @evict: if this move is evicting the buffer from the graphics address space
1235 * @new_mem: new information of the bufer object
1237 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
1239 * TTM driver callback which is called when ttm moves a buffer.
1241 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
1243 struct ttm_resource *new_mem)
1245 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1246 struct amdgpu_bo *abo;
1247 struct ttm_resource *old_mem = &bo->mem;
1249 if (!amdgpu_bo_is_amdgpu_bo(bo))
1252 abo = ttm_to_amdgpu_bo(bo);
1253 amdgpu_vm_bo_invalidate(adev, abo, evict);
1255 amdgpu_bo_kunmap(abo);
1257 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach &&
1258 bo->mem.mem_type != TTM_PL_SYSTEM)
1259 dma_buf_move_notify(abo->tbo.base.dma_buf);
1261 /* remember the eviction */
1263 atomic64_inc(&adev->num_evictions);
1265 /* update statistics */
1269 /* move_notify is called before move happens */
1270 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
1274 * amdgpu_bo_release_notify - notification about a BO being released
1275 * @bo: pointer to a buffer object
1277 * Wipes VRAM buffers whose contents should not be leaked before the
1278 * memory is released.
1280 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
1282 struct dma_fence *fence = NULL;
1283 struct amdgpu_bo *abo;
1286 if (!amdgpu_bo_is_amdgpu_bo(bo))
1289 abo = ttm_to_amdgpu_bo(bo);
1292 amdgpu_amdkfd_unreserve_memory_limit(abo);
1294 /* We only remove the fence if the resv has individualized. */
1295 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel
1296 && bo->base.resv != &bo->base._resv);
1297 if (bo->base.resv == &bo->base._resv)
1298 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
1300 if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node ||
1301 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE))
1304 dma_resv_lock(bo->base.resv, NULL);
1306 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence);
1308 amdgpu_bo_fence(abo, fence, false);
1309 dma_fence_put(fence);
1312 dma_resv_unlock(bo->base.resv);
1316 * amdgpu_bo_fault_reserve_notify - notification about a memory fault
1317 * @bo: pointer to a buffer object
1319 * Notifies the driver we are taking a fault on this BO and have reserved it,
1320 * also performs bookkeeping.
1321 * TTM driver callback for dealing with vm faults.
1324 * 0 for success or a negative error code on failure.
1326 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
1328 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1329 struct ttm_operation_ctx ctx = { false, false };
1330 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1331 unsigned long offset, size;
1334 /* Remember that this BO was accessed by the CPU */
1335 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1337 if (bo->mem.mem_type != TTM_PL_VRAM)
1340 size = bo->mem.num_pages << PAGE_SHIFT;
1341 offset = bo->mem.start << PAGE_SHIFT;
1342 if ((offset + size) <= adev->gmc.visible_vram_size)
1345 /* Can't move a pinned BO to visible VRAM */
1346 if (abo->tbo.pin_count > 0)
1347 return VM_FAULT_SIGBUS;
1349 /* hurrah the memory is not visible ! */
1350 atomic64_inc(&adev->num_vram_cpu_page_faults);
1351 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
1352 AMDGPU_GEM_DOMAIN_GTT);
1354 /* Avoid costly evictions; only set GTT as a busy placement */
1355 abo->placement.num_busy_placement = 1;
1356 abo->placement.busy_placement = &abo->placements[1];
1358 r = ttm_bo_validate(bo, &abo->placement, &ctx);
1359 if (unlikely(r == -EBUSY || r == -ERESTARTSYS))
1360 return VM_FAULT_NOPAGE;
1361 else if (unlikely(r))
1362 return VM_FAULT_SIGBUS;
1364 offset = bo->mem.start << PAGE_SHIFT;
1365 /* this should never happen */
1366 if (bo->mem.mem_type == TTM_PL_VRAM &&
1367 (offset + size) > adev->gmc.visible_vram_size)
1368 return VM_FAULT_SIGBUS;
1370 ttm_bo_move_to_lru_tail_unlocked(bo);
1375 * amdgpu_bo_fence - add fence to buffer object
1377 * @bo: buffer object in question
1378 * @fence: fence to add
1379 * @shared: true if fence should be added shared
1382 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1385 struct dma_resv *resv = bo->tbo.base.resv;
1388 dma_resv_add_shared_fence(resv, fence);
1390 dma_resv_add_excl_fence(resv, fence);
1394 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
1396 * @adev: amdgpu device pointer
1397 * @resv: reservation object to sync to
1398 * @sync_mode: synchronization mode
1399 * @owner: fence owner
1400 * @intr: Whether the wait is interruptible
1402 * Extract the fences from the reservation object and waits for them to finish.
1405 * 0 on success, errno otherwise.
1407 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
1408 enum amdgpu_sync_mode sync_mode, void *owner,
1411 struct amdgpu_sync sync;
1414 amdgpu_sync_create(&sync);
1415 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
1416 r = amdgpu_sync_wait(&sync, intr);
1417 amdgpu_sync_free(&sync);
1422 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
1423 * @bo: buffer object to wait for
1424 * @owner: fence owner
1425 * @intr: Whether the wait is interruptible
1427 * Wrapper to wait for fences in a BO.
1429 * 0 on success, errno otherwise.
1431 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
1433 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1435 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
1436 AMDGPU_SYNC_NE_OWNER, owner, intr);
1440 * amdgpu_bo_gpu_offset - return GPU offset of bo
1441 * @bo: amdgpu object for which we query the offset
1443 * Note: object should either be pinned or reserved when calling this
1444 * function, it might be useful to add check for this for debugging.
1447 * current GPU offset of the object.
1449 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1451 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1452 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&
1453 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel);
1454 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1455 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1456 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1458 return amdgpu_bo_gpu_offset_no_check(bo);
1462 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
1463 * @bo: amdgpu object for which we query the offset
1466 * current GPU offset of the object without raising warnings.
1468 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
1470 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1473 offset = (bo->tbo.mem.start << PAGE_SHIFT) +
1474 amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type);
1476 return amdgpu_gmc_sign_extend(offset);
1480 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout
1481 * @adev: amdgpu device object
1482 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>`
1485 * Which of the allowed domains is preferred for pinning the BO for scanout.
1487 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
1490 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
1491 domain = AMDGPU_GEM_DOMAIN_VRAM;
1492 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
1493 domain = AMDGPU_GEM_DOMAIN_GTT;
1498 #if defined(CONFIG_DEBUG_FS)
1499 #define amdgpu_bo_print_flag(m, bo, flag) \
1501 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
1502 seq_printf((m), " " #flag); \
1507 * amdgpu_bo_print_info - print BO info in debugfs file
1509 * @id: Index or Id of the BO
1510 * @bo: Requested BO for printing info
1513 * Print BO information in debugfs file
1516 * Size of the BO in bytes.
1518 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
1520 struct dma_buf_attachment *attachment;
1521 struct dma_buf *dma_buf;
1522 unsigned int domain;
1523 const char *placement;
1524 unsigned int pin_count;
1527 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
1529 case AMDGPU_GEM_DOMAIN_VRAM:
1532 case AMDGPU_GEM_DOMAIN_GTT:
1535 case AMDGPU_GEM_DOMAIN_CPU:
1541 size = amdgpu_bo_size(bo);
1542 seq_printf(m, "\t\t0x%08x: %12lld byte %s",
1543 id, size, placement);
1545 pin_count = READ_ONCE(bo->tbo.pin_count);
1547 seq_printf(m, " pin count %d", pin_count);
1549 dma_buf = READ_ONCE(bo->tbo.base.dma_buf);
1550 attachment = READ_ONCE(bo->tbo.base.import_attach);
1553 seq_printf(m, " imported from %p", dma_buf);
1555 seq_printf(m, " exported as %p", dma_buf);
1557 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
1558 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS);
1559 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC);
1560 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED);
1561 amdgpu_bo_print_flag(m, bo, SHADOW);
1562 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
1563 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);
1564 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);