drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_drv.h>
  32 #include <drm/drm_fb_helper.h>
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "atom.h"
  36
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/slab.h>
  39 #include <linux/uaccess.h>
  40 #include <linux/pci.h>
  41 #include <linux/pm_runtime.h>
  42 #include "amdgpu_amdkfd.h"
  43 #include "amdgpu_gem.h"
  44 #include "amdgpu_display.h"
  45 #include "amdgpu_ras.h"
  46 #include "amd_pcie.h"
  47
  48 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  49 {
  50         struct amdgpu_gpu_instance *gpu_instance;
  51         int i;
  52
  53         mutex_lock(&mgpu_info.mutex);
  54
  55         for (i = 0; i < mgpu_info.num_gpu; i++) {
  56                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  57                 if (gpu_instance->adev == adev) {
  58                         mgpu_info.gpu_ins[i] =
  59                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  60                         mgpu_info.num_gpu--;
  61                         if (adev->flags & AMD_IS_APU)
  62                                 mgpu_info.num_apu--;
  63                         else
  64                                 mgpu_info.num_dgpu--;
  65                         break;
  66                 }
  67         }
  68
  69         mutex_unlock(&mgpu_info.mutex);
  70 }
  71
  72 /**
  73  * amdgpu_driver_unload_kms - Main unload function for KMS.
  74  *
  75  * @dev: drm dev pointer
  76  *
  77  * This is the main unload function for KMS (all asics).
  78  * Returns 0 on success.
  79  */
  80 void amdgpu_driver_unload_kms(struct drm_device *dev)
  81 {
  82         struct amdgpu_device *adev = drm_to_adev(dev);
  83
  84         if (adev == NULL)
  85                 return;
  86
  87         amdgpu_unregister_gpu_instance(adev);
  88
  89         if (adev->rmmio == NULL)
  90                 return;
  91
  92         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
  93                 DRM_WARN("smart shift update failed\n");
  94
  95         amdgpu_acpi_fini(adev);
  96         amdgpu_device_fini_hw(adev);
  97 }
  98
  99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 100 {
 101         struct amdgpu_gpu_instance *gpu_instance;
 102
 103         mutex_lock(&mgpu_info.mutex);
 104
 105         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 106                 DRM_ERROR("Cannot register more gpu instance\n");
 107                 mutex_unlock(&mgpu_info.mutex);
 108                 return;
 109         }
 110
 111         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 112         gpu_instance->adev = adev;
 113         gpu_instance->mgpu_fan_enabled = 0;
 114
 115         mgpu_info.num_gpu++;
 116         if (adev->flags & AMD_IS_APU)
 117                 mgpu_info.num_apu++;
 118         else
 119                 mgpu_info.num_dgpu++;
 120
 121         mutex_unlock(&mgpu_info.mutex);
 122 }
 123
 124 /**
 125  * amdgpu_driver_load_kms - Main load function for KMS.
 126  *
 127  * @adev: pointer to struct amdgpu_device
 128  * @flags: device flags
 129  *
 130  * This is the main load function for KMS (all asics).
 131  * Returns 0 on success, error on failure.
 132  */
 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 134 {
 135         struct drm_device *dev;
 136         int r, acpi_status;
 137
 138         dev = adev_to_drm(adev);
 139
 140         /* amdgpu_device_init should report only fatal error
 141          * like memory allocation failure or iomapping failure,
 142          * or memory manager initialization failure, it must
 143          * properly initialize the GPU MC controller and permit
 144          * VRAM allocation
 145          */
 146         r = amdgpu_device_init(adev, flags);
 147         if (r) {
 148                 dev_err(dev->dev, "Fatal error during GPU init\n");
 149                 goto out;
 150         }
 151
 152         adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
 153         if (amdgpu_device_supports_px(dev) &&
 154             (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */
 155                 adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
 156                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 157         } else if (amdgpu_device_supports_boco(dev) &&
 158                    (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */
 159                 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
 160                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 161         } else if (amdgpu_device_supports_baco(dev) &&
 162                    (amdgpu_runtime_pm != 0)) {
 163                 switch (adev->asic_type) {
 164                 case CHIP_VEGA20:
 165                 case CHIP_ARCTURUS:
 166                         /* enable BACO as runpm mode if runpm=1 */
 167                         if (amdgpu_runtime_pm > 0)
 168                                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 169                         break;
 170                 case CHIP_VEGA10:
 171                         /* enable BACO as runpm mode if noretry=0 */
 172                         if (!adev->gmc.noretry)
 173                                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 174                         break;
 175                 default:
 176                         /* enable BACO as runpm mode on CI+ */
 177                         adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 178                         break;
 179                 }
 180
 181                 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)
 182                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 183         }
 184
 185         /* Call ACPI methods: require modeset init
 186          * but failure is not fatal
 187          */
 188
 189         acpi_status = amdgpu_acpi_init(adev);
 190         if (acpi_status)
 191                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 192
 193         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
 194                 DRM_WARN("smart shift update failed\n");
 195
 196 out:
 197         if (r)
 198                 amdgpu_driver_unload_kms(dev);
 199
 200         return r;
 201 }
 202
 203 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 204                                 struct drm_amdgpu_query_fw *query_fw,
 205                                 struct amdgpu_device *adev)
 206 {
 207         switch (query_fw->fw_type) {
 208         case AMDGPU_INFO_FW_VCE:
 209                 fw_info->ver = adev->vce.fw_version;
 210                 fw_info->feature = adev->vce.fb_version;
 211                 break;
 212         case AMDGPU_INFO_FW_UVD:
 213                 fw_info->ver = adev->uvd.fw_version;
 214                 fw_info->feature = 0;
 215                 break;
 216         case AMDGPU_INFO_FW_VCN:
 217                 fw_info->ver = adev->vcn.fw_version;
 218                 fw_info->feature = 0;
 219                 break;
 220         case AMDGPU_INFO_FW_GMC:
 221                 fw_info->ver = adev->gmc.fw_version;
 222                 fw_info->feature = 0;
 223                 break;
 224         case AMDGPU_INFO_FW_GFX_ME:
 225                 fw_info->ver = adev->gfx.me_fw_version;
 226                 fw_info->feature = adev->gfx.me_feature_version;
 227                 break;
 228         case AMDGPU_INFO_FW_GFX_PFP:
 229                 fw_info->ver = adev->gfx.pfp_fw_version;
 230                 fw_info->feature = adev->gfx.pfp_feature_version;
 231                 break;
 232         case AMDGPU_INFO_FW_GFX_CE:
 233                 fw_info->ver = adev->gfx.ce_fw_version;
 234                 fw_info->feature = adev->gfx.ce_feature_version;
 235                 break;
 236         case AMDGPU_INFO_FW_GFX_RLC:
 237                 fw_info->ver = adev->gfx.rlc_fw_version;
 238                 fw_info->feature = adev->gfx.rlc_feature_version;
 239                 break;
 240         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 241                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 242                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 243                 break;
 244         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 245                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 246                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 247                 break;
 248         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 249                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 250                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 251                 break;
 252         case AMDGPU_INFO_FW_GFX_RLCP:
 253                 fw_info->ver = adev->gfx.rlcp_ucode_version;
 254                 fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
 255                 break;
 256         case AMDGPU_INFO_FW_GFX_RLCV:
 257                 fw_info->ver = adev->gfx.rlcv_ucode_version;
 258                 fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
 259                 break;
 260         case AMDGPU_INFO_FW_GFX_MEC:
 261                 if (query_fw->index == 0) {
 262                         fw_info->ver = adev->gfx.mec_fw_version;
 263                         fw_info->feature = adev->gfx.mec_feature_version;
 264                 } else if (query_fw->index == 1) {
 265                         fw_info->ver = adev->gfx.mec2_fw_version;
 266                         fw_info->feature = adev->gfx.mec2_feature_version;
 267                 } else
 268                         return -EINVAL;
 269                 break;
 270         case AMDGPU_INFO_FW_SMC:
 271                 fw_info->ver = adev->pm.fw_version;
 272                 fw_info->feature = 0;
 273                 break;
 274         case AMDGPU_INFO_FW_TA:
 275                 switch (query_fw->index) {
 276                 case TA_FW_TYPE_PSP_XGMI:
 277                         fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
 278                         fw_info->feature = adev->psp.xgmi_context.context
 279                                                    .bin_desc.feature_version;
 280                         break;
 281                 case TA_FW_TYPE_PSP_RAS:
 282                         fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
 283                         fw_info->feature = adev->psp.ras_context.context
 284                                                    .bin_desc.feature_version;
 285                         break;
 286                 case TA_FW_TYPE_PSP_HDCP:
 287                         fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
 288                         fw_info->feature = adev->psp.hdcp_context.context
 289                                                    .bin_desc.feature_version;
 290                         break;
 291                 case TA_FW_TYPE_PSP_DTM:
 292                         fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
 293                         fw_info->feature = adev->psp.dtm_context.context
 294                                                    .bin_desc.feature_version;
 295                         break;
 296                 case TA_FW_TYPE_PSP_RAP:
 297                         fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
 298                         fw_info->feature = adev->psp.rap_context.context
 299                                                    .bin_desc.feature_version;
 300                         break;
 301                 case TA_FW_TYPE_PSP_SECUREDISPLAY:
 302                         fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
 303                         fw_info->feature =
 304                                 adev->psp.securedisplay_context.context.bin_desc
 305                                         .feature_version;
 306                         break;
 307                 default:
 308                         return -EINVAL;
 309                 }
 310                 break;
 311         case AMDGPU_INFO_FW_SDMA:
 312                 if (query_fw->index >= adev->sdma.num_instances)
 313                         return -EINVAL;
 314                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 315                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 316                 break;
 317         case AMDGPU_INFO_FW_SOS:
 318                 fw_info->ver = adev->psp.sos.fw_version;
 319                 fw_info->feature = adev->psp.sos.feature_version;
 320                 break;
 321         case AMDGPU_INFO_FW_ASD:
 322                 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
 323                 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
 324                 break;
 325         case AMDGPU_INFO_FW_DMCU:
 326                 fw_info->ver = adev->dm.dmcu_fw_version;
 327                 fw_info->feature = 0;
 328                 break;
 329         case AMDGPU_INFO_FW_DMCUB:
 330                 fw_info->ver = adev->dm.dmcub_fw_version;
 331                 fw_info->feature = 0;
 332                 break;
 333         case AMDGPU_INFO_FW_TOC:
 334                 fw_info->ver = adev->psp.toc.fw_version;
 335                 fw_info->feature = adev->psp.toc.feature_version;
 336                 break;
 337         case AMDGPU_INFO_FW_CAP:
 338                 fw_info->ver = adev->psp.cap_fw_version;
 339                 fw_info->feature = adev->psp.cap_feature_version;
 340                 break;
 341         case AMDGPU_INFO_FW_MES_KIQ:
 342                 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK;
 343                 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK)
 344                                         >> AMDGPU_MES_FEAT_VERSION_SHIFT;
 345                 break;
 346         case AMDGPU_INFO_FW_MES:
 347                 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
 348                 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK)
 349                                         >> AMDGPU_MES_FEAT_VERSION_SHIFT;
 350                 break;
 351         case AMDGPU_INFO_FW_IMU:
 352                 fw_info->ver = adev->gfx.imu_fw_version;
 353                 fw_info->feature = 0;
 354                 break;
 355         default:
 356                 return -EINVAL;
 357         }
 358         return 0;
 359 }
 360
 361 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 362                              struct drm_amdgpu_info *info,
 363                              struct drm_amdgpu_info_hw_ip *result)
 364 {
 365         uint32_t ib_start_alignment = 0;
 366         uint32_t ib_size_alignment = 0;
 367         enum amd_ip_block_type type;
 368         unsigned int num_rings = 0;
 369         unsigned int i, j;
 370
 371         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 372                 return -EINVAL;
 373
 374         switch (info->query_hw_ip.type) {
 375         case AMDGPU_HW_IP_GFX:
 376                 type = AMD_IP_BLOCK_TYPE_GFX;
 377                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 378                         if (adev->gfx.gfx_ring[i].sched.ready)
 379                                 ++num_rings;
 380                 ib_start_alignment = 32;
 381                 ib_size_alignment = 32;
 382                 break;
 383         case AMDGPU_HW_IP_COMPUTE:
 384                 type = AMD_IP_BLOCK_TYPE_GFX;
 385                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 386                         if (adev->gfx.compute_ring[i].sched.ready)
 387                                 ++num_rings;
 388                 ib_start_alignment = 32;
 389                 ib_size_alignment = 32;
 390                 break;
 391         case AMDGPU_HW_IP_DMA:
 392                 type = AMD_IP_BLOCK_TYPE_SDMA;
 393                 for (i = 0; i < adev->sdma.num_instances; i++)
 394                         if (adev->sdma.instance[i].ring.sched.ready)
 395                                 ++num_rings;
 396                 ib_start_alignment = 256;
 397                 ib_size_alignment = 4;
 398                 break;
 399         case AMDGPU_HW_IP_UVD:
 400                 type = AMD_IP_BLOCK_TYPE_UVD;
 401                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 402                         if (adev->uvd.harvest_config & (1 << i))
 403                                 continue;
 404
 405                         if (adev->uvd.inst[i].ring.sched.ready)
 406                                 ++num_rings;
 407                 }
 408                 ib_start_alignment = 64;
 409                 ib_size_alignment = 64;
 410                 break;
 411         case AMDGPU_HW_IP_VCE:
 412                 type = AMD_IP_BLOCK_TYPE_VCE;
 413                 for (i = 0; i < adev->vce.num_rings; i++)
 414                         if (adev->vce.ring[i].sched.ready)
 415                                 ++num_rings;
 416                 ib_start_alignment = 4;
 417                 ib_size_alignment = 1;
 418                 break;
 419         case AMDGPU_HW_IP_UVD_ENC:
 420                 type = AMD_IP_BLOCK_TYPE_UVD;
 421                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 422                         if (adev->uvd.harvest_config & (1 << i))
 423                                 continue;
 424
 425                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 426                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 427                                         ++num_rings;
 428                 }
 429                 ib_start_alignment = 64;
 430                 ib_size_alignment = 64;
 431                 break;
 432         case AMDGPU_HW_IP_VCN_DEC:
 433                 type = AMD_IP_BLOCK_TYPE_VCN;
 434                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 435                         if (adev->vcn.harvest_config & (1 << i))
 436                                 continue;
 437
 438                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 439                                 ++num_rings;
 440                 }
 441                 ib_start_alignment = 16;
 442                 ib_size_alignment = 16;
 443                 break;
 444         case AMDGPU_HW_IP_VCN_ENC:
 445                 type = AMD_IP_BLOCK_TYPE_VCN;
 446                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 447                         if (adev->vcn.harvest_config & (1 << i))
 448                                 continue;
 449
 450                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 451                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 452                                         ++num_rings;
 453                 }
 454                 ib_start_alignment = 64;
 455                 ib_size_alignment = 1;
 456                 break;
 457         case AMDGPU_HW_IP_VCN_JPEG:
 458                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 459                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 460
 461                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 462                         if (adev->jpeg.harvest_config & (1 << i))
 463                                 continue;
 464
 465                         for (j = 0; j < adev->jpeg.num_jpeg_rings; j++)
 466                                 if (adev->jpeg.inst[i].ring_dec[j].sched.ready)
 467                                         ++num_rings;
 468                 }
 469                 ib_start_alignment = 16;
 470                 ib_size_alignment = 16;
 471                 break;
 472         default:
 473                 return -EINVAL;
 474         }
 475
 476         for (i = 0; i < adev->num_ip_blocks; i++)
 477                 if (adev->ip_blocks[i].version->type == type &&
 478                     adev->ip_blocks[i].status.valid)
 479                         break;
 480
 481         if (i == adev->num_ip_blocks)
 482                 return 0;
 483
 484         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 485                         num_rings);
 486
 487         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 488         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 489
 490         if (adev->asic_type >= CHIP_VEGA10) {
 491                 switch (type) {
 492                 case AMD_IP_BLOCK_TYPE_GFX:
 493                         result->ip_discovery_version = adev->ip_versions[GC_HWIP][0];
 494                         break;
 495                 case AMD_IP_BLOCK_TYPE_SDMA:
 496                         result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0];
 497                         break;
 498                 case AMD_IP_BLOCK_TYPE_UVD:
 499                 case AMD_IP_BLOCK_TYPE_VCN:
 500                 case AMD_IP_BLOCK_TYPE_JPEG:
 501                         result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0];
 502                         break;
 503                 case AMD_IP_BLOCK_TYPE_VCE:
 504                         result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0];
 505                         break;
 506                 default:
 507                         result->ip_discovery_version = 0;
 508                         break;
 509                 }
 510         } else {
 511                 result->ip_discovery_version = 0;
 512         }
 513         result->capabilities_flags = 0;
 514         result->available_rings = (1 << num_rings) - 1;
 515         result->ib_start_alignment = ib_start_alignment;
 516         result->ib_size_alignment = ib_size_alignment;
 517         return 0;
 518 }
 519
 520 /*
 521  * Userspace get information ioctl
 522  */
 523 /**
 524  * amdgpu_info_ioctl - answer a device specific request.
 525  *
 526  * @dev: drm device pointer
 527  * @data: request object
 528  * @filp: drm filp
 529  *
 530  * This function is used to pass device specific parameters to the userspace
 531  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 532  * etc. (all asics).
 533  * Returns 0 on success, -EINVAL on failure.
 534  */
 535 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 536 {
 537         struct amdgpu_device *adev = drm_to_adev(dev);
 538         struct drm_amdgpu_info *info = data;
 539         struct amdgpu_mode_info *minfo = &adev->mode_info;
 540         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 541         uint32_t size = info->return_size;
 542         struct drm_crtc *crtc;
 543         uint32_t ui32 = 0;
 544         uint64_t ui64 = 0;
 545         int i, found;
 546         int ui32_size = sizeof(ui32);
 547
 548         if (!info->return_size || !info->return_pointer)
 549                 return -EINVAL;
 550
 551         switch (info->query) {
 552         case AMDGPU_INFO_ACCEL_WORKING:
 553                 ui32 = adev->accel_working;
 554                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 555         case AMDGPU_INFO_CRTC_FROM_ID:
 556                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 557                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 558                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 559                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 560
 561                                 ui32 = amdgpu_crtc->crtc_id;
 562                                 found = 1;
 563                                 break;
 564                         }
 565                 }
 566                 if (!found) {
 567                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 568                         return -EINVAL;
 569                 }
 570                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 571         case AMDGPU_INFO_HW_IP_INFO: {
 572                 struct drm_amdgpu_info_hw_ip ip = {};
 573                 int ret;
 574
 575                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 576                 if (ret)
 577                         return ret;
 578
 579                 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip)));
 580                 return ret ? -EFAULT : 0;
 581         }
 582         case AMDGPU_INFO_HW_IP_COUNT: {
 583                 enum amd_ip_block_type type;
 584                 uint32_t count = 0;
 585
 586                 switch (info->query_hw_ip.type) {
 587                 case AMDGPU_HW_IP_GFX:
 588                         type = AMD_IP_BLOCK_TYPE_GFX;
 589                         break;
 590                 case AMDGPU_HW_IP_COMPUTE:
 591                         type = AMD_IP_BLOCK_TYPE_GFX;
 592                         break;
 593                 case AMDGPU_HW_IP_DMA:
 594                         type = AMD_IP_BLOCK_TYPE_SDMA;
 595                         break;
 596                 case AMDGPU_HW_IP_UVD:
 597                         type = AMD_IP_BLOCK_TYPE_UVD;
 598                         break;
 599                 case AMDGPU_HW_IP_VCE:
 600                         type = AMD_IP_BLOCK_TYPE_VCE;
 601                         break;
 602                 case AMDGPU_HW_IP_UVD_ENC:
 603                         type = AMD_IP_BLOCK_TYPE_UVD;
 604                         break;
 605                 case AMDGPU_HW_IP_VCN_DEC:
 606                 case AMDGPU_HW_IP_VCN_ENC:
 607                         type = AMD_IP_BLOCK_TYPE_VCN;
 608                         break;
 609                 case AMDGPU_HW_IP_VCN_JPEG:
 610                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 611                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 612                         break;
 613                 default:
 614                         return -EINVAL;
 615                 }
 616
 617                 for (i = 0; i < adev->num_ip_blocks; i++)
 618                         if (adev->ip_blocks[i].version->type == type &&
 619                             adev->ip_blocks[i].status.valid &&
 620                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 621                                 count++;
 622
 623                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 624         }
 625         case AMDGPU_INFO_TIMESTAMP:
 626                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 627                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 628         case AMDGPU_INFO_FW_VERSION: {
 629                 struct drm_amdgpu_info_firmware fw_info;
 630                 int ret;
 631
 632                 /* We only support one instance of each IP block right now. */
 633                 if (info->query_fw.ip_instance != 0)
 634                         return -EINVAL;
 635
 636                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 637                 if (ret)
 638                         return ret;
 639
 640                 return copy_to_user(out, &fw_info,
 641                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 642         }
 643         case AMDGPU_INFO_NUM_BYTES_MOVED:
 644                 ui64 = atomic64_read(&adev->num_bytes_moved);
 645                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 646         case AMDGPU_INFO_NUM_EVICTIONS:
 647                 ui64 = atomic64_read(&adev->num_evictions);
 648                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 649         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 650                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 651                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 652         case AMDGPU_INFO_VRAM_USAGE:
 653                 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 654                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 655         case AMDGPU_INFO_VIS_VRAM_USAGE:
 656                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 657                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 658         case AMDGPU_INFO_GTT_USAGE:
 659                 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
 660                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 661         case AMDGPU_INFO_GDS_CONFIG: {
 662                 struct drm_amdgpu_info_gds gds_info;
 663
 664                 memset(&gds_info, 0, sizeof(gds_info));
 665                 gds_info.compute_partition_size = adev->gds.gds_size;
 666                 gds_info.gds_total_size = adev->gds.gds_size;
 667                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 668                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 669                 return copy_to_user(out, &gds_info,
 670                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 671         }
 672         case AMDGPU_INFO_VRAM_GTT: {
 673                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 674
 675                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 676                         atomic64_read(&adev->vram_pin_size) -
 677                         AMDGPU_VM_RESERVED_VRAM;
 678                 vram_gtt.vram_cpu_accessible_size =
 679                         min(adev->gmc.visible_vram_size -
 680                             atomic64_read(&adev->visible_pin_size),
 681                             vram_gtt.vram_size);
 682                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 683                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 684                 return copy_to_user(out, &vram_gtt,
 685                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 686         }
 687         case AMDGPU_INFO_MEMORY: {
 688                 struct drm_amdgpu_memory_info mem;
 689                 struct ttm_resource_manager *gtt_man =
 690                         &adev->mman.gtt_mgr.manager;
 691                 struct ttm_resource_manager *vram_man =
 692                         &adev->mman.vram_mgr.manager;
 693
 694                 memset(&mem, 0, sizeof(mem));
 695                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 696                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 697                         atomic64_read(&adev->vram_pin_size) -
 698                         AMDGPU_VM_RESERVED_VRAM;
 699                 mem.vram.heap_usage =
 700                         ttm_resource_manager_usage(vram_man);
 701                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 702
 703                 mem.cpu_accessible_vram.total_heap_size =
 704                         adev->gmc.visible_vram_size;
 705                 mem.cpu_accessible_vram.usable_heap_size =
 706                         min(adev->gmc.visible_vram_size -
 707                             atomic64_read(&adev->visible_pin_size),
 708                             mem.vram.usable_heap_size);
 709                 mem.cpu_accessible_vram.heap_usage =
 710                         amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 711                 mem.cpu_accessible_vram.max_allocation =
 712                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 713
 714                 mem.gtt.total_heap_size = gtt_man->size;
 715                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 716                         atomic64_read(&adev->gart_pin_size);
 717                 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
 718                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 719
 720                 return copy_to_user(out, &mem,
 721                                     min((size_t)size, sizeof(mem)))
 722                                     ? -EFAULT : 0;
 723         }
 724         case AMDGPU_INFO_READ_MMR_REG: {
 725                 unsigned int n, alloc_size;
 726                 uint32_t *regs;
 727                 unsigned int se_num = (info->read_mmr_reg.instance >>
 728                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 729                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 730                 unsigned int sh_num = (info->read_mmr_reg.instance >>
 731                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 732                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 733
 734                 /* set full masks if the userspace set all bits
 735                  * in the bitfields
 736                  */
 737                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 738                         se_num = 0xffffffff;
 739                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 740                         return -EINVAL;
 741                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 742                         sh_num = 0xffffffff;
 743                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 744                         return -EINVAL;
 745
 746                 if (info->read_mmr_reg.count > 128)
 747                         return -EINVAL;
 748
 749                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 750                 if (!regs)
 751                         return -ENOMEM;
 752                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 753
 754                 amdgpu_gfx_off_ctrl(adev, false);
 755                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 756                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 757                                                       info->read_mmr_reg.dword_offset + i,
 758                                                       &regs[i])) {
 759                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 760                                               info->read_mmr_reg.dword_offset + i);
 761                                 kfree(regs);
 762                                 amdgpu_gfx_off_ctrl(adev, true);
 763                                 return -EFAULT;
 764                         }
 765                 }
 766                 amdgpu_gfx_off_ctrl(adev, true);
 767                 n = copy_to_user(out, regs, min(size, alloc_size));
 768                 kfree(regs);
 769                 return n ? -EFAULT : 0;
 770         }
 771         case AMDGPU_INFO_DEV_INFO: {
 772                 struct drm_amdgpu_info_device *dev_info;
 773                 uint64_t vm_size;
 774                 uint32_t pcie_gen_mask;
 775                 int ret;
 776
 777                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 778                 if (!dev_info)
 779                         return -ENOMEM;
 780
 781                 dev_info->device_id = adev->pdev->device;
 782                 dev_info->chip_rev = adev->rev_id;
 783                 dev_info->external_rev = adev->external_rev_id;
 784                 dev_info->pci_rev = adev->pdev->revision;
 785                 dev_info->family = adev->family;
 786                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 787                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 788                 /* return all clocks in KHz */
 789                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 790                 if (adev->pm.dpm_enabled) {
 791                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 792                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 793                         dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;
 794                         dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;
 795                 } else {
 796                         dev_info->max_engine_clock =
 797                                 dev_info->min_engine_clock =
 798                                         adev->clock.default_sclk * 10;
 799                         dev_info->max_memory_clock =
 800                                 dev_info->min_memory_clock =
 801                                         adev->clock.default_mclk * 10;
 802                 }
 803                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 804                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 805                         adev->gfx.config.max_shader_engines;
 806                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 807                 dev_info->ids_flags = 0;
 808                 if (adev->flags & AMD_IS_APU)
 809                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 810                 if (adev->gfx.mcbp)
 811                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 812                 if (amdgpu_is_tmz(adev))
 813                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 814                 if (adev->gfx.config.ta_cntl2_truncate_coord_mode)
 815                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD;
 816
 817                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 818                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 819
 820                 /* Older VCE FW versions are buggy and can handle only 40bits */
 821                 if (adev->vce.fw_version &&
 822                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 823                         vm_size = min(vm_size, 1ULL << 40);
 824
 825                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 826                 dev_info->virtual_address_max =
 827                         min(vm_size, AMDGPU_GMC_HOLE_START);
 828
 829                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 830                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 831                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 832                 }
 833                 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 834                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 835                 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 836                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 837                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 838                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 839                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 840                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 841                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 842                        sizeof(dev_info->cu_bitmap));
 843                 dev_info->vram_type = adev->gmc.vram_type;
 844                 dev_info->vram_bit_width = adev->gmc.vram_width;
 845                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 846                 dev_info->gc_double_offchip_lds_buf =
 847                         adev->gfx.config.double_offchip_lds_buf;
 848                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 849                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 850                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 851                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 852                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 853                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 854                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 855
 856                 if (adev->family >= AMDGPU_FAMILY_NV)
 857                         dev_info->pa_sc_tile_steering_override =
 858                                 adev->gfx.config.pa_sc_tile_steering_override;
 859
 860                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 861
 862                 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */
 863                 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16);
 864                 dev_info->pcie_gen = fls(pcie_gen_mask);
 865                 dev_info->pcie_num_lanes =
 866                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :
 867                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :
 868                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :
 869                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :
 870                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :
 871                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;
 872
 873                 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;
 874                 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;
 875                 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
 876                 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
 877                 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *
 878                                             adev->gfx.config.gc_gl1c_per_sa;
 879                 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;
 880                 dev_info->mall_size = adev->gmc.mall_size;
 881
 882
 883                 if (adev->gfx.funcs->get_gfx_shadow_info) {
 884                         struct amdgpu_gfx_shadow_info shadow_info;
 885
 886                         ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info);
 887                         if (!ret) {
 888                                 dev_info->shadow_size = shadow_info.shadow_size;
 889                                 dev_info->shadow_alignment = shadow_info.shadow_alignment;
 890                                 dev_info->csa_size = shadow_info.csa_size;
 891                                 dev_info->csa_alignment = shadow_info.csa_alignment;
 892                         }
 893                 }
 894
 895                 ret = copy_to_user(out, dev_info,
 896                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 897                 kfree(dev_info);
 898                 return ret;
 899         }
 900         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 901                 unsigned int i;
 902                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 903                 struct amd_vce_state *vce_state;
 904
 905                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 906                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 907                         if (vce_state) {
 908                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 909                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 910                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 911                                 vce_clk_table.num_valid_entries++;
 912                         }
 913                 }
 914
 915                 return copy_to_user(out, &vce_clk_table,
 916                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 917         }
 918         case AMDGPU_INFO_VBIOS: {
 919                 uint32_t bios_size = adev->bios_size;
 920
 921                 switch (info->vbios_info.type) {
 922                 case AMDGPU_INFO_VBIOS_SIZE:
 923                         return copy_to_user(out, &bios_size,
 924                                         min((size_t)size, sizeof(bios_size)))
 925                                         ? -EFAULT : 0;
 926                 case AMDGPU_INFO_VBIOS_IMAGE: {
 927                         uint8_t *bios;
 928                         uint32_t bios_offset = info->vbios_info.offset;
 929
 930                         if (bios_offset >= bios_size)
 931                                 return -EINVAL;
 932
 933                         bios = adev->bios + bios_offset;
 934                         return copy_to_user(out, bios,
 935                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 936                                         ? -EFAULT : 0;
 937                 }
 938                 case AMDGPU_INFO_VBIOS_INFO: {
 939                         struct drm_amdgpu_info_vbios vbios_info = {};
 940                         struct atom_context *atom_context;
 941
 942                         atom_context = adev->mode_info.atom_context;
 943                         if (atom_context) {
 944                                 memcpy(vbios_info.name, atom_context->name,
 945                                        sizeof(atom_context->name));
 946                                 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn,
 947                                        sizeof(atom_context->vbios_pn));
 948                                 vbios_info.version = atom_context->version;
 949                                 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
 950                                        sizeof(atom_context->vbios_ver_str));
 951                                 memcpy(vbios_info.date, atom_context->date,
 952                                        sizeof(atom_context->date));
 953                         }
 954
 955                         return copy_to_user(out, &vbios_info,
 956                                                 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
 957                 }
 958                 default:
 959                         DRM_DEBUG_KMS("Invalid request %d\n",
 960                                         info->vbios_info.type);
 961                         return -EINVAL;
 962                 }
 963         }
 964         case AMDGPU_INFO_NUM_HANDLES: {
 965                 struct drm_amdgpu_info_num_handles handle;
 966
 967                 switch (info->query_hw_ip.type) {
 968                 case AMDGPU_HW_IP_UVD:
 969                         /* Starting Polaris, we support unlimited UVD handles */
 970                         if (adev->asic_type < CHIP_POLARIS10) {
 971                                 handle.uvd_max_handles = adev->uvd.max_handles;
 972                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 973
 974                                 return copy_to_user(out, &handle,
 975                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 976                         } else {
 977                                 return -ENODATA;
 978                         }
 979
 980                         break;
 981                 default:
 982                         return -EINVAL;
 983                 }
 984         }
 985         case AMDGPU_INFO_SENSOR: {
 986                 if (!adev->pm.dpm_enabled)
 987                         return -ENOENT;
 988
 989                 switch (info->sensor_info.type) {
 990                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 991                         /* get sclk in Mhz */
 992                         if (amdgpu_dpm_read_sensor(adev,
 993                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 994                                                    (void *)&ui32, &ui32_size)) {
 995                                 return -EINVAL;
 996                         }
 997                         ui32 /= 100;
 998                         break;
 999                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
1000                         /* get mclk in Mhz */
1001                         if (amdgpu_dpm_read_sensor(adev,
1002                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
1003                                                    (void *)&ui32, &ui32_size)) {
1004                                 return -EINVAL;
1005                         }
1006                         ui32 /= 100;
1007                         break;
1008                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
1009                         /* get temperature in millidegrees C */
1010                         if (amdgpu_dpm_read_sensor(adev,
1011                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
1012                                                    (void *)&ui32, &ui32_size)) {
1013                                 return -EINVAL;
1014                         }
1015                         break;
1016                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
1017                         /* get GPU load */
1018                         if (amdgpu_dpm_read_sensor(adev,
1019                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
1020                                                    (void *)&ui32, &ui32_size)) {
1021                                 return -EINVAL;
1022                         }
1023                         break;
1024                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
1025                         /* get average GPU power */
1026                         if (amdgpu_dpm_read_sensor(adev,
1027                                                    AMDGPU_PP_SENSOR_GPU_AVG_POWER,
1028                                                    (void *)&ui32, &ui32_size)) {
1029                                 return -EINVAL;
1030                         }
1031                         ui32 >>= 8;
1032                         break;
1033                 case AMDGPU_INFO_SENSOR_VDDNB:
1034                         /* get VDDNB in millivolts */
1035                         if (amdgpu_dpm_read_sensor(adev,
1036                                                    AMDGPU_PP_SENSOR_VDDNB,
1037                                                    (void *)&ui32, &ui32_size)) {
1038                                 return -EINVAL;
1039                         }
1040                         break;
1041                 case AMDGPU_INFO_SENSOR_VDDGFX:
1042                         /* get VDDGFX in millivolts */
1043                         if (amdgpu_dpm_read_sensor(adev,
1044                                                    AMDGPU_PP_SENSOR_VDDGFX,
1045                                                    (void *)&ui32, &ui32_size)) {
1046                                 return -EINVAL;
1047                         }
1048                         break;
1049                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1050                         /* get stable pstate sclk in Mhz */
1051                         if (amdgpu_dpm_read_sensor(adev,
1052                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1053                                                    (void *)&ui32, &ui32_size)) {
1054                                 return -EINVAL;
1055                         }
1056                         ui32 /= 100;
1057                         break;
1058                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1059                         /* get stable pstate mclk in Mhz */
1060                         if (amdgpu_dpm_read_sensor(adev,
1061                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1062                                                    (void *)&ui32, &ui32_size)) {
1063                                 return -EINVAL;
1064                         }
1065                         ui32 /= 100;
1066                         break;
1067                 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK:
1068                         /* get peak pstate sclk in Mhz */
1069                         if (amdgpu_dpm_read_sensor(adev,
1070                                                    AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
1071                                                    (void *)&ui32, &ui32_size)) {
1072                                 return -EINVAL;
1073                         }
1074                         ui32 /= 100;
1075                         break;
1076                 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK:
1077                         /* get peak pstate mclk in Mhz */
1078                         if (amdgpu_dpm_read_sensor(adev,
1079                                                    AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
1080                                                    (void *)&ui32, &ui32_size)) {
1081                                 return -EINVAL;
1082                         }
1083                         ui32 /= 100;
1084                         break;
1085                 default:
1086                         DRM_DEBUG_KMS("Invalid request %d\n",
1087                                       info->sensor_info.type);
1088                         return -EINVAL;
1089                 }
1090                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1091         }
1092         case AMDGPU_INFO_VRAM_LOST_COUNTER:
1093                 ui32 = atomic_read(&adev->vram_lost_counter);
1094                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1095         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1096                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1097                 uint64_t ras_mask;
1098
1099                 if (!ras)
1100                         return -EINVAL;
1101                 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1102
1103                 return copy_to_user(out, &ras_mask,
1104                                 min_t(u64, size, sizeof(ras_mask))) ?
1105                         -EFAULT : 0;
1106         }
1107         case AMDGPU_INFO_VIDEO_CAPS: {
1108                 const struct amdgpu_video_codecs *codecs;
1109                 struct drm_amdgpu_info_video_caps *caps;
1110                 int r;
1111
1112                 if (!adev->asic_funcs->query_video_codecs)
1113                         return -EINVAL;
1114
1115                 switch (info->video_cap.type) {
1116                 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1117                         r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1118                         if (r)
1119                                 return -EINVAL;
1120                         break;
1121                 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1122                         r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1123                         if (r)
1124                                 return -EINVAL;
1125                         break;
1126                 default:
1127                         DRM_DEBUG_KMS("Invalid request %d\n",
1128                                       info->video_cap.type);
1129                         return -EINVAL;
1130                 }
1131
1132                 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1133                 if (!caps)
1134                         return -ENOMEM;
1135
1136                 for (i = 0; i < codecs->codec_count; i++) {
1137                         int idx = codecs->codec_array[i].codec_type;
1138
1139                         switch (idx) {
1140                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1141                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1142                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1143                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1144                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1145                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1146                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1147                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1148                                 caps->codec_info[idx].valid = 1;
1149                                 caps->codec_info[idx].max_width =
1150                                         codecs->codec_array[i].max_width;
1151                                 caps->codec_info[idx].max_height =
1152                                         codecs->codec_array[i].max_height;
1153                                 caps->codec_info[idx].max_pixels_per_frame =
1154                                         codecs->codec_array[i].max_pixels_per_frame;
1155                                 caps->codec_info[idx].max_level =
1156                                         codecs->codec_array[i].max_level;
1157                                 break;
1158                         default:
1159                                 break;
1160                         }
1161                 }
1162                 r = copy_to_user(out, caps,
1163                                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1164                 kfree(caps);
1165                 return r;
1166         }
1167         case AMDGPU_INFO_MAX_IBS: {
1168                 uint32_t max_ibs[AMDGPU_HW_IP_NUM];
1169
1170                 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
1171                         max_ibs[i] = amdgpu_ring_max_ibs(i);
1172
1173                 return copy_to_user(out, max_ibs,
1174                                     min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0;
1175         }
1176         default:
1177                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1178                 return -EINVAL;
1179         }
1180         return 0;
1181 }
1182
1183
1184 /*
1185  * Outdated mess for old drm with Xorg being in charge (void function now).
1186  */
1187 /**
1188  * amdgpu_driver_lastclose_kms - drm callback for last close
1189  *
1190  * @dev: drm dev pointer
1191  *
1192  * Switch vga_switcheroo state after last close (all asics).
1193  */
1194 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1195 {
1196         drm_fb_helper_lastclose(dev);
1197         vga_switcheroo_process_delayed_switch();
1198 }
1199
1200 /**
1201  * amdgpu_driver_open_kms - drm callback for open
1202  *
1203  * @dev: drm dev pointer
1204  * @file_priv: drm file
1205  *
1206  * On device open, init vm on cayman+ (all asics).
1207  * Returns 0 on success, error on failure.
1208  */
1209 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1210 {
1211         struct amdgpu_device *adev = drm_to_adev(dev);
1212         struct amdgpu_fpriv *fpriv;
1213         int r, pasid;
1214
1215         /* Ensure IB tests are run on ring */
1216         flush_delayed_work(&adev->delayed_init_work);
1217
1218
1219         if (amdgpu_ras_intr_triggered()) {
1220                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1221                 return -EHWPOISON;
1222         }
1223
1224         file_priv->driver_priv = NULL;
1225
1226         r = pm_runtime_get_sync(dev->dev);
1227         if (r < 0)
1228                 goto pm_put;
1229
1230         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1231         if (unlikely(!fpriv)) {
1232                 r = -ENOMEM;
1233                 goto out_suspend;
1234         }
1235
1236         pasid = amdgpu_pasid_alloc(16);
1237         if (pasid < 0) {
1238                 dev_warn(adev->dev, "No more PASIDs available!");
1239                 pasid = 0;
1240         }
1241
1242         r = amdgpu_xcp_open_device(adev, fpriv, file_priv);
1243         if (r)
1244                 goto error_pasid;
1245
1246         r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id);
1247         if (r)
1248                 goto error_pasid;
1249
1250         r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1251         if (r)
1252                 goto error_vm;
1253
1254         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1255         if (!fpriv->prt_va) {
1256                 r = -ENOMEM;
1257                 goto error_vm;
1258         }
1259
1260         if (adev->gfx.mcbp) {
1261                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1262
1263                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1264                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1265                 if (r)
1266                         goto error_vm;
1267         }
1268
1269         mutex_init(&fpriv->bo_list_lock);
1270         idr_init_base(&fpriv->bo_list_handles, 1);
1271
1272         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1273
1274         file_priv->driver_priv = fpriv;
1275         goto out_suspend;
1276
1277 error_vm:
1278         amdgpu_vm_fini(adev, &fpriv->vm);
1279
1280 error_pasid:
1281         if (pasid) {
1282                 amdgpu_pasid_free(pasid);
1283                 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1284         }
1285
1286         kfree(fpriv);
1287
1288 out_suspend:
1289         pm_runtime_mark_last_busy(dev->dev);
1290 pm_put:
1291         pm_runtime_put_autosuspend(dev->dev);
1292
1293         return r;
1294 }
1295
1296 /**
1297  * amdgpu_driver_postclose_kms - drm callback for post close
1298  *
1299  * @dev: drm dev pointer
1300  * @file_priv: drm file
1301  *
1302  * On device post close, tear down vm on cayman+ (all asics).
1303  */
1304 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1305                                  struct drm_file *file_priv)
1306 {
1307         struct amdgpu_device *adev = drm_to_adev(dev);
1308         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1309         struct amdgpu_bo_list *list;
1310         struct amdgpu_bo *pd;
1311         u32 pasid;
1312         int handle;
1313
1314         if (!fpriv)
1315                 return;
1316
1317         pm_runtime_get_sync(dev->dev);
1318
1319         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1320                 amdgpu_uvd_free_handles(adev, file_priv);
1321         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1322                 amdgpu_vce_free_handles(adev, file_priv);
1323
1324         if (fpriv->csa_va) {
1325                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1326
1327                 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1328                                                 fpriv->csa_va, csa_addr));
1329                 fpriv->csa_va = NULL;
1330         }
1331
1332         pasid = fpriv->vm.pasid;
1333         pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1334         if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1335                 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1336                 amdgpu_bo_unreserve(pd);
1337         }
1338
1339         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1340         amdgpu_vm_fini(adev, &fpriv->vm);
1341
1342         if (pasid)
1343                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1344         amdgpu_bo_unref(&pd);
1345
1346         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1347                 amdgpu_bo_list_put(list);
1348
1349         idr_destroy(&fpriv->bo_list_handles);
1350         mutex_destroy(&fpriv->bo_list_lock);
1351
1352         kfree(fpriv);
1353         file_priv->driver_priv = NULL;
1354
1355         pm_runtime_mark_last_busy(dev->dev);
1356         pm_runtime_put_autosuspend(dev->dev);
1357 }
1358
1359
1360 void amdgpu_driver_release_kms(struct drm_device *dev)
1361 {
1362         struct amdgpu_device *adev = drm_to_adev(dev);
1363
1364         amdgpu_device_fini_sw(adev);
1365         pci_set_drvdata(adev->pdev, NULL);
1366 }
1367
1368 /*
1369  * VBlank related functions.
1370  */
1371 /**
1372  * amdgpu_get_vblank_counter_kms - get frame count
1373  *
1374  * @crtc: crtc to get the frame count from
1375  *
1376  * Gets the frame count on the requested crtc (all asics).
1377  * Returns frame count on success, -EINVAL on failure.
1378  */
1379 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1380 {
1381         struct drm_device *dev = crtc->dev;
1382         unsigned int pipe = crtc->index;
1383         struct amdgpu_device *adev = drm_to_adev(dev);
1384         int vpos, hpos, stat;
1385         u32 count;
1386
1387         if (pipe >= adev->mode_info.num_crtc) {
1388                 DRM_ERROR("Invalid crtc %u\n", pipe);
1389                 return -EINVAL;
1390         }
1391
1392         /* The hw increments its frame counter at start of vsync, not at start
1393          * of vblank, as is required by DRM core vblank counter handling.
1394          * Cook the hw count here to make it appear to the caller as if it
1395          * incremented at start of vblank. We measure distance to start of
1396          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1397          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1398          * result by 1 to give the proper appearance to caller.
1399          */
1400         if (adev->mode_info.crtcs[pipe]) {
1401                 /* Repeat readout if needed to provide stable result if
1402                  * we cross start of vsync during the queries.
1403                  */
1404                 do {
1405                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1406                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1407                          * vpos as distance to start of vblank, instead of
1408                          * regular vertical scanout pos.
1409                          */
1410                         stat = amdgpu_display_get_crtc_scanoutpos(
1411                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1412                                 &vpos, &hpos, NULL, NULL,
1413                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1414                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1415
1416                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1417                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1418                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1419                 } else {
1420                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1421                                       pipe, vpos);
1422
1423                         /* Bump counter if we are at >= leading edge of vblank,
1424                          * but before vsync where vpos would turn negative and
1425                          * the hw counter really increments.
1426                          */
1427                         if (vpos >= 0)
1428                                 count++;
1429                 }
1430         } else {
1431                 /* Fallback to use value as is. */
1432                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1433                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1434         }
1435
1436         return count;
1437 }
1438
1439 /**
1440  * amdgpu_enable_vblank_kms - enable vblank interrupt
1441  *
1442  * @crtc: crtc to enable vblank interrupt for
1443  *
1444  * Enable the interrupt on the requested crtc (all asics).
1445  * Returns 0 on success, -EINVAL on failure.
1446  */
1447 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1448 {
1449         struct drm_device *dev = crtc->dev;
1450         unsigned int pipe = crtc->index;
1451         struct amdgpu_device *adev = drm_to_adev(dev);
1452         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1453
1454         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1455 }
1456
1457 /**
1458  * amdgpu_disable_vblank_kms - disable vblank interrupt
1459  *
1460  * @crtc: crtc to disable vblank interrupt for
1461  *
1462  * Disable the interrupt on the requested crtc (all asics).
1463  */
1464 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1465 {
1466         struct drm_device *dev = crtc->dev;
1467         unsigned int pipe = crtc->index;
1468         struct amdgpu_device *adev = drm_to_adev(dev);
1469         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1470
1471         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1472 }
1473
1474 /*
1475  * Debugfs info
1476  */
1477 #if defined(CONFIG_DEBUG_FS)
1478
1479 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1480 {
1481         struct amdgpu_device *adev = m->private;
1482         struct drm_amdgpu_info_firmware fw_info;
1483         struct drm_amdgpu_query_fw query_fw;
1484         struct atom_context *ctx = adev->mode_info.atom_context;
1485         uint8_t smu_program, smu_major, smu_minor, smu_debug;
1486         int ret, i;
1487
1488         static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1489 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type
1490                 TA_FW_NAME(XGMI),
1491                 TA_FW_NAME(RAS),
1492                 TA_FW_NAME(HDCP),
1493                 TA_FW_NAME(DTM),
1494                 TA_FW_NAME(RAP),
1495                 TA_FW_NAME(SECUREDISPLAY),
1496 #undef TA_FW_NAME
1497         };
1498
1499         /* VCE */
1500         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1501         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1502         if (ret)
1503                 return ret;
1504         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1505                    fw_info.feature, fw_info.ver);
1506
1507         /* UVD */
1508         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1509         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1510         if (ret)
1511                 return ret;
1512         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1513                    fw_info.feature, fw_info.ver);
1514
1515         /* GMC */
1516         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1517         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1518         if (ret)
1519                 return ret;
1520         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1521                    fw_info.feature, fw_info.ver);
1522
1523         /* ME */
1524         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1525         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1526         if (ret)
1527                 return ret;
1528         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1529                    fw_info.feature, fw_info.ver);
1530
1531         /* PFP */
1532         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1533         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1534         if (ret)
1535                 return ret;
1536         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1537                    fw_info.feature, fw_info.ver);
1538
1539         /* CE */
1540         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1541         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1542         if (ret)
1543                 return ret;
1544         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1545                    fw_info.feature, fw_info.ver);
1546
1547         /* RLC */
1548         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1549         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1550         if (ret)
1551                 return ret;
1552         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1553                    fw_info.feature, fw_info.ver);
1554
1555         /* RLC SAVE RESTORE LIST CNTL */
1556         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1557         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1558         if (ret)
1559                 return ret;
1560         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1561                    fw_info.feature, fw_info.ver);
1562
1563         /* RLC SAVE RESTORE LIST GPM MEM */
1564         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1565         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1566         if (ret)
1567                 return ret;
1568         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1569                    fw_info.feature, fw_info.ver);
1570
1571         /* RLC SAVE RESTORE LIST SRM MEM */
1572         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1573         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1574         if (ret)
1575                 return ret;
1576         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1577                    fw_info.feature, fw_info.ver);
1578
1579         /* RLCP */
1580         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
1581         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1582         if (ret)
1583                 return ret;
1584         seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
1585                    fw_info.feature, fw_info.ver);
1586
1587         /* RLCV */
1588         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
1589         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1590         if (ret)
1591                 return ret;
1592         seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
1593                    fw_info.feature, fw_info.ver);
1594
1595         /* MEC */
1596         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1597         query_fw.index = 0;
1598         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1599         if (ret)
1600                 return ret;
1601         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1602                    fw_info.feature, fw_info.ver);
1603
1604         /* MEC2 */
1605         if (adev->gfx.mec2_fw) {
1606                 query_fw.index = 1;
1607                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1608                 if (ret)
1609                         return ret;
1610                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1611                            fw_info.feature, fw_info.ver);
1612         }
1613
1614         /* IMU */
1615         query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1616         query_fw.index = 0;
1617         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1618         if (ret)
1619                 return ret;
1620         seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1621                    fw_info.feature, fw_info.ver);
1622
1623         /* PSP SOS */
1624         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1625         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1626         if (ret)
1627                 return ret;
1628         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1629                    fw_info.feature, fw_info.ver);
1630
1631
1632         /* PSP ASD */
1633         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1634         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1635         if (ret)
1636                 return ret;
1637         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1638                    fw_info.feature, fw_info.ver);
1639
1640         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1641         for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1642                 query_fw.index = i;
1643                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1644                 if (ret)
1645                         continue;
1646
1647                 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1648                            ta_fw_name[i], fw_info.feature, fw_info.ver);
1649         }
1650
1651         /* SMC */
1652         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1653         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1654         if (ret)
1655                 return ret;
1656         smu_program = (fw_info.ver >> 24) & 0xff;
1657         smu_major = (fw_info.ver >> 16) & 0xff;
1658         smu_minor = (fw_info.ver >> 8) & 0xff;
1659         smu_debug = (fw_info.ver >> 0) & 0xff;
1660         seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1661                    fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1662
1663         /* SDMA */
1664         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1665         for (i = 0; i < adev->sdma.num_instances; i++) {
1666                 query_fw.index = i;
1667                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1668                 if (ret)
1669                         return ret;
1670                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1671                            i, fw_info.feature, fw_info.ver);
1672         }
1673
1674         /* VCN */
1675         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1676         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1677         if (ret)
1678                 return ret;
1679         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1680                    fw_info.feature, fw_info.ver);
1681
1682         /* DMCU */
1683         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1684         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1685         if (ret)
1686                 return ret;
1687         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1688                    fw_info.feature, fw_info.ver);
1689
1690         /* DMCUB */
1691         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1692         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1693         if (ret)
1694                 return ret;
1695         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1696                    fw_info.feature, fw_info.ver);
1697
1698         /* TOC */
1699         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1700         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1701         if (ret)
1702                 return ret;
1703         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1704                    fw_info.feature, fw_info.ver);
1705
1706         /* CAP */
1707         if (adev->psp.cap_fw) {
1708                 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1709                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1710                 if (ret)
1711                         return ret;
1712                 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1713                                 fw_info.feature, fw_info.ver);
1714         }
1715
1716         /* MES_KIQ */
1717         query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
1718         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1719         if (ret)
1720                 return ret;
1721         seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
1722                    fw_info.feature, fw_info.ver);
1723
1724         /* MES */
1725         query_fw.fw_type = AMDGPU_INFO_FW_MES;
1726         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1727         if (ret)
1728                 return ret;
1729         seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
1730                    fw_info.feature, fw_info.ver);
1731
1732         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn);
1733
1734         return 0;
1735 }
1736
1737 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1738
1739 #endif
1740
1741 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1742 {
1743 #if defined(CONFIG_DEBUG_FS)
1744         struct drm_minor *minor = adev_to_drm(adev)->primary;
1745         struct dentry *root = minor->debugfs_root;
1746
1747         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1748                             adev, &amdgpu_debugfs_firmware_info_fops);
1749
1750 #endif
1751 }