2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/irq.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/amdgpu_drm.h>
33 #include "amdgpu_ih.h"
35 #include "amdgpu_connectors.h"
36 #include "amdgpu_trace.h"
38 #include <linux/pm_runtime.h>
40 #ifdef CONFIG_DRM_AMD_DC
41 #include "amdgpu_dm_irq.h"
44 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
47 * Handle hotplug events outside the interrupt handler proper.
50 * amdgpu_hotplug_work_func - display hotplug work handler
54 * This is the hot plug event work handler (all asics).
55 * The work gets scheduled from the irq handler if there
56 * was a hot plug interrupt. It walks the connector table
57 * and calls the hotplug handler for each one, then sends
58 * a drm hotplug event to alert userspace.
60 static void amdgpu_hotplug_work_func(struct work_struct *work)
62 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
64 struct drm_device *dev = adev->ddev;
65 struct drm_mode_config *mode_config = &dev->mode_config;
66 struct drm_connector *connector;
68 mutex_lock(&mode_config->mutex);
69 list_for_each_entry(connector, &mode_config->connector_list, head)
70 amdgpu_connector_hotplug(connector);
71 mutex_unlock(&mode_config->mutex);
72 /* Just fire off a uevent and let userspace tell us what to do */
73 drm_helper_hpd_irq_event(dev);
77 * amdgpu_irq_reset_work_func - execute gpu reset
81 * Execute scheduled gpu reset (cayman+).
82 * This function is called when the irq handler
83 * thinks we need a gpu reset.
85 static void amdgpu_irq_reset_work_func(struct work_struct *work)
87 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
90 if (!amdgpu_sriov_vf(adev))
91 amdgpu_device_gpu_recover(adev, NULL, false);
94 /* Disable *all* interrupts */
95 void amdgpu_irq_disable_all(struct amdgpu_device *adev)
97 unsigned long irqflags;
101 spin_lock_irqsave(&adev->irq.lock, irqflags);
102 for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
103 if (!adev->irq.client[i].sources)
106 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
107 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
109 if (!src || !src->funcs->set || !src->num_types)
112 for (k = 0; k < src->num_types; ++k) {
113 atomic_set(&src->enabled_types[k], 0);
114 r = src->funcs->set(adev, src, k,
115 AMDGPU_IRQ_STATE_DISABLE);
117 DRM_ERROR("error disabling interrupt (%d)\n",
122 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
126 * amdgpu_irq_handler - irq handler
128 * @int irq, void *arg: args
130 * This is the irq handler for the amdgpu driver (all asics).
132 irqreturn_t amdgpu_irq_handler(int irq, void *arg)
134 struct drm_device *dev = (struct drm_device *) arg;
135 struct amdgpu_device *adev = dev->dev_private;
138 ret = amdgpu_ih_process(adev);
139 if (ret == IRQ_HANDLED)
140 pm_runtime_mark_last_busy(dev->dev);
145 * amdgpu_msi_ok - asic specific msi checks
147 * @adev: amdgpu device pointer
149 * Handles asic specific MSI checks to determine if
150 * MSIs should be enabled on a particular chip (all asics).
151 * Returns true if MSIs should be enabled, false if MSIs
152 * should not be enabled.
154 static bool amdgpu_msi_ok(struct amdgpu_device *adev)
159 else if (amdgpu_msi == 0)
166 * amdgpu_irq_init - init driver interrupt info
168 * @adev: amdgpu device pointer
170 * Sets up the work irq handlers, vblank init, MSIs, etc. (all asics).
171 * Returns 0 for success, error for failure.
173 int amdgpu_irq_init(struct amdgpu_device *adev)
177 spin_lock_init(&adev->irq.lock);
180 adev->irq.msi_enabled = false;
182 if (amdgpu_msi_ok(adev)) {
183 int ret = pci_enable_msi(adev->pdev);
185 adev->irq.msi_enabled = true;
186 dev_dbg(adev->dev, "amdgpu: using MSI.\n");
190 if (!amdgpu_device_has_dc_support(adev)) {
191 if (!adev->enable_virtual_display)
192 /* Disable vblank irqs aggressively for power-saving */
193 /* XXX: can this be enabled for DC? */
194 adev->ddev->vblank_disable_immediate = true;
196 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
201 INIT_WORK(&adev->hotplug_work,
202 amdgpu_hotplug_work_func);
205 INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
207 adev->irq.installed = true;
208 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
210 adev->irq.installed = false;
211 if (!amdgpu_device_has_dc_support(adev))
212 flush_work(&adev->hotplug_work);
213 cancel_work_sync(&adev->reset_work);
216 adev->ddev->max_vblank_count = 0x00ffffff;
218 DRM_DEBUG("amdgpu: irq initialized.\n");
223 * amdgpu_irq_fini - tear down driver interrupt info
225 * @adev: amdgpu device pointer
227 * Tears down the work irq handlers, vblank handlers, MSIs, etc. (all asics).
229 void amdgpu_irq_fini(struct amdgpu_device *adev)
233 if (adev->irq.installed) {
234 drm_irq_uninstall(adev->ddev);
235 adev->irq.installed = false;
236 if (adev->irq.msi_enabled)
237 pci_disable_msi(adev->pdev);
238 if (!amdgpu_device_has_dc_support(adev))
239 flush_work(&adev->hotplug_work);
240 cancel_work_sync(&adev->reset_work);
243 for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
244 if (!adev->irq.client[i].sources)
247 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
248 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
253 kfree(src->enabled_types);
254 src->enabled_types = NULL;
258 adev->irq.client[i].sources[j] = NULL;
261 kfree(adev->irq.client[i].sources);
262 adev->irq.client[i].sources = NULL;
267 * amdgpu_irq_add_id - register irq source
269 * @adev: amdgpu device pointer
270 * @src_id: source id for this source
271 * @source: irq source
274 int amdgpu_irq_add_id(struct amdgpu_device *adev,
275 unsigned client_id, unsigned src_id,
276 struct amdgpu_irq_src *source)
278 if (client_id >= AMDGPU_IH_CLIENTID_MAX)
281 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
287 if (!adev->irq.client[client_id].sources) {
288 adev->irq.client[client_id].sources =
289 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
290 sizeof(struct amdgpu_irq_src *),
292 if (!adev->irq.client[client_id].sources)
296 if (adev->irq.client[client_id].sources[src_id] != NULL)
299 if (source->num_types && !source->enabled_types) {
302 types = kcalloc(source->num_types, sizeof(atomic_t),
307 source->enabled_types = types;
310 adev->irq.client[client_id].sources[src_id] = source;
315 * amdgpu_irq_dispatch - dispatch irq to IP blocks
317 * @adev: amdgpu device pointer
318 * @entry: interrupt vector
320 * Dispatches the irq to the different IP blocks
322 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
323 struct amdgpu_iv_entry *entry)
325 unsigned client_id = entry->client_id;
326 unsigned src_id = entry->src_id;
327 struct amdgpu_irq_src *src;
330 trace_amdgpu_iv(entry);
332 if (client_id >= AMDGPU_IH_CLIENTID_MAX) {
333 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
337 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
338 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
342 if (adev->irq.virq[src_id]) {
343 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
345 if (!adev->irq.client[client_id].sources) {
346 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
351 src = adev->irq.client[client_id].sources[src_id];
353 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
357 r = src->funcs->process(adev, src, entry);
359 DRM_ERROR("error processing interrupt (%d)\n", r);
364 * amdgpu_irq_update - update hw interrupt state
366 * @adev: amdgpu device pointer
367 * @src: interrupt src you want to enable
368 * @type: type of interrupt you want to update
370 * Updates the interrupt state for a specific src (all asics).
372 int amdgpu_irq_update(struct amdgpu_device *adev,
373 struct amdgpu_irq_src *src, unsigned type)
375 unsigned long irqflags;
376 enum amdgpu_interrupt_state state;
379 spin_lock_irqsave(&adev->irq.lock, irqflags);
381 /* we need to determine after taking the lock, otherwise
382 we might disable just enabled interrupts again */
383 if (amdgpu_irq_enabled(adev, src, type))
384 state = AMDGPU_IRQ_STATE_ENABLE;
386 state = AMDGPU_IRQ_STATE_DISABLE;
388 r = src->funcs->set(adev, src, type, state);
389 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
393 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
397 for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
398 if (!adev->irq.client[i].sources)
401 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
402 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
406 for (k = 0; k < src->num_types; k++)
407 amdgpu_irq_update(adev, src, k);
413 * amdgpu_irq_get - enable interrupt
415 * @adev: amdgpu device pointer
416 * @src: interrupt src you want to enable
417 * @type: type of interrupt you want to enable
419 * Enables the interrupt type for a specific src (all asics).
421 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
424 if (!adev->ddev->irq_enabled)
427 if (type >= src->num_types)
430 if (!src->enabled_types || !src->funcs->set)
433 if (atomic_inc_return(&src->enabled_types[type]) == 1)
434 return amdgpu_irq_update(adev, src, type);
440 * amdgpu_irq_put - disable interrupt
442 * @adev: amdgpu device pointer
443 * @src: interrupt src you want to disable
444 * @type: type of interrupt you want to disable
446 * Disables the interrupt type for a specific src (all asics).
448 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
451 if (!adev->ddev->irq_enabled)
454 if (type >= src->num_types)
457 if (!src->enabled_types || !src->funcs->set)
460 if (atomic_dec_and_test(&src->enabled_types[type]))
461 return amdgpu_irq_update(adev, src, type);
467 * amdgpu_irq_enabled - test if irq is enabled or not
469 * @adev: amdgpu device pointer
470 * @idx: interrupt src you want to test
472 * Tests if the given interrupt source is enabled or not
474 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
477 if (!adev->ddev->irq_enabled)
480 if (type >= src->num_types)
483 if (!src->enabled_types || !src->funcs->set)
486 return !!atomic_read(&src->enabled_types[type]);
490 static void amdgpu_irq_mask(struct irq_data *irqd)
495 static void amdgpu_irq_unmask(struct irq_data *irqd)
500 static struct irq_chip amdgpu_irq_chip = {
502 .irq_mask = amdgpu_irq_mask,
503 .irq_unmask = amdgpu_irq_unmask,
506 static int amdgpu_irqdomain_map(struct irq_domain *d,
507 unsigned int irq, irq_hw_number_t hwirq)
509 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
512 irq_set_chip_and_handler(irq,
513 &amdgpu_irq_chip, handle_simple_irq);
517 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
518 .map = amdgpu_irqdomain_map,
522 * amdgpu_irq_add_domain - create a linear irq domain
524 * @adev: amdgpu device pointer
526 * Create an irq domain for GPU interrupt sources
527 * that may be driven by another driver (e.g., ACP).
529 int amdgpu_irq_add_domain(struct amdgpu_device *adev)
531 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
532 &amdgpu_hw_irqdomain_ops, adev);
533 if (!adev->irq.domain) {
534 DRM_ERROR("GPU irq add domain failed\n");
542 * amdgpu_irq_remove_domain - remove the irq domain
544 * @adev: amdgpu device pointer
546 * Remove the irq domain for GPU interrupt sources
547 * that may be driven by another driver (e.g., ACP).
549 void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
551 if (adev->irq.domain) {
552 irq_domain_remove(adev->irq.domain);
553 adev->irq.domain = NULL;
558 * amdgpu_irq_create_mapping - create a mapping between a domain irq and a
561 * @adev: amdgpu device pointer
562 * @src_id: IH source id
564 * Create a mapping between a domain irq (GPU IH src id) and a Linux irq
565 * Use this for components that generate a GPU interrupt, but are driven
566 * by a different driver (e.g., ACP).
567 * Returns the Linux irq.
569 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
571 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
573 return adev->irq.virq[src_id];