2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef __AMDGPU_GFX_H__
25 #define __AMDGPU_GFX_H__
30 #include "clearstate_defs.h"
31 #include "amdgpu_ring.h"
32 #include "amdgpu_rlc.h"
33 #include "amdgpu_imu.h"
35 #include "amdgpu_ras.h"
36 #include "amdgpu_ring_mux.h"
38 /* GFX current status */
39 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
40 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
41 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
42 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
43 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
45 #define AMDGPU_MAX_GC_INSTANCES 8
47 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
48 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
50 enum amdgpu_gfx_pipe_priority {
51 AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1,
52 AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2
55 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
56 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
58 enum amdgpu_gfx_partition {
59 AMDGPU_SPX_PARTITION_MODE = 0,
60 AMDGPU_DPX_PARTITION_MODE = 1,
61 AMDGPU_TPX_PARTITION_MODE = 2,
62 AMDGPU_QPX_PARTITION_MODE = 3,
63 AMDGPU_CPX_PARTITION_MODE = 4,
64 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE,
68 struct amdgpu_bo *hpd_eop_obj;
70 struct amdgpu_bo *mec_fw_obj;
72 struct amdgpu_bo *mec_fw_data_obj;
73 u64 mec_fw_data_gpu_addr;
77 u32 num_queue_per_pipe;
78 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES];
81 struct amdgpu_mec_bitmap {
82 /* These are the resources for which amdgpu takes ownership */
83 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
86 enum amdgpu_unmap_queues_action {
89 DISABLE_PROCESS_QUEUES,
90 PREEMPT_QUEUES_NO_UNMAP,
93 struct kiq_pm4_funcs {
94 /* Support ASIC-specific kiq pm4 packets*/
95 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
97 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
98 struct amdgpu_ring *ring);
99 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
100 struct amdgpu_ring *ring,
101 enum amdgpu_unmap_queues_action action,
102 u64 gpu_addr, u64 seq);
103 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
104 struct amdgpu_ring *ring,
107 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,
108 uint16_t pasid, uint32_t flush_type,
111 int set_resources_size;
113 int unmap_queues_size;
114 int query_status_size;
115 int invalidate_tlbs_size;
120 struct amdgpu_bo *eop_obj;
121 spinlock_t ring_lock;
122 struct amdgpu_ring ring;
123 struct amdgpu_irq_src irq;
124 const struct kiq_pm4_funcs *pmf;
131 #define AMDGPU_GFX_MAX_SE 4
132 #define AMDGPU_GFX_MAX_SH_PER_SE 2
134 struct amdgpu_rb_config {
135 uint32_t rb_backend_disable;
136 uint32_t user_rb_backend_disable;
137 uint32_t raster_config;
138 uint32_t raster_config_1;
141 struct gb_addr_config {
142 uint16_t pipe_interleave_size;
144 uint8_t max_compress_frags;
147 uint8_t num_rb_per_se;
151 struct amdgpu_gfx_config {
152 unsigned max_shader_engines;
153 unsigned max_tile_pipes;
154 unsigned max_cu_per_sh;
155 unsigned max_sh_per_se;
156 unsigned max_backends_per_se;
157 unsigned max_texture_channel_caches;
159 unsigned max_gs_threads;
160 unsigned max_hw_contexts;
161 unsigned sc_prim_fifo_size_frontend;
162 unsigned sc_prim_fifo_size_backend;
163 unsigned sc_hiz_tile_fifo_size;
164 unsigned sc_earlyz_tile_fifo_size;
166 unsigned num_tile_pipes;
167 unsigned backend_enable_mask;
168 unsigned mem_max_burst_length_bytes;
169 unsigned mem_row_size_in_kb;
170 unsigned shader_engine_tile_size;
172 unsigned multi_gpu_tile_size;
173 unsigned mc_arb_ramcfg;
176 unsigned gb_addr_config;
178 unsigned gs_vgt_table_depth;
179 unsigned gs_prim_buffer_depth;
181 uint32_t tile_mode_array[32];
182 uint32_t macrotile_mode_array[16];
184 struct gb_addr_config gb_addr_config_fields;
185 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
187 /* gfx configure feature */
188 uint32_t double_offchip_lds_buf;
189 /* cached value of DB_DEBUG2 */
191 /* gfx10 specific config */
192 uint32_t num_sc_per_sh;
193 uint32_t num_packer_per_sc;
194 uint32_t pa_sc_tile_steering_override;
195 /* Whether texture coordinate truncation is conformant. */
196 bool ta_cntl2_truncate_coord_mode;
197 uint64_t tcc_disabled_mask;
198 uint32_t gc_num_tcp_per_sa;
199 uint32_t gc_num_sdp_interface;
200 uint32_t gc_num_tcps;
201 uint32_t gc_num_tcp_per_wpg;
202 uint32_t gc_tcp_l1_size;
203 uint32_t gc_num_sqc_per_wgp;
204 uint32_t gc_l1_instruction_cache_size_per_sqc;
205 uint32_t gc_l1_data_cache_size_per_sqc;
206 uint32_t gc_gl1c_per_sa;
207 uint32_t gc_gl1c_size_per_instance;
208 uint32_t gc_gl2c_per_gpu;
211 struct amdgpu_cu_info {
212 uint32_t simd_per_cu;
213 uint32_t max_waves_per_simd;
214 uint32_t wave_front_size;
215 uint32_t max_scratch_slots_per_cu;
218 /* total active CU number */
221 uint32_t ao_cu_bitmap[4][4];
222 uint32_t bitmap[4][4];
225 struct amdgpu_gfx_ras {
226 struct amdgpu_ras_block_object ras_block;
227 void (*enable_watchdog_timer)(struct amdgpu_device *adev);
228 bool (*query_utcl2_poison_status)(struct amdgpu_device *adev);
229 int (*rlc_gc_fed_irq)(struct amdgpu_device *adev,
230 struct amdgpu_irq_src *source,
231 struct amdgpu_iv_entry *entry);
232 int (*poison_consumption_handler)(struct amdgpu_device *adev,
233 struct amdgpu_iv_entry *entry);
236 struct amdgpu_gfx_shadow_info {
238 u32 shadow_alignment;
243 struct amdgpu_gfx_funcs {
244 /* get the gpu clock counter */
245 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
246 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
247 u32 sh_num, u32 instance, int xcc_id);
248 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
249 uint32_t wave, uint32_t *dst, int *no_fields);
250 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
251 uint32_t wave, uint32_t thread, uint32_t start,
252 uint32_t size, uint32_t *dst);
253 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
254 uint32_t wave, uint32_t start, uint32_t size,
256 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
257 u32 queue, u32 vmid);
258 void (*init_spm_golden)(struct amdgpu_device *adev);
259 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
260 int (*get_gfx_shadow_info)(struct amdgpu_device *adev,
261 struct amdgpu_gfx_shadow_info *shadow_info);
265 struct work_struct work;
270 struct amdgpu_bo *pfp_fw_obj;
271 uint64_t pfp_fw_gpu_addr;
272 uint32_t *pfp_fw_ptr;
274 struct amdgpu_bo *pfp_fw_data_obj;
275 uint64_t pfp_fw_data_gpu_addr;
276 uint32_t *pfp_fw_data_ptr;
280 struct amdgpu_bo *ce_fw_obj;
281 uint64_t ce_fw_gpu_addr;
286 struct amdgpu_bo *me_fw_obj;
287 uint64_t me_fw_gpu_addr;
290 struct amdgpu_bo *me_fw_data_obj;
291 uint64_t me_fw_data_gpu_addr;
292 uint32_t *me_fw_data_ptr;
295 uint32_t num_pipe_per_me;
296 uint32_t num_queue_per_pipe;
297 void *mqd_backup[AMDGPU_MAX_GFX_RINGS];
299 /* These are the resources for which amdgpu takes ownership */
300 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
304 struct mutex gpu_clock_mutex;
305 struct amdgpu_gfx_config config;
306 struct amdgpu_rlc rlc;
307 struct amdgpu_pfp pfp;
310 struct amdgpu_mec mec;
311 struct amdgpu_mec_bitmap mec_bitmap[AMDGPU_MAX_GC_INSTANCES];
312 struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES];
313 struct amdgpu_imu imu;
314 bool rs64_enable; /* firmware format */
315 const struct firmware *me_fw; /* ME firmware */
316 uint32_t me_fw_version;
317 const struct firmware *pfp_fw; /* PFP firmware */
318 uint32_t pfp_fw_version;
319 const struct firmware *ce_fw; /* CE firmware */
320 uint32_t ce_fw_version;
321 const struct firmware *rlc_fw; /* RLC firmware */
322 uint32_t rlc_fw_version;
323 const struct firmware *mec_fw; /* MEC firmware */
324 uint32_t mec_fw_version;
325 const struct firmware *mec2_fw; /* MEC2 firmware */
326 uint32_t mec2_fw_version;
327 const struct firmware *imu_fw; /* IMU firmware */
328 uint32_t imu_fw_version;
329 uint32_t me_feature_version;
330 uint32_t ce_feature_version;
331 uint32_t pfp_feature_version;
332 uint32_t rlc_feature_version;
333 uint32_t rlc_srlc_fw_version;
334 uint32_t rlc_srlc_feature_version;
335 uint32_t rlc_srlg_fw_version;
336 uint32_t rlc_srlg_feature_version;
337 uint32_t rlc_srls_fw_version;
338 uint32_t rlc_srls_feature_version;
339 uint32_t rlcp_ucode_version;
340 uint32_t rlcp_ucode_feature_version;
341 uint32_t rlcv_ucode_version;
342 uint32_t rlcv_ucode_feature_version;
343 uint32_t mec_feature_version;
344 uint32_t mec2_feature_version;
345 bool mec_fw_write_wait;
346 bool me_fw_write_wait;
347 bool cp_fw_write_wait;
348 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
349 unsigned num_gfx_rings;
350 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES];
351 unsigned num_compute_rings;
352 struct amdgpu_irq_src eop_irq;
353 struct amdgpu_irq_src priv_reg_irq;
354 struct amdgpu_irq_src priv_inst_irq;
355 struct amdgpu_irq_src cp_ecc_error_irq;
356 struct amdgpu_irq_src sq_irq;
357 struct amdgpu_irq_src rlc_gc_fed_irq;
358 struct sq_work sq_work;
361 uint32_t gfx_current_status;
363 unsigned ce_ram_size;
364 struct amdgpu_cu_info cu_info;
365 const struct amdgpu_gfx_funcs *funcs;
368 uint32_t grbm_soft_reset;
369 uint32_t srbm_soft_reset;
372 bool gfx_off_state; /* true: enabled, false: disabled */
373 struct mutex gfx_off_mutex; /* mutex to change gfxoff state */
374 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
375 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */
376 uint32_t gfx_off_residency; /* last logged residency */
377 uint64_t gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */
379 /* pipe reservation */
380 struct mutex pipe_reserve_mutex;
381 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
384 struct ras_common_if *ras_if;
385 struct amdgpu_gfx_ras *ras;
389 struct amdgpu_ring sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
390 struct amdgpu_ring_mux muxer;
392 bool cp_gfx_shadow; /* for gfx11 */
394 enum amdgpu_gfx_partition partition_mode;
396 uint32_t num_xcc_per_xcp;
399 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
400 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id)))
401 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
402 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
403 #define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si)))
406 * amdgpu_gfx_create_bitmask - create a bitmask
408 * @bit_width: length of the mask
410 * create a variable length bit mask.
411 * Returns the bitmask.
413 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
415 return (u32)((1ULL << bit_width) - 1);
418 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
421 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
422 struct amdgpu_ring *ring,
423 struct amdgpu_irq_src *irq, int xcc_id);
425 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
427 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id);
428 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
429 unsigned hpd_size, int xcc_id);
431 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
432 unsigned mqd_size, int xcc_id);
433 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id);
434 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id);
435 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id);
437 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
438 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
440 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
441 int pipe, int queue);
442 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
443 int *mec, int *pipe, int *queue);
444 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id,
445 int mec, int pipe, int queue);
446 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
447 struct amdgpu_ring *ring);
448 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
449 struct amdgpu_ring *ring);
450 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
451 int pipe, int queue);
452 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
453 int *me, int *pipe, int *queue);
454 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
455 int pipe, int queue);
456 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
457 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
458 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
459 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
460 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value);
461 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency);
462 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value);
463 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
465 struct amdgpu_iv_entry *entry);
466 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
467 struct amdgpu_irq_src *source,
468 struct amdgpu_iv_entry *entry);
469 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
470 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
471 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
472 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id);
474 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev);
475 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
476 struct amdgpu_iv_entry *entry);
478 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id);