drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_gfx.h"
  29 #include "amdgpu_rlc.h"
  30 #include "amdgpu_ras.h"
  31
  32 /* delay 0.1 second to enable gfx off feature */
  33 #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(100)
  34
  35 #define GFX_OFF_NO_DELAY 0
  36
  37 /*
  38  * GPU GFX IP block helpers function.
  39  */
  40
  41 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
  42                                 int pipe, int queue)
  43 {
  44         int bit = 0;
  45
  46         bit += mec * adev->gfx.mec.num_pipe_per_mec
  47                 * adev->gfx.mec.num_queue_per_pipe;
  48         bit += pipe * adev->gfx.mec.num_queue_per_pipe;
  49         bit += queue;
  50
  51         return bit;
  52 }
  53
  54 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
  55                                  int *mec, int *pipe, int *queue)
  56 {
  57         *queue = bit % adev->gfx.mec.num_queue_per_pipe;
  58         *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
  59                 % adev->gfx.mec.num_pipe_per_mec;
  60         *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
  61                / adev->gfx.mec.num_pipe_per_mec;
  62
  63 }
  64
  65 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
  66                                      int xcc_id, int mec, int pipe, int queue)
  67 {
  68         return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
  69                         adev->gfx.mec_bitmap[xcc_id].queue_bitmap);
  70 }
  71
  72 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
  73                                int me, int pipe, int queue)
  74 {
  75         int bit = 0;
  76
  77         bit += me * adev->gfx.me.num_pipe_per_me
  78                 * adev->gfx.me.num_queue_per_pipe;
  79         bit += pipe * adev->gfx.me.num_queue_per_pipe;
  80         bit += queue;
  81
  82         return bit;
  83 }
  84
  85 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
  86                                 int *me, int *pipe, int *queue)
  87 {
  88         *queue = bit % adev->gfx.me.num_queue_per_pipe;
  89         *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
  90                 % adev->gfx.me.num_pipe_per_me;
  91         *me = (bit / adev->gfx.me.num_queue_per_pipe)
  92                 / adev->gfx.me.num_pipe_per_me;
  93 }
  94
  95 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
  96                                     int me, int pipe, int queue)
  97 {
  98         return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
  99                         adev->gfx.me.queue_bitmap);
 100 }
 101
 102 /**
 103  * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
 104  *
 105  * @mask: array in which the per-shader array disable masks will be stored
 106  * @max_se: number of SEs
 107  * @max_sh: number of SHs
 108  *
 109  * The bitmask of CUs to be disabled in the shader array determined by se and
 110  * sh is stored in mask[se * max_sh + sh].
 111  */
 112 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
 113 {
 114         unsigned se, sh, cu;
 115         const char *p;
 116
 117         memset(mask, 0, sizeof(*mask) * max_se * max_sh);
 118
 119         if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
 120                 return;
 121
 122         p = amdgpu_disable_cu;
 123         for (;;) {
 124                 char *next;
 125                 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
 126                 if (ret < 3) {
 127                         DRM_ERROR("amdgpu: could not parse disable_cu\n");
 128                         return;
 129                 }
 130
 131                 if (se < max_se && sh < max_sh && cu < 16) {
 132                         DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
 133                         mask[se * max_sh + sh] |= 1u << cu;
 134                 } else {
 135                         DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
 136                                   se, sh, cu);
 137                 }
 138
 139                 next = strchr(p, ',');
 140                 if (!next)
 141                         break;
 142                 p = next + 1;
 143         }
 144 }
 145
 146 static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev)
 147 {
 148         return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1;
 149 }
 150
 151 static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev)
 152 {
 153         if (amdgpu_compute_multipipe != -1) {
 154                 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
 155                          amdgpu_compute_multipipe);
 156                 return amdgpu_compute_multipipe == 1;
 157         }
 158
 159         if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
 160                 return true;
 161
 162         /* FIXME: spreading the queues across pipes causes perf regressions
 163          * on POLARIS11 compute workloads */
 164         if (adev->asic_type == CHIP_POLARIS11)
 165                 return false;
 166
 167         return adev->gfx.mec.num_mec > 1;
 168 }
 169
 170 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
 171                                                 struct amdgpu_ring *ring)
 172 {
 173         int queue = ring->queue;
 174         int pipe = ring->pipe;
 175
 176         /* Policy: use pipe1 queue0 as high priority graphics queue if we
 177          * have more than one gfx pipe.
 178          */
 179         if (amdgpu_gfx_is_graphics_multipipe_capable(adev) &&
 180             adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {
 181                 int me = ring->me;
 182                 int bit;
 183
 184                 bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue);
 185                 if (ring == &adev->gfx.gfx_ring[bit])
 186                         return true;
 187         }
 188
 189         return false;
 190 }
 191
 192 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 193                                                struct amdgpu_ring *ring)
 194 {
 195         /* Policy: use 1st queue as high priority compute queue if we
 196          * have more than one compute queue.
 197          */
 198         if (adev->gfx.num_compute_rings > 1 &&
 199             ring == &adev->gfx.compute_ring[0])
 200                 return true;
 201
 202         return false;
 203 }
 204
 205 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 206 {
 207         int i, j, queue, pipe;
 208         bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev);
 209         int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
 210                                      adev->gfx.mec.num_queue_per_pipe,
 211                                      adev->gfx.num_compute_rings);
 212         int num_xcd = (adev->gfx.num_xcd > 1) ? adev->gfx.num_xcd : 1;
 213
 214         if (multipipe_policy) {
 215                 /* policy: make queues evenly cross all pipes on MEC1 only
 216                  * for multiple xcc, just use the original policy for simplicity */
 217                 for (j = 0; j < num_xcd; j++) {
 218                         for (i = 0; i < max_queues_per_mec; i++) {
 219                                 pipe = i % adev->gfx.mec.num_pipe_per_mec;
 220                                 queue = (i / adev->gfx.mec.num_pipe_per_mec) %
 221                                          adev->gfx.mec.num_queue_per_pipe;
 222
 223                                 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
 224                                         adev->gfx.mec_bitmap[j].queue_bitmap);
 225                         }
 226                 }
 227         } else {
 228                 /* policy: amdgpu owns all queues in the given pipe */
 229                 for (j = 0; j < num_xcd; j++) {
 230                         for (i = 0; i < max_queues_per_mec; ++i)
 231                                 set_bit(i, adev->gfx.mec_bitmap[j].queue_bitmap);
 232                 }
 233         }
 234
 235         for (j = 0; j < num_xcd; j++) {
 236                 dev_dbg(adev->dev, "mec queue bitmap weight=%d\n",
 237                         bitmap_weight(adev->gfx.mec_bitmap[j].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));
 238         }
 239 }
 240
 241 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
 242 {
 243         int i, queue, pipe;
 244         bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev);
 245         int max_queues_per_me = adev->gfx.me.num_pipe_per_me *
 246                                         adev->gfx.me.num_queue_per_pipe;
 247
 248         if (multipipe_policy) {
 249                 /* policy: amdgpu owns the first queue per pipe at this stage
 250                  * will extend to mulitple queues per pipe later */
 251                 for (i = 0; i < max_queues_per_me; i++) {
 252                         pipe = i % adev->gfx.me.num_pipe_per_me;
 253                         queue = (i / adev->gfx.me.num_pipe_per_me) %
 254                                 adev->gfx.me.num_queue_per_pipe;
 255
 256                         set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
 257                                 adev->gfx.me.queue_bitmap);
 258                 }
 259         } else {
 260                 for (i = 0; i < max_queues_per_me; ++i)
 261                         set_bit(i, adev->gfx.me.queue_bitmap);
 262         }
 263
 264         /* update the number of active graphics rings */
 265         adev->gfx.num_gfx_rings =
 266                 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 267 }
 268
 269 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 270                                   struct amdgpu_ring *ring, int xcc_id)
 271 {
 272         int queue_bit;
 273         int mec, pipe, queue;
 274
 275         queue_bit = adev->gfx.mec.num_mec
 276                     * adev->gfx.mec.num_pipe_per_mec
 277                     * adev->gfx.mec.num_queue_per_pipe;
 278
 279         while (--queue_bit >= 0) {
 280                 if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
 281                         continue;
 282
 283                 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 284
 285                 /*
 286                  * 1. Using pipes 2/3 from MEC 2 seems cause problems.
 287                  * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
 288                  * only can be issued on queue 0.
 289                  */
 290                 if ((mec == 1 && pipe > 1) || queue != 0)
 291                         continue;
 292
 293                 ring->me = mec + 1;
 294                 ring->pipe = pipe;
 295                 ring->queue = queue;
 296
 297                 return 0;
 298         }
 299
 300         dev_err(adev->dev, "Failed to find a queue for KIQ\n");
 301         return -EINVAL;
 302 }
 303
 304 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 305                              struct amdgpu_ring *ring,
 306                              struct amdgpu_irq_src *irq, int xcc_id)
 307 {
 308         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 309         int r = 0;
 310
 311         spin_lock_init(&kiq->ring_lock);
 312
 313         ring->adev = NULL;
 314         ring->ring_obj = NULL;
 315         ring->use_doorbell = true;
 316         ring->doorbell_index = adev->doorbell_index.kiq;
 317         ring->xcc_id = xcc_id;
 318         ring->vm_hub = AMDGPU_GFXHUB_0;
 319         if (xcc_id >= 1)
 320                 ring->doorbell_index = adev->doorbell_index.xcc1_kiq_start +
 321                                         xcc_id - 1;
 322         else
 323                 ring->doorbell_index = adev->doorbell_index.kiq;
 324
 325         r = amdgpu_gfx_kiq_acquire(adev, ring, xcc_id);
 326         if (r)
 327                 return r;
 328
 329         ring->eop_gpu_addr = kiq->eop_gpu_addr;
 330         ring->no_scheduler = true;
 331         sprintf(ring->name, "kiq_%d.%d.%d.%d", xcc_id, ring->me, ring->pipe, ring->queue);
 332         r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0,
 333                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 334         if (r)
 335                 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
 336
 337         return r;
 338 }
 339
 340 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
 341 {
 342         amdgpu_ring_fini(ring);
 343 }
 344
 345 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id)
 346 {
 347         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 348
 349         amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
 350 }
 351
 352 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 353                         unsigned hpd_size, int xcc_id)
 354 {
 355         int r;
 356         u32 *hpd;
 357         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 358
 359         r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
 360                                     AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
 361                                     &kiq->eop_gpu_addr, (void **)&hpd);
 362         if (r) {
 363                 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
 364                 return r;
 365         }
 366
 367         memset(hpd, 0, hpd_size);
 368
 369         r = amdgpu_bo_reserve(kiq->eop_obj, true);
 370         if (unlikely(r != 0))
 371                 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
 372         amdgpu_bo_kunmap(kiq->eop_obj);
 373         amdgpu_bo_unreserve(kiq->eop_obj);
 374
 375         return 0;
 376 }
 377
 378 /* create MQD for each compute/gfx queue */
 379 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 380                            unsigned mqd_size, int xcc_id)
 381 {
 382         int r, i;
 383         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 384         struct amdgpu_ring *ring = &kiq->ring;
 385
 386         /* create MQD for KIQ */
 387         if (!adev->enable_mes_kiq && !ring->mqd_obj) {
 388                 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
 389                  * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
 390                  * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
 391                  * KIQ MQD no matter SRIOV or Bare-metal
 392                  */
 393                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 394                                             AMDGPU_GEM_DOMAIN_VRAM |
 395                                             AMDGPU_GEM_DOMAIN_GTT,
 396                                             &ring->mqd_obj,
 397                                             &ring->mqd_gpu_addr,
 398                                             &ring->mqd_ptr);
 399                 if (r) {
 400                         dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
 401                         return r;
 402                 }
 403
 404                 /* prepare MQD backup */
 405                 kiq->mqd_backup = kmalloc(mqd_size, GFP_KERNEL);
 406                 if (!kiq->mqd_backup)
 407                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 408         }
 409
 410         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 411                 /* create MQD for each KGQ */
 412                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 413                         ring = &adev->gfx.gfx_ring[i];
 414                         if (!ring->mqd_obj) {
 415                                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 416                                                             AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
 417                                                             &ring->mqd_gpu_addr, &ring->mqd_ptr);
 418                                 if (r) {
 419                                         dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 420                                         return r;
 421                                 }
 422
 423                                 ring->mqd_size = mqd_size;
 424                                 /* prepare MQD backup */
 425                                 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
 426                                 if (!adev->gfx.me.mqd_backup[i])
 427                                         dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 428                         }
 429                 }
 430         }
 431
 432         /* create MQD for each KCQ */
 433         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 434                 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings];
 435                 if (!ring->mqd_obj) {
 436                         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 437                                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
 438                                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
 439                         if (r) {
 440                                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 441                                 return r;
 442                         }
 443
 444                         ring->mqd_size = mqd_size;
 445                         /* prepare MQD backup */
 446                         adev->gfx.mec.mqd_backup[i + xcc_id * adev->gfx.num_compute_rings] = kmalloc(mqd_size, GFP_KERNEL);
 447                         if (!adev->gfx.mec.mqd_backup[i])
 448                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 449                 }
 450         }
 451
 452         return 0;
 453 }
 454
 455 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id)
 456 {
 457         struct amdgpu_ring *ring = NULL;
 458         int i, j;
 459         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 460
 461         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 462                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 463                         ring = &adev->gfx.gfx_ring[i];
 464                         kfree(adev->gfx.me.mqd_backup[i]);
 465                         amdgpu_bo_free_kernel(&ring->mqd_obj,
 466                                               &ring->mqd_gpu_addr,
 467                                               &ring->mqd_ptr);
 468                 }
 469         }
 470
 471         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 472                 j = i + xcc_id * adev->gfx.num_compute_rings;
 473                 ring = &adev->gfx.compute_ring[i];
 474                 kfree(adev->gfx.mec.mqd_backup[i]);
 475                 amdgpu_bo_free_kernel(&ring->mqd_obj,
 476                                       &ring->mqd_gpu_addr,
 477                                       &ring->mqd_ptr);
 478         }
 479
 480         ring = &kiq->ring;
 481         kfree(kiq->mqd_backup);
 482         kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
 483         amdgpu_bo_free_kernel(&ring->mqd_obj,
 484                               &ring->mqd_gpu_addr,
 485                               &ring->mqd_ptr);
 486 }
 487
 488 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id)
 489 {
 490         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 491         struct amdgpu_ring *kiq_ring = &kiq->ring;
 492         int i, r = 0;
 493         int j;
 494
 495         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 496                 return -EINVAL;
 497
 498         spin_lock(&kiq->ring_lock);
 499         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 500                 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 501                                                 adev->gfx.num_compute_rings)) {
 502                         spin_unlock(&kiq->ring_lock);
 503                         return -ENOMEM;
 504                 }
 505
 506                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 507                         j = i + xcc_id * adev->gfx.num_compute_rings;
 508                         kiq->pmf->kiq_unmap_queues(kiq_ring,
 509                                                    &adev->gfx.compute_ring[i],
 510                                                    RESET_QUEUES, 0, 0);
 511                 }
 512         }
 513
 514         if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang)
 515                 r = amdgpu_ring_test_helper(kiq_ring);
 516         spin_unlock(&kiq->ring_lock);
 517
 518         return r;
 519 }
 520
 521 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
 522                                         int queue_bit)
 523 {
 524         int mec, pipe, queue;
 525         int set_resource_bit = 0;
 526
 527         amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 528
 529         set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;
 530
 531         return set_resource_bit;
 532 }
 533
 534 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)
 535 {
 536         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 537         struct amdgpu_ring *kiq_ring = &kiq->ring;
 538         uint64_t queue_mask = 0;
 539         int r, i, j;
 540
 541         if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
 542                 return -EINVAL;
 543
 544         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
 545                 if (!test_bit(i, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
 546                         continue;
 547
 548                 /* This situation may be hit in the future if a new HW
 549                  * generation exposes more than 64 queues. If so, the
 550                  * definition of queue_mask needs updating */
 551                 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
 552                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
 553                         break;
 554                 }
 555
 556                 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i));
 557         }
 558
 559         DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
 560                                                         kiq_ring->queue);
 561         spin_lock(&kiq->ring_lock);
 562         /* No need to map kcq on the slave */
 563         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 564                 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 565                                                 adev->gfx.num_compute_rings +
 566                                                 kiq->pmf->set_resources_size);
 567                 if (r) {
 568                         DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 569                         spin_unlock(&adev->gfx.kiq[0].ring_lock);
 570                         return r;
 571                 }
 572
 573                 if (adev->enable_mes)
 574                         queue_mask = ~0ULL;
 575
 576                 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
 577                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 578                         j = i + xcc_id * adev->gfx.num_compute_rings;
 579                         kiq->pmf->kiq_map_queues(kiq_ring,
 580                                                  &adev->gfx.compute_ring[i]);
 581                 }
 582         }
 583
 584         r = amdgpu_ring_test_helper(kiq_ring);
 585         spin_unlock(&kiq->ring_lock);
 586         if (r)
 587                 DRM_ERROR("KCQ enable failed\n");
 588
 589         return r;
 590 }
 591
 592 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
 593  *
 594  * @adev: amdgpu_device pointer
 595  * @bool enable true: enable gfx off feature, false: disable gfx off feature
 596  *
 597  * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
 598  * 2. other client can send request to disable gfx off feature, the request should be honored.
 599  * 3. other client can cancel their request of disable gfx off feature
 600  * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
 601  */
 602
 603 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 604 {
 605         unsigned long delay = GFX_OFF_DELAY_ENABLE;
 606
 607         if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 608                 return;
 609
 610         mutex_lock(&adev->gfx.gfx_off_mutex);
 611
 612         if (enable) {
 613                 /* If the count is already 0, it means there's an imbalance bug somewhere.
 614                  * Note that the bug may be in a different caller than the one which triggers the
 615                  * WARN_ON_ONCE.
 616                  */
 617                 if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0))
 618                         goto unlock;
 619
 620                 adev->gfx.gfx_off_req_count--;
 621
 622                 if (adev->gfx.gfx_off_req_count == 0 &&
 623                     !adev->gfx.gfx_off_state) {
 624                         /* If going to s2idle, no need to wait */
 625                         if (adev->in_s0ix) {
 626                                 if (!amdgpu_dpm_set_powergating_by_smu(adev,
 627                                                 AMD_IP_BLOCK_TYPE_GFX, true))
 628                                         adev->gfx.gfx_off_state = true;
 629                         } else {
 630                                 schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
 631                                               delay);
 632                         }
 633                 }
 634         } else {
 635                 if (adev->gfx.gfx_off_req_count == 0) {
 636                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
 637
 638                         if (adev->gfx.gfx_off_state &&
 639                             !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
 640                                 adev->gfx.gfx_off_state = false;
 641
 642                                 if (adev->gfx.funcs->init_spm_golden) {
 643                                         dev_dbg(adev->dev,
 644                                                 "GFXOFF is disabled, re-init SPM golden settings\n");
 645                                         amdgpu_gfx_init_spm_golden(adev);
 646                                 }
 647                         }
 648                 }
 649
 650                 adev->gfx.gfx_off_req_count++;
 651         }
 652
 653 unlock:
 654         mutex_unlock(&adev->gfx.gfx_off_mutex);
 655 }
 656
 657 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value)
 658 {
 659         int r = 0;
 660
 661         mutex_lock(&adev->gfx.gfx_off_mutex);
 662
 663         r = amdgpu_dpm_set_residency_gfxoff(adev, value);
 664
 665         mutex_unlock(&adev->gfx.gfx_off_mutex);
 666
 667         return r;
 668 }
 669
 670 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value)
 671 {
 672         int r = 0;
 673
 674         mutex_lock(&adev->gfx.gfx_off_mutex);
 675
 676         r = amdgpu_dpm_get_residency_gfxoff(adev, value);
 677
 678         mutex_unlock(&adev->gfx.gfx_off_mutex);
 679
 680         return r;
 681 }
 682
 683 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value)
 684 {
 685         int r = 0;
 686
 687         mutex_lock(&adev->gfx.gfx_off_mutex);
 688
 689         r = amdgpu_dpm_get_entrycount_gfxoff(adev, value);
 690
 691         mutex_unlock(&adev->gfx.gfx_off_mutex);
 692
 693         return r;
 694 }
 695
 696 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)
 697 {
 698
 699         int r = 0;
 700
 701         mutex_lock(&adev->gfx.gfx_off_mutex);
 702
 703         r = amdgpu_dpm_get_status_gfxoff(adev, value);
 704
 705         mutex_unlock(&adev->gfx.gfx_off_mutex);
 706
 707         return r;
 708 }
 709
 710 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 711 {
 712         int r;
 713
 714         if (amdgpu_ras_is_supported(adev, ras_block->block)) {
 715                 if (!amdgpu_persistent_edc_harvesting_supported(adev))
 716                         amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);
 717
 718                 r = amdgpu_ras_block_late_init(adev, ras_block);
 719                 if (r)
 720                         return r;
 721
 722                 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
 723                 if (r)
 724                         goto late_fini;
 725         } else {
 726                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
 727         }
 728
 729         return 0;
 730 late_fini:
 731         amdgpu_ras_block_late_fini(adev, ras_block);
 732         return r;
 733 }
 734
 735 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev)
 736 {
 737         int err = 0;
 738         struct amdgpu_gfx_ras *ras = NULL;
 739
 740         /* adev->gfx.ras is NULL, which means gfx does not
 741          * support ras function, then do nothing here.
 742          */
 743         if (!adev->gfx.ras)
 744                 return 0;
 745
 746         ras = adev->gfx.ras;
 747
 748         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
 749         if (err) {
 750                 dev_err(adev->dev, "Failed to register gfx ras block!\n");
 751                 return err;
 752         }
 753
 754         strcpy(ras->ras_block.ras_comm.name, "gfx");
 755         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX;
 756         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 757         adev->gfx.ras_if = &ras->ras_block.ras_comm;
 758
 759         /* If not define special ras_late_init function, use gfx default ras_late_init */
 760         if (!ras->ras_block.ras_late_init)
 761                 ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init;
 762
 763         /* If not defined special ras_cb function, use default ras_cb */
 764         if (!ras->ras_block.ras_cb)
 765                 ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb;
 766
 767         return 0;
 768 }
 769
 770 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
 771                                                 struct amdgpu_iv_entry *entry)
 772 {
 773         if (adev->gfx.ras && adev->gfx.ras->poison_consumption_handler)
 774                 return adev->gfx.ras->poison_consumption_handler(adev, entry);
 775
 776         return 0;
 777 }
 778
 779 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
 780                 void *err_data,
 781                 struct amdgpu_iv_entry *entry)
 782 {
 783         /* TODO ue will trigger an interrupt.
 784          *
 785          * When “Full RAS” is enabled, the per-IP interrupt sources should
 786          * be disabled and the driver should only look for the aggregated
 787          * interrupt via sync flood
 788          */
 789         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
 790                 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 791                 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops &&
 792                     adev->gfx.ras->ras_block.hw_ops->query_ras_error_count)
 793                         adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
 794                 amdgpu_ras_reset_gpu(adev);
 795         }
 796         return AMDGPU_RAS_SUCCESS;
 797 }
 798
 799 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 800                                   struct amdgpu_irq_src *source,
 801                                   struct amdgpu_iv_entry *entry)
 802 {
 803         struct ras_common_if *ras_if = adev->gfx.ras_if;
 804         struct ras_dispatch_if ih_data = {
 805                 .entry = entry,
 806         };
 807
 808         if (!ras_if)
 809                 return 0;
 810
 811         ih_data.head = *ras_if;
 812
 813         DRM_ERROR("CP ECC ERROR IRQ\n");
 814         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 815         return 0;
 816 }
 817
 818 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
 819 {
 820         signed long r, cnt = 0;
 821         unsigned long flags;
 822         uint32_t seq, reg_val_offs = 0, value = 0;
 823         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 824         struct amdgpu_ring *ring = &kiq->ring;
 825
 826         if (amdgpu_device_skip_hw_access(adev))
 827                 return 0;
 828
 829         if (adev->mes.ring.sched.ready)
 830                 return amdgpu_mes_rreg(adev, reg);
 831
 832         BUG_ON(!ring->funcs->emit_rreg);
 833
 834         spin_lock_irqsave(&kiq->ring_lock, flags);
 835         if (amdgpu_device_wb_get(adev, &reg_val_offs)) {
 836                 pr_err("critical bug! too many kiq readers\n");
 837                 goto failed_unlock;
 838         }
 839         amdgpu_ring_alloc(ring, 32);
 840         amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
 841         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 842         if (r)
 843                 goto failed_undo;
 844
 845         amdgpu_ring_commit(ring);
 846         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 847
 848         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 849
 850         /* don't wait anymore for gpu reset case because this way may
 851          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 852          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 853          * never return if we keep waiting in virt_kiq_rreg, which cause
 854          * gpu_recover() hang there.
 855          *
 856          * also don't wait anymore for IRQ context
 857          * */
 858         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 859                 goto failed_kiq_read;
 860
 861         might_sleep();
 862         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 863                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 864                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 865         }
 866
 867         if (cnt > MAX_KIQ_REG_TRY)
 868                 goto failed_kiq_read;
 869
 870         mb();
 871         value = adev->wb.wb[reg_val_offs];
 872         amdgpu_device_wb_free(adev, reg_val_offs);
 873         return value;
 874
 875 failed_undo:
 876         amdgpu_ring_undo(ring);
 877 failed_unlock:
 878         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 879 failed_kiq_read:
 880         if (reg_val_offs)
 881                 amdgpu_device_wb_free(adev, reg_val_offs);
 882         dev_err(adev->dev, "failed to read reg:%x\n", reg);
 883         return ~0;
 884 }
 885
 886 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 887 {
 888         signed long r, cnt = 0;
 889         unsigned long flags;
 890         uint32_t seq;
 891         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 892         struct amdgpu_ring *ring = &kiq->ring;
 893
 894         BUG_ON(!ring->funcs->emit_wreg);
 895
 896         if (amdgpu_device_skip_hw_access(adev))
 897                 return;
 898
 899         if (adev->mes.ring.sched.ready) {
 900                 amdgpu_mes_wreg(adev, reg, v);
 901                 return;
 902         }
 903
 904         spin_lock_irqsave(&kiq->ring_lock, flags);
 905         amdgpu_ring_alloc(ring, 32);
 906         amdgpu_ring_emit_wreg(ring, reg, v);
 907         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 908         if (r)
 909                 goto failed_undo;
 910
 911         amdgpu_ring_commit(ring);
 912         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 913
 914         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 915
 916         /* don't wait anymore for gpu reset case because this way may
 917          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 918          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 919          * never return if we keep waiting in virt_kiq_rreg, which cause
 920          * gpu_recover() hang there.
 921          *
 922          * also don't wait anymore for IRQ context
 923          * */
 924         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 925                 goto failed_kiq_write;
 926
 927         might_sleep();
 928         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 929
 930                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 931                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 932         }
 933
 934         if (cnt > MAX_KIQ_REG_TRY)
 935                 goto failed_kiq_write;
 936
 937         return;
 938
 939 failed_undo:
 940         amdgpu_ring_undo(ring);
 941         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 942 failed_kiq_write:
 943         dev_err(adev->dev, "failed to write reg:%x\n", reg);
 944 }
 945
 946 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
 947 {
 948         if (amdgpu_num_kcq == -1) {
 949                 return 8;
 950         } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
 951                 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
 952                 return 8;
 953         }
 954         return amdgpu_num_kcq;
 955 }
 956
 957 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev,
 958                                   uint32_t ucode_id)
 959 {
 960         const struct gfx_firmware_header_v1_0 *cp_hdr;
 961         const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
 962         struct amdgpu_firmware_info *info = NULL;
 963         const struct firmware *ucode_fw;
 964         unsigned int fw_size;
 965
 966         switch (ucode_id) {
 967         case AMDGPU_UCODE_ID_CP_PFP:
 968                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 969                         adev->gfx.pfp_fw->data;
 970                 adev->gfx.pfp_fw_version =
 971                         le32_to_cpu(cp_hdr->header.ucode_version);
 972                 adev->gfx.pfp_feature_version =
 973                         le32_to_cpu(cp_hdr->ucode_feature_version);
 974                 ucode_fw = adev->gfx.pfp_fw;
 975                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
 976                 break;
 977         case AMDGPU_UCODE_ID_CP_RS64_PFP:
 978                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
 979                         adev->gfx.pfp_fw->data;
 980                 adev->gfx.pfp_fw_version =
 981                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
 982                 adev->gfx.pfp_feature_version =
 983                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
 984                 ucode_fw = adev->gfx.pfp_fw;
 985                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
 986                 break;
 987         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
 988         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
 989                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
 990                         adev->gfx.pfp_fw->data;
 991                 ucode_fw = adev->gfx.pfp_fw;
 992                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
 993                 break;
 994         case AMDGPU_UCODE_ID_CP_ME:
 995                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 996                         adev->gfx.me_fw->data;
 997                 adev->gfx.me_fw_version =
 998                         le32_to_cpu(cp_hdr->header.ucode_version);
 999                 adev->gfx.me_feature_version =
1000                         le32_to_cpu(cp_hdr->ucode_feature_version);
1001                 ucode_fw = adev->gfx.me_fw;
1002                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1003                 break;
1004         case AMDGPU_UCODE_ID_CP_RS64_ME:
1005                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1006                         adev->gfx.me_fw->data;
1007                 adev->gfx.me_fw_version =
1008                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1009                 adev->gfx.me_feature_version =
1010                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1011                 ucode_fw = adev->gfx.me_fw;
1012                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1013                 break;
1014         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
1015         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
1016                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1017                         adev->gfx.me_fw->data;
1018                 ucode_fw = adev->gfx.me_fw;
1019                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1020                 break;
1021         case AMDGPU_UCODE_ID_CP_CE:
1022                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1023                         adev->gfx.ce_fw->data;
1024                 adev->gfx.ce_fw_version =
1025                         le32_to_cpu(cp_hdr->header.ucode_version);
1026                 adev->gfx.ce_feature_version =
1027                         le32_to_cpu(cp_hdr->ucode_feature_version);
1028                 ucode_fw = adev->gfx.ce_fw;
1029                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1030                 break;
1031         case AMDGPU_UCODE_ID_CP_MEC1:
1032                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1033                         adev->gfx.mec_fw->data;
1034                 adev->gfx.mec_fw_version =
1035                         le32_to_cpu(cp_hdr->header.ucode_version);
1036                 adev->gfx.mec_feature_version =
1037                         le32_to_cpu(cp_hdr->ucode_feature_version);
1038                 ucode_fw = adev->gfx.mec_fw;
1039                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1040                           le32_to_cpu(cp_hdr->jt_size) * 4;
1041                 break;
1042         case AMDGPU_UCODE_ID_CP_MEC1_JT:
1043                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1044                         adev->gfx.mec_fw->data;
1045                 ucode_fw = adev->gfx.mec_fw;
1046                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1047                 break;
1048         case AMDGPU_UCODE_ID_CP_MEC2:
1049                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1050                         adev->gfx.mec2_fw->data;
1051                 adev->gfx.mec2_fw_version =
1052                         le32_to_cpu(cp_hdr->header.ucode_version);
1053                 adev->gfx.mec2_feature_version =
1054                         le32_to_cpu(cp_hdr->ucode_feature_version);
1055                 ucode_fw = adev->gfx.mec2_fw;
1056                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1057                           le32_to_cpu(cp_hdr->jt_size) * 4;
1058                 break;
1059         case AMDGPU_UCODE_ID_CP_MEC2_JT:
1060                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1061                         adev->gfx.mec2_fw->data;
1062                 ucode_fw = adev->gfx.mec2_fw;
1063                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1064                 break;
1065         case AMDGPU_UCODE_ID_CP_RS64_MEC:
1066                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1067                         adev->gfx.mec_fw->data;
1068                 adev->gfx.mec_fw_version =
1069                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1070                 adev->gfx.mec_feature_version =
1071                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1072                 ucode_fw = adev->gfx.mec_fw;
1073                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1074                 break;
1075         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
1076         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
1077         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
1078         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
1079                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1080                         adev->gfx.mec_fw->data;
1081                 ucode_fw = adev->gfx.mec_fw;
1082                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1083                 break;
1084         default:
1085                 break;
1086         }
1087
1088         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1089                 info = &adev->firmware.ucode[ucode_id];
1090                 info->ucode_id = ucode_id;
1091                 info->fw = ucode_fw;
1092                 adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE);
1093         }
1094 }
1095
1096 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id)
1097 {
1098         return !(xcc_id % (adev->gfx.num_xcc_per_xcp ?
1099                         adev->gfx.num_xcc_per_xcp : 1));
1100 }