2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/ktime.h>
29 #include <linux/module.h>
30 #include <linux/pagemap.h>
31 #include <linux/pci.h>
32 #include <linux/dma-buf.h>
34 #include <drm/amdgpu_drm.h>
35 #include <drm/drm_drv.h>
36 #include <drm/drm_exec.h>
37 #include <drm/drm_gem_ttm_helper.h>
38 #include <drm/ttm/ttm_tt.h>
41 #include "amdgpu_display.h"
42 #include "amdgpu_dma_buf.h"
43 #include "amdgpu_hmm.h"
44 #include "amdgpu_xgmi.h"
46 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs;
48 static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf)
50 struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
51 struct drm_device *ddev = bo->base.dev;
55 ret = ttm_bo_vm_reserve(bo, vmf);
59 if (drm_dev_enter(ddev, &idx)) {
60 ret = amdgpu_bo_fault_reserve_notify(bo);
66 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
67 TTM_BO_VM_NUM_PREFAULT);
71 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot);
73 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
77 dma_resv_unlock(bo->base.resv);
81 static const struct vm_operations_struct amdgpu_gem_vm_ops = {
82 .fault = amdgpu_gem_fault,
83 .open = ttm_bo_vm_open,
84 .close = ttm_bo_vm_close,
85 .access = ttm_bo_vm_access
88 static void amdgpu_gem_object_free(struct drm_gem_object *gobj)
90 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
93 amdgpu_hmm_unregister(robj);
94 amdgpu_bo_unref(&robj);
98 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
99 int alignment, u32 initial_domain,
100 u64 flags, enum ttm_bo_type type,
101 struct dma_resv *resv,
102 struct drm_gem_object **obj, int8_t xcp_id_plus1)
104 struct amdgpu_bo *bo;
105 struct amdgpu_bo_user *ubo;
106 struct amdgpu_bo_param bp;
109 memset(&bp, 0, sizeof(bp));
113 bp.byte_align = alignment;
116 bp.preferred_domain = initial_domain;
118 bp.domain = initial_domain;
119 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
120 bp.xcp_id_plus1 = xcp_id_plus1;
122 r = amdgpu_bo_create_user(adev, &bp, &ubo);
127 *obj = &bo->tbo.base;
128 (*obj)->funcs = &amdgpu_gem_object_funcs;
133 void amdgpu_gem_force_release(struct amdgpu_device *adev)
135 struct drm_device *ddev = adev_to_drm(adev);
136 struct drm_file *file;
138 mutex_lock(&ddev->filelist_mutex);
140 list_for_each_entry(file, &ddev->filelist, lhead) {
141 struct drm_gem_object *gobj;
144 WARN_ONCE(1, "Still active user space clients!\n");
145 spin_lock(&file->table_lock);
146 idr_for_each_entry(&file->object_idr, gobj, handle) {
147 WARN_ONCE(1, "And also active allocations!\n");
148 drm_gem_object_put(gobj);
150 idr_destroy(&file->object_idr);
151 spin_unlock(&file->table_lock);
154 mutex_unlock(&ddev->filelist_mutex);
158 * Call from drm_gem_handle_create which appear in both new and open ioctl
161 static int amdgpu_gem_object_open(struct drm_gem_object *obj,
162 struct drm_file *file_priv)
164 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
165 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
166 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
167 struct amdgpu_vm *vm = &fpriv->vm;
168 struct amdgpu_bo_va *bo_va;
169 struct mm_struct *mm;
172 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
173 if (mm && mm != current->mm)
176 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
177 abo->tbo.base.resv != vm->root.bo->tbo.base.resv)
180 r = amdgpu_bo_reserve(abo, false);
184 bo_va = amdgpu_vm_bo_find(vm, abo);
186 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
190 amdgpu_bo_unreserve(abo);
194 static void amdgpu_gem_object_close(struct drm_gem_object *obj,
195 struct drm_file *file_priv)
197 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
198 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
199 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
200 struct amdgpu_vm *vm = &fpriv->vm;
202 struct dma_fence *fence = NULL;
203 struct amdgpu_bo_va *bo_va;
204 struct drm_exec exec;
207 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES);
208 drm_exec_until_all_locked(&exec) {
209 r = drm_exec_prepare_obj(&exec, &bo->tbo.base, 1);
210 drm_exec_retry_on_contention(&exec);
214 r = amdgpu_vm_lock_pd(vm, &exec, 0);
215 drm_exec_retry_on_contention(&exec);
220 bo_va = amdgpu_vm_bo_find(vm, bo);
221 if (!bo_va || --bo_va->ref_count)
224 amdgpu_vm_bo_del(adev, bo_va);
225 if (!amdgpu_vm_ready(vm))
228 r = amdgpu_vm_clear_freed(adev, vm, &fence);
230 dev_err(adev->dev, "failed to clear page "
231 "tables on GEM object close (%ld)\n", r);
235 amdgpu_bo_fence(bo, fence, true);
236 dma_fence_put(fence);
240 dev_err(adev->dev, "leaking bo va (%ld)\n", r);
241 drm_exec_fini(&exec);
244 static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
246 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
248 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
250 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
253 /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings
254 * for debugger access to invisible VRAM. Should have used MAP_SHARED
255 * instead. Clearing VM_MAYWRITE prevents the mapping from ever
256 * becoming writable and makes is_cow_mapping(vm_flags) false.
258 if (is_cow_mapping(vma->vm_flags) &&
259 !(vma->vm_flags & VM_ACCESS_FLAGS))
260 vm_flags_clear(vma, VM_MAYWRITE);
262 return drm_gem_ttm_mmap(obj, vma);
265 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {
266 .free = amdgpu_gem_object_free,
267 .open = amdgpu_gem_object_open,
268 .close = amdgpu_gem_object_close,
269 .export = amdgpu_gem_prime_export,
270 .vmap = drm_gem_ttm_vmap,
271 .vunmap = drm_gem_ttm_vunmap,
272 .mmap = amdgpu_gem_object_mmap,
273 .vm_ops = &amdgpu_gem_vm_ops,
279 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
280 struct drm_file *filp)
282 struct amdgpu_device *adev = drm_to_adev(dev);
283 struct amdgpu_fpriv *fpriv = filp->driver_priv;
284 struct amdgpu_vm *vm = &fpriv->vm;
285 union drm_amdgpu_gem_create *args = data;
286 uint64_t flags = args->in.domain_flags;
287 uint64_t size = args->in.bo_size;
288 struct dma_resv *resv = NULL;
289 struct drm_gem_object *gobj;
290 uint32_t handle, initial_domain;
293 /* reject invalid gem flags */
294 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
295 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
296 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
297 AMDGPU_GEM_CREATE_VRAM_CLEARED |
298 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
299 AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
300 AMDGPU_GEM_CREATE_ENCRYPTED |
301 AMDGPU_GEM_CREATE_DISCARDABLE))
304 /* reject invalid gem domains */
305 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
308 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
309 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n");
313 /* create a gem object to contain this object in */
314 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
315 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
316 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
317 /* if gds bo is created from user space, it must be
320 DRM_ERROR("GDS bo cannot be per-vm-bo\n");
323 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
326 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
327 r = amdgpu_bo_reserve(vm->root.bo, false);
331 resv = vm->root.bo->tbo.base.resv;
334 initial_domain = (u32)(0xffffffff & args->in.domains);
336 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
338 flags, ttm_bo_type_device, resv, &gobj, fpriv->xcp_id + 1);
339 if (r && r != -ERESTARTSYS) {
340 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
341 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
345 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
346 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
349 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
350 size, initial_domain, args->in.alignment, r);
353 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
355 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
357 abo->parent = amdgpu_bo_ref(vm->root.bo);
359 amdgpu_bo_unreserve(vm->root.bo);
364 r = drm_gem_handle_create(filp, gobj, &handle);
365 /* drop reference from allocate - handle holds it now */
366 drm_gem_object_put(gobj);
370 memset(args, 0, sizeof(*args));
371 args->out.handle = handle;
375 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
376 struct drm_file *filp)
378 struct ttm_operation_ctx ctx = { true, false };
379 struct amdgpu_device *adev = drm_to_adev(dev);
380 struct drm_amdgpu_gem_userptr *args = data;
381 struct amdgpu_fpriv *fpriv = filp->driver_priv;
382 struct drm_gem_object *gobj;
383 struct hmm_range *range;
384 struct amdgpu_bo *bo;
388 args->addr = untagged_addr(args->addr);
390 if (offset_in_page(args->addr | args->size))
393 /* reject unknown flag values */
394 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
395 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
396 AMDGPU_GEM_USERPTR_REGISTER))
399 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
400 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
402 /* if we want to write to it we must install a MMU notifier */
406 /* create a gem object to contain this object in */
407 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
408 0, ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
412 bo = gem_to_amdgpu_bo(gobj);
413 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
414 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
415 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags);
419 r = amdgpu_hmm_register(bo, args->addr);
423 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
424 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
429 r = amdgpu_bo_reserve(bo, true);
431 goto user_pages_done;
433 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
434 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
435 amdgpu_bo_unreserve(bo);
437 goto user_pages_done;
440 r = drm_gem_handle_create(filp, gobj, &handle);
442 goto user_pages_done;
444 args->handle = handle;
447 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
448 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
451 drm_gem_object_put(gobj);
456 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
457 struct drm_device *dev,
458 uint32_t handle, uint64_t *offset_p)
460 struct drm_gem_object *gobj;
461 struct amdgpu_bo *robj;
463 gobj = drm_gem_object_lookup(filp, handle);
467 robj = gem_to_amdgpu_bo(gobj);
468 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
469 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
470 drm_gem_object_put(gobj);
473 *offset_p = amdgpu_bo_mmap_offset(robj);
474 drm_gem_object_put(gobj);
478 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
479 struct drm_file *filp)
481 union drm_amdgpu_gem_mmap *args = data;
482 uint32_t handle = args->in.handle;
483 memset(args, 0, sizeof(*args));
484 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
488 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
490 * @timeout_ns: timeout in ns
492 * Calculate the timeout in jiffies from an absolute timeout in ns.
494 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
496 unsigned long timeout_jiffies;
499 /* clamp timeout if it's to large */
500 if (((int64_t)timeout_ns) < 0)
501 return MAX_SCHEDULE_TIMEOUT;
503 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
504 if (ktime_to_ns(timeout) < 0)
507 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
508 /* clamp timeout to avoid unsigned-> signed overflow */
509 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
510 return MAX_SCHEDULE_TIMEOUT - 1;
512 return timeout_jiffies;
515 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
516 struct drm_file *filp)
518 union drm_amdgpu_gem_wait_idle *args = data;
519 struct drm_gem_object *gobj;
520 struct amdgpu_bo *robj;
521 uint32_t handle = args->in.handle;
522 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
526 gobj = drm_gem_object_lookup(filp, handle);
530 robj = gem_to_amdgpu_bo(gobj);
531 ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ,
534 /* ret == 0 means not signaled,
535 * ret > 0 means signaled
536 * ret < 0 means interrupted before timeout
539 memset(args, 0, sizeof(*args));
540 args->out.status = (ret == 0);
544 drm_gem_object_put(gobj);
548 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
549 struct drm_file *filp)
551 struct drm_amdgpu_gem_metadata *args = data;
552 struct drm_gem_object *gobj;
553 struct amdgpu_bo *robj;
556 DRM_DEBUG("%d \n", args->handle);
557 gobj = drm_gem_object_lookup(filp, args->handle);
560 robj = gem_to_amdgpu_bo(gobj);
562 r = amdgpu_bo_reserve(robj, false);
563 if (unlikely(r != 0))
566 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
567 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
568 r = amdgpu_bo_get_metadata(robj, args->data.data,
569 sizeof(args->data.data),
570 &args->data.data_size_bytes,
572 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
573 if (args->data.data_size_bytes > sizeof(args->data.data)) {
577 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
579 r = amdgpu_bo_set_metadata(robj, args->data.data,
580 args->data.data_size_bytes,
585 amdgpu_bo_unreserve(robj);
587 drm_gem_object_put(gobj);
592 * amdgpu_gem_va_update_vm -update the bo_va in its VM
594 * @adev: amdgpu_device pointer
596 * @bo_va: bo_va to update
597 * @operation: map, unmap or clear
599 * Update the bo_va directly after setting its address. Errors are not
600 * vital here, so they are not reported back to userspace.
602 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
603 struct amdgpu_vm *vm,
604 struct amdgpu_bo_va *bo_va,
609 if (!amdgpu_vm_ready(vm))
612 r = amdgpu_vm_clear_freed(adev, vm, NULL);
616 if (operation == AMDGPU_VA_OP_MAP ||
617 operation == AMDGPU_VA_OP_REPLACE) {
618 r = amdgpu_vm_bo_update(adev, bo_va, false);
623 r = amdgpu_vm_update_pdes(adev, vm, false);
626 if (r && r != -ERESTARTSYS)
627 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
631 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags
633 * @adev: amdgpu_device pointer
634 * @flags: GEM UAPI flags
636 * Returns the GEM UAPI flags mapped into hardware for the ASIC.
638 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)
640 uint64_t pte_flag = 0;
642 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
643 pte_flag |= AMDGPU_PTE_EXECUTABLE;
644 if (flags & AMDGPU_VM_PAGE_READABLE)
645 pte_flag |= AMDGPU_PTE_READABLE;
646 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
647 pte_flag |= AMDGPU_PTE_WRITEABLE;
648 if (flags & AMDGPU_VM_PAGE_PRT)
649 pte_flag |= AMDGPU_PTE_PRT;
650 if (flags & AMDGPU_VM_PAGE_NOALLOC)
651 pte_flag |= AMDGPU_PTE_NOALLOC;
653 if (adev->gmc.gmc_funcs->map_mtype)
654 pte_flag |= amdgpu_gmc_map_mtype(adev,
655 flags & AMDGPU_VM_MTYPE_MASK);
660 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
661 struct drm_file *filp)
663 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
664 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
665 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK |
666 AMDGPU_VM_PAGE_NOALLOC;
667 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
670 struct drm_amdgpu_gem_va *args = data;
671 struct drm_gem_object *gobj;
672 struct amdgpu_device *adev = drm_to_adev(dev);
673 struct amdgpu_fpriv *fpriv = filp->driver_priv;
674 struct amdgpu_bo *abo;
675 struct amdgpu_bo_va *bo_va;
676 struct drm_exec exec;
681 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
683 "va_address 0x%LX is in reserved area 0x%LX\n",
684 args->va_address, AMDGPU_VA_RESERVED_SIZE);
688 if (args->va_address >= AMDGPU_GMC_HOLE_START &&
689 args->va_address < AMDGPU_GMC_HOLE_END) {
691 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
692 args->va_address, AMDGPU_GMC_HOLE_START,
693 AMDGPU_GMC_HOLE_END);
697 args->va_address &= AMDGPU_GMC_HOLE_MASK;
699 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
700 vm_size -= AMDGPU_VA_RESERVED_SIZE;
701 if (args->va_address + args->map_size > vm_size) {
703 "va_address 0x%llx is in top reserved area 0x%llx\n",
704 args->va_address + args->map_size, vm_size);
708 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
709 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n",
714 switch (args->operation) {
715 case AMDGPU_VA_OP_MAP:
716 case AMDGPU_VA_OP_UNMAP:
717 case AMDGPU_VA_OP_CLEAR:
718 case AMDGPU_VA_OP_REPLACE:
721 dev_dbg(dev->dev, "unsupported operation %d\n",
726 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
727 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
728 gobj = drm_gem_object_lookup(filp, args->handle);
731 abo = gem_to_amdgpu_bo(gobj);
737 drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
738 DRM_EXEC_IGNORE_DUPLICATES);
739 drm_exec_until_all_locked(&exec) {
741 r = drm_exec_lock_obj(&exec, gobj);
742 drm_exec_retry_on_contention(&exec);
747 r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2);
748 drm_exec_retry_on_contention(&exec);
754 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
759 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
760 bo_va = fpriv->prt_va;
765 switch (args->operation) {
766 case AMDGPU_VA_OP_MAP:
767 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
768 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
769 args->offset_in_bo, args->map_size,
772 case AMDGPU_VA_OP_UNMAP:
773 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
776 case AMDGPU_VA_OP_CLEAR:
777 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
781 case AMDGPU_VA_OP_REPLACE:
782 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
783 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
784 args->offset_in_bo, args->map_size,
790 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
791 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
795 drm_exec_fini(&exec);
796 drm_gem_object_put(gobj);
800 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
801 struct drm_file *filp)
803 struct amdgpu_device *adev = drm_to_adev(dev);
804 struct drm_amdgpu_gem_op *args = data;
805 struct drm_gem_object *gobj;
806 struct amdgpu_vm_bo_base *base;
807 struct amdgpu_bo *robj;
810 gobj = drm_gem_object_lookup(filp, args->handle);
814 robj = gem_to_amdgpu_bo(gobj);
816 r = amdgpu_bo_reserve(robj, false);
821 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
822 struct drm_amdgpu_gem_create_in info;
823 void __user *out = u64_to_user_ptr(args->value);
825 info.bo_size = robj->tbo.base.size;
826 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT;
827 info.domains = robj->preferred_domains;
828 info.domain_flags = robj->flags;
829 amdgpu_bo_unreserve(robj);
830 if (copy_to_user(out, &info, sizeof(info)))
834 case AMDGPU_GEM_OP_SET_PLACEMENT:
835 if (robj->tbo.base.import_attach &&
836 args->value & AMDGPU_GEM_DOMAIN_VRAM) {
838 amdgpu_bo_unreserve(robj);
841 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
843 amdgpu_bo_unreserve(robj);
846 for (base = robj->vm_bo; base; base = base->next)
847 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),
848 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) {
850 amdgpu_bo_unreserve(robj);
855 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
856 AMDGPU_GEM_DOMAIN_GTT |
857 AMDGPU_GEM_DOMAIN_CPU);
858 robj->allowed_domains = robj->preferred_domains;
859 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
860 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
862 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
863 amdgpu_vm_bo_invalidate(adev, robj, true);
865 amdgpu_bo_unreserve(robj);
868 amdgpu_bo_unreserve(robj);
873 drm_gem_object_put(gobj);
877 static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
898 aligned += pitch_mask;
899 aligned &= ~pitch_mask;
900 return aligned * cpp;
903 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
904 struct drm_device *dev,
905 struct drm_mode_create_dumb *args)
907 struct amdgpu_device *adev = drm_to_adev(dev);
908 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
909 struct drm_gem_object *gobj;
911 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
912 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
913 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
918 * The buffer returned from this function should be cleared, but
919 * it can only be done if the ring is enabled or we'll fail to
922 if (adev->mman.buffer_funcs_enabled)
923 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
925 args->pitch = amdgpu_gem_align_pitch(adev, args->width,
926 DIV_ROUND_UP(args->bpp, 8), 0);
927 args->size = (u64)args->pitch * args->height;
928 args->size = ALIGN(args->size, PAGE_SIZE);
929 domain = amdgpu_bo_get_preferred_domain(adev,
930 amdgpu_display_supported_domains(adev, flags));
931 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
932 ttm_bo_type_device, NULL, &gobj, fpriv->xcp_id + 1);
936 r = drm_gem_handle_create(file_priv, gobj, &handle);
937 /* drop reference from allocate - handle holds it now */
938 drm_gem_object_put(gobj);
942 args->handle = handle;
946 #if defined(CONFIG_DEBUG_FS)
947 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused)
949 struct amdgpu_device *adev = m->private;
950 struct drm_device *dev = adev_to_drm(adev);
951 struct drm_file *file;
954 r = mutex_lock_interruptible(&dev->filelist_mutex);
958 list_for_each_entry(file, &dev->filelist, lhead) {
959 struct task_struct *task;
960 struct drm_gem_object *gobj;
964 * Although we have a valid reference on file->pid, that does
965 * not guarantee that the task_struct who called get_pid() is
966 * still alive (e.g. get_pid(current) => fork() => exit()).
967 * Therefore, we need to protect this ->comm access using RCU.
970 task = pid_task(file->pid, PIDTYPE_TGID);
971 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
972 task ? task->comm : "<unknown>");
975 spin_lock(&file->table_lock);
976 idr_for_each_entry(&file->object_idr, gobj, id) {
977 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
979 amdgpu_bo_print_info(id, bo, m);
981 spin_unlock(&file->table_lock);
984 mutex_unlock(&dev->filelist_mutex);
988 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info);
992 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
994 #if defined(CONFIG_DEBUG_FS)
995 struct drm_minor *minor = adev_to_drm(adev)->primary;
996 struct dentry *root = minor->debugfs_root;
998 debugfs_create_file("amdgpu_gem_info", 0444, root, adev,
999 &amdgpu_debugfs_gem_info_fops);