2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
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21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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25 #include <drm/amdgpu_drm.h>
26 #include <drm/drm_aperture.h>
27 #include <drm/drm_drv.h>
28 #include <drm/drm_gem.h>
29 #include <drm/drm_vblank.h>
30 #include <drm/drm_managed.h>
31 #include "amdgpu_drv.h"
33 #include <drm/drm_pciids.h>
34 #include <linux/module.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_probe_helper.h>
38 #include <linux/mmu_notifier.h>
39 #include <linux/suspend.h>
40 #include <linux/cc_platform.h>
42 #include <linux/dynamic_debug.h>
45 #include "amdgpu_irq.h"
46 #include "amdgpu_dma_buf.h"
47 #include "amdgpu_sched.h"
48 #include "amdgpu_fdinfo.h"
49 #include "amdgpu_amdkfd.h"
51 #include "amdgpu_ras.h"
52 #include "amdgpu_xgmi.h"
53 #include "amdgpu_reset.h"
57 * - 3.0.0 - initial driver
58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
61 * - 3.3.0 - Add VM support for UVD on supported hardware.
62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
63 * - 3.5.0 - Add support for new UVD_NO_OP register.
64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
65 * - 3.7.0 - Add support for VCE clock list packet
66 * - 3.8.0 - Add support raster config init in the kernel
67 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
70 * - 3.12.0 - Add query for double offchip LDS buffers
71 * - 3.13.0 - Add PRT support
72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
73 * - 3.15.0 - Export more gpu info for gfx9
74 * - 3.16.0 - Add reserved vmid support
75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
76 * - 3.18.0 - Export gpu always on cu bitmap
77 * - 3.19.0 - Add support for UVD MJPEG decode
78 * - 3.20.0 - Add support for local BOs
79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
81 * - 3.23.0 - Add query for VRAM lost counter
82 * - 3.24.0 - Add high priority compute support for gfx9
83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
94 * - 3.36.0 - Allow reading more status registers on si/cik
95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
99 * - 3.41.0 - Add video codec query
100 * - 3.42.0 - Add 16bpc fixed point display support
101 * - 3.43.0 - Add device hot plug/unplug support
102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
103 * - 3.45.0 - Add context ioctl stable pstate interface
104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
106 * - 3.48.0 - Add IP discovery version info to HW INFO
107 * 3.49.0 - Add gang submit into CS IOCTL
109 #define KMS_DRIVER_MAJOR 3
110 #define KMS_DRIVER_MINOR 49
111 #define KMS_DRIVER_PATCHLEVEL 0
113 int amdgpu_vram_limit;
114 int amdgpu_vis_vram_limit;
115 int amdgpu_gart_size = -1; /* auto */
116 int amdgpu_gtt_size = -1; /* auto */
117 int amdgpu_moverate = -1; /* auto */
118 int amdgpu_audio = -1;
119 int amdgpu_disp_priority;
121 int amdgpu_pcie_gen2 = -1;
123 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
125 int amdgpu_fw_load_type = -1;
126 int amdgpu_aspm = -1;
127 int amdgpu_runtime_pm = -1;
128 uint amdgpu_ip_block_mask = 0xffffffff;
129 int amdgpu_bapm = -1;
130 int amdgpu_deep_color;
131 int amdgpu_vm_size = -1;
132 int amdgpu_vm_fragment_size = -1;
133 int amdgpu_vm_block_size = -1;
134 int amdgpu_vm_fault_stop;
136 int amdgpu_vm_update_mode = -1;
137 int amdgpu_exp_hw_support;
139 int amdgpu_sched_jobs = 32;
140 int amdgpu_sched_hw_submission = 2;
141 uint amdgpu_pcie_gen_cap;
142 uint amdgpu_pcie_lane_cap;
143 u64 amdgpu_cg_mask = 0xffffffffffffffff;
144 uint amdgpu_pg_mask = 0xffffffff;
145 uint amdgpu_sdma_phase_quantum = 32;
146 char *amdgpu_disable_cu = NULL;
147 char *amdgpu_virtual_display = NULL;
150 * OverDrive(bit 14) disabled by default
151 * GFX DCS(bit 19) disabled by default
153 uint amdgpu_pp_feature_mask = 0xfff7bfff;
154 uint amdgpu_force_long_training;
155 int amdgpu_job_hang_limit;
156 int amdgpu_lbpw = -1;
157 int amdgpu_compute_multipipe = -1;
158 int amdgpu_gpu_recovery = -1; /* auto */
160 uint amdgpu_smu_memory_pool_size;
161 int amdgpu_smu_pptable_id = -1;
163 * FBC (bit 0) disabled by default
164 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
165 * - With this, for multiple monitors in sync(e.g. with the same model),
166 * mclk switching will be allowed. And the mclk will be not foced to the
167 * highest. That helps saving some idle power.
168 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
169 * PSR (bit 3) disabled by default
170 * EDP NO POWER SEQUENCING (bit 4) disabled by default
172 uint amdgpu_dc_feature_mask = 2;
173 uint amdgpu_dc_debug_mask;
174 uint amdgpu_dc_visual_confirm;
175 int amdgpu_async_gfx_ring = 1;
177 int amdgpu_discovery = -1;
180 int amdgpu_noretry = -1;
181 int amdgpu_force_asic_type = -1;
182 int amdgpu_tmz = -1; /* auto */
183 int amdgpu_reset_method = -1; /* auto */
184 int amdgpu_num_kcq = -1;
185 int amdgpu_smartshift_bias;
186 int amdgpu_use_xgmi_p2p = 1;
187 int amdgpu_vcnfw_log;
189 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
191 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
203 struct amdgpu_mgpu_info mgpu_info = {
204 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
205 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
206 mgpu_info.delayed_reset_work,
207 amdgpu_drv_delayed_reset_work_handler, 0),
209 int amdgpu_ras_enable = -1;
210 uint amdgpu_ras_mask = 0xffffffff;
211 int amdgpu_bad_page_threshold = -1;
212 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
213 .timeout_fatal_disable = false,
214 .period = 0x0, /* default to 0x0 (timeout disable) */
218 * DOC: vramlimit (int)
219 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
221 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
222 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
225 * DOC: vis_vramlimit (int)
226 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
228 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
229 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
232 * DOC: gartsize (uint)
233 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
235 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
236 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
240 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
241 * otherwise 3/4 RAM size).
243 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
244 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
247 * DOC: moverate (int)
248 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
250 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
251 module_param_named(moverate, amdgpu_moverate, int, 0600);
255 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
257 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
258 module_param_named(audio, amdgpu_audio, int, 0444);
261 * DOC: disp_priority (int)
262 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
264 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
265 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
269 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
271 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
272 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
275 * DOC: pcie_gen2 (int)
276 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
278 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
279 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
283 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
285 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
286 module_param_named(msi, amdgpu_msi, int, 0444);
289 * DOC: lockup_timeout (string)
290 * Set GPU scheduler timeout value in ms.
292 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
293 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
294 * to the default timeout.
296 * - With one value specified, the setting will apply to all non-compute jobs.
297 * - With multiple values specified, the first one will be for GFX.
298 * The second one is for Compute. The third and fourth ones are
299 * for SDMA and Video.
301 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
302 * jobs is 10000. The timeout for compute is 60000.
304 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
305 "for passthrough or sriov, 10000 for all jobs."
306 " 0: keep default value. negative: infinity timeout), "
307 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
308 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
309 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
313 * Override for dynamic power management setting
314 * (0 = disable, 1 = enable)
315 * The default is -1 (auto).
317 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
318 module_param_named(dpm, amdgpu_dpm, int, 0444);
321 * DOC: fw_load_type (int)
322 * Set different firmware loading type for debugging, if supported.
323 * Set to 0 to force direct loading if supported by the ASIC. Set
324 * to -1 to select the default loading mode for the ASIC, as defined
325 * by the driver. The default is -1 (auto).
327 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
328 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
332 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
334 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
335 module_param_named(aspm, amdgpu_aspm, int, 0444);
339 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
340 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
341 * Setting the value to 0 disables this functionality.
343 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
344 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
347 * DOC: ip_block_mask (uint)
348 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
349 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
350 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
351 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
353 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
354 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
358 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
359 * The default -1 (auto, enabled)
361 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
362 module_param_named(bapm, amdgpu_bapm, int, 0444);
365 * DOC: deep_color (int)
366 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
368 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
369 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
373 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
375 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
376 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
379 * DOC: vm_fragment_size (int)
380 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
382 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
383 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
386 * DOC: vm_block_size (int)
387 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
389 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
390 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
393 * DOC: vm_fault_stop (int)
394 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
396 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
397 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
400 * DOC: vm_debug (int)
401 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
403 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
404 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
407 * DOC: vm_update_mode (int)
408 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
409 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
411 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
412 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
415 * DOC: exp_hw_support (int)
416 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
418 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
419 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
423 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
425 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
426 module_param_named(dc, amdgpu_dc, int, 0444);
429 * DOC: sched_jobs (int)
430 * Override the max number of jobs supported in the sw queue. The default is 32.
432 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
433 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
436 * DOC: sched_hw_submission (int)
437 * Override the max number of HW submissions. The default is 2.
439 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
440 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
443 * DOC: ppfeaturemask (hexint)
444 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
445 * The default is the current set of stable power features.
447 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
448 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
451 * DOC: forcelongtraining (uint)
452 * Force long memory training in resume.
453 * The default is zero, indicates short training in resume.
455 MODULE_PARM_DESC(forcelongtraining, "force memory long training");
456 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
459 * DOC: pcie_gen_cap (uint)
460 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
461 * The default is 0 (automatic for each asic).
463 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
464 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
467 * DOC: pcie_lane_cap (uint)
468 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
469 * The default is 0 (automatic for each asic).
471 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
472 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
475 * DOC: cg_mask (ullong)
476 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
477 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
479 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
480 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
483 * DOC: pg_mask (uint)
484 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
485 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
487 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
488 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
491 * DOC: sdma_phase_quantum (uint)
492 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
494 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
495 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
498 * DOC: disable_cu (charp)
499 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
501 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
502 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
505 * DOC: virtual_display (charp)
506 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
507 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
508 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
509 * device at 26:00.0. The default is NULL.
511 MODULE_PARM_DESC(virtual_display,
512 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
513 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
516 * DOC: job_hang_limit (int)
517 * Set how much time allow a job hang and not drop it. The default is 0.
519 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
520 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
524 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
526 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
527 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
529 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
530 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
533 * DOC: gpu_recovery (int)
534 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
536 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)");
537 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
540 * DOC: emu_mode (int)
541 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
543 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
544 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
547 * DOC: ras_enable (int)
548 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
550 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
551 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
554 * DOC: ras_mask (uint)
555 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
556 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
558 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
559 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
562 * DOC: timeout_fatal_disable (bool)
563 * Disable Watchdog timeout fatal error event
565 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
566 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
569 * DOC: timeout_period (uint)
570 * Modify the watchdog timeout max_cycles as (1 << period)
572 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
573 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
576 * DOC: si_support (int)
577 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
578 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
579 * otherwise using amdgpu driver.
581 #ifdef CONFIG_DRM_AMDGPU_SI
583 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
584 int amdgpu_si_support = 0;
585 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
587 int amdgpu_si_support = 1;
588 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
591 module_param_named(si_support, amdgpu_si_support, int, 0444);
595 * DOC: cik_support (int)
596 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
597 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
598 * otherwise using amdgpu driver.
600 #ifdef CONFIG_DRM_AMDGPU_CIK
602 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
603 int amdgpu_cik_support = 0;
604 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
606 int amdgpu_cik_support = 1;
607 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
610 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
614 * DOC: smu_memory_pool_size (uint)
615 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
616 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
618 MODULE_PARM_DESC(smu_memory_pool_size,
619 "reserve gtt for smu debug usage, 0 = disable,"
620 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
621 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
624 * DOC: async_gfx_ring (int)
625 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
627 MODULE_PARM_DESC(async_gfx_ring,
628 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
629 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
633 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
635 MODULE_PARM_DESC(mcbp,
636 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
637 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
640 * DOC: discovery (int)
641 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
642 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
644 MODULE_PARM_DESC(discovery,
645 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
646 module_param_named(discovery, amdgpu_discovery, int, 0444);
650 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
651 * (0 = disabled (default), 1 = enabled)
653 MODULE_PARM_DESC(mes,
654 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
655 module_param_named(mes, amdgpu_mes, int, 0444);
659 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
660 * (0 = disabled (default), 1 = enabled)
662 MODULE_PARM_DESC(mes_kiq,
663 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
664 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
668 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
669 * do not support per-process XNACK this also disables retry page faults.
670 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
672 MODULE_PARM_DESC(noretry,
673 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
674 module_param_named(noretry, amdgpu_noretry, int, 0644);
677 * DOC: force_asic_type (int)
678 * A non negative value used to specify the asic type for all supported GPUs.
680 MODULE_PARM_DESC(force_asic_type,
681 "A non negative value used to specify the asic type for all supported GPUs");
682 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
685 * DOC: use_xgmi_p2p (int)
686 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
688 MODULE_PARM_DESC(use_xgmi_p2p,
689 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
690 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
693 #ifdef CONFIG_HSA_AMD
695 * DOC: sched_policy (int)
696 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
697 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
698 * assigns queues to HQDs.
700 int sched_policy = KFD_SCHED_POLICY_HWS;
701 module_param(sched_policy, int, 0444);
702 MODULE_PARM_DESC(sched_policy,
703 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
706 * DOC: hws_max_conc_proc (int)
707 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
708 * number of VMIDs assigned to the HWS, which is also the default.
710 int hws_max_conc_proc = -1;
711 module_param(hws_max_conc_proc, int, 0444);
712 MODULE_PARM_DESC(hws_max_conc_proc,
713 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
716 * DOC: cwsr_enable (int)
717 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
718 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
722 module_param(cwsr_enable, int, 0444);
723 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
726 * DOC: max_num_of_queues_per_device (int)
727 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
730 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
731 module_param(max_num_of_queues_per_device, int, 0444);
732 MODULE_PARM_DESC(max_num_of_queues_per_device,
733 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
736 * DOC: send_sigterm (int)
737 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
738 * but just print errors on dmesg. Setting 1 enables sending sigterm.
741 module_param(send_sigterm, int, 0444);
742 MODULE_PARM_DESC(send_sigterm,
743 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
746 * DOC: debug_largebar (int)
747 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
748 * system. This limits the VRAM size reported to ROCm applications to the visible
749 * size, usually 256MB.
750 * Default value is 0, diabled.
753 module_param(debug_largebar, int, 0444);
754 MODULE_PARM_DESC(debug_largebar,
755 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
758 * DOC: ignore_crat (int)
759 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
760 * table to get information about AMD APUs. This option can serve as a workaround on
761 * systems with a broken CRAT table.
763 * Default is auto (according to asic type, iommu_v2, and crat table, to decide
767 module_param(ignore_crat, int, 0444);
768 MODULE_PARM_DESC(ignore_crat,
769 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
772 * DOC: halt_if_hws_hang (int)
773 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
774 * Setting 1 enables halt on hang.
776 int halt_if_hws_hang;
777 module_param(halt_if_hws_hang, int, 0644);
778 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
781 * DOC: hws_gws_support(bool)
782 * Assume that HWS supports GWS barriers regardless of what firmware version
783 * check says. Default value: false (rely on MEC2 firmware version check).
785 bool hws_gws_support;
786 module_param(hws_gws_support, bool, 0444);
787 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
790 * DOC: queue_preemption_timeout_ms (int)
791 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
793 int queue_preemption_timeout_ms = 9000;
794 module_param(queue_preemption_timeout_ms, int, 0644);
795 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
798 * DOC: debug_evictions(bool)
799 * Enable extra debug messages to help determine the cause of evictions
801 bool debug_evictions;
802 module_param(debug_evictions, bool, 0644);
803 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
806 * DOC: no_system_mem_limit(bool)
807 * Disable system memory limit, to support multiple process shared memory
809 bool no_system_mem_limit;
810 module_param(no_system_mem_limit, bool, 0644);
811 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
814 * DOC: no_queue_eviction_on_vm_fault (int)
815 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
817 int amdgpu_no_queue_eviction_on_vm_fault = 0;
818 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
819 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
823 * DOC: pcie_p2p (bool)
824 * Enable PCIe P2P (requires large-BAR). Default value: true (on)
826 #ifdef CONFIG_HSA_AMD_P2P
827 bool pcie_p2p = true;
828 module_param(pcie_p2p, bool, 0444);
829 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
833 * DOC: dcfeaturemask (uint)
834 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
835 * The default is the current set of stable display features.
837 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
838 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
841 * DOC: dcdebugmask (uint)
842 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
844 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
845 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
847 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
848 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
851 * DOC: abmlevel (uint)
852 * Override the default ABM (Adaptive Backlight Management) level used for DC
853 * enabled hardware. Requires DMCU to be supported and loaded.
854 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
855 * default. Values 1-4 control the maximum allowable brightness reduction via
856 * the ABM algorithm, with 1 being the least reduction and 4 being the most
859 * Defaults to 0, or disabled. Userspace can still override this level later
862 uint amdgpu_dm_abm_level;
863 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
864 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
866 int amdgpu_backlight = -1;
867 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
868 module_param_named(backlight, amdgpu_backlight, bint, 0444);
872 * Trusted Memory Zone (TMZ) is a method to protect data being written
873 * to or read from memory.
875 * The default value: 0 (off). TODO: change to auto till it is completed.
877 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
878 module_param_named(tmz, amdgpu_tmz, int, 0444);
881 * DOC: reset_method (int)
882 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
884 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
885 module_param_named(reset_method, amdgpu_reset_method, int, 0444);
888 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
889 * threshold value of faulty pages detected by RAS ECC, which may
890 * result in the GPU entering bad status when the number of total
891 * faulty pages by ECC exceeds the threshold value.
893 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)");
894 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
896 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
897 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
900 * DOC: vcnfw_log (int)
901 * Enable vcnfw log output for debugging, the default is disabled.
903 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
904 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
907 * DOC: smu_pptable_id (int)
908 * Used to override pptable id. id = 0 use VBIOS pptable.
909 * id > 0 use the soft pptable with specicfied id.
911 MODULE_PARM_DESC(smu_pptable_id,
912 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
913 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
915 /* These devices are not supported by amdgpu.
916 * They are supported by the mach64, r128, radeon drivers
918 static const u16 amdgpu_unsupported_pciidlist[] = {
1543 /* radeon secondary ids */
1626 static const struct pci_device_id pciidlist[] = {
1627 #ifdef CONFIG_DRM_AMDGPU_SI
1628 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1629 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1630 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1631 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1632 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1633 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1634 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1635 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1636 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1637 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1638 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1639 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1640 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1641 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1642 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1643 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1644 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1645 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1646 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1647 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1648 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1649 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1650 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1651 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1652 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1653 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1654 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1655 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1656 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1657 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1658 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1659 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1660 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1661 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1662 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1663 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1664 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1665 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1666 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1667 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1668 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1669 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1670 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1671 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1672 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1673 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1674 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1675 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1676 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1677 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1678 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1679 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1680 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1681 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1682 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1683 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1684 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1685 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1686 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1687 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1688 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1689 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1690 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1691 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1692 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1693 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1694 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1695 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1696 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1697 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1698 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1699 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1701 #ifdef CONFIG_DRM_AMDGPU_CIK
1703 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1704 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1705 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1706 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1707 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1708 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1709 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1710 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1711 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1712 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1713 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1714 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1715 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1716 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1717 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1718 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1719 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1720 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1721 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1722 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1723 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1724 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1726 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1727 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1728 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1729 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1730 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1731 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1732 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1733 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1734 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1735 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1736 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1738 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1739 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1740 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1741 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1742 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1743 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1744 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1745 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1746 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1747 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1748 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1749 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1751 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1752 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1753 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1754 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1755 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1756 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1757 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1758 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1759 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1760 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1761 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1762 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1763 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1764 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1765 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1766 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1768 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1769 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1770 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1771 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1772 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1773 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1774 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1775 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1776 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1777 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1778 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1779 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1780 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1781 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1782 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1783 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1786 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1787 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1788 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1789 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1790 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1792 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1793 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1794 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1795 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1796 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1797 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1798 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1799 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1800 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1802 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1803 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1805 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1806 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1807 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1808 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1809 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1811 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1813 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1814 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1815 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1816 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1817 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1818 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1819 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1820 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1821 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1823 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1824 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1825 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1826 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1827 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1828 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1829 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1830 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1831 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1832 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1833 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1834 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1835 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1837 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1838 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1839 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1840 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1841 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1842 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1843 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1844 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1846 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1847 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1848 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1850 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1851 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1852 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1853 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1854 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1855 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1856 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1857 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1858 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1859 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1860 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1861 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1862 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1863 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1864 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1866 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1867 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1868 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1869 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1870 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1872 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1873 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1874 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1875 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1876 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1877 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1878 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1880 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1881 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1883 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1884 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1885 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1886 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1888 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1889 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1890 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1891 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1892 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1893 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1894 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1895 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1897 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1898 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1899 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1900 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1903 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1904 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1905 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1906 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1909 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1910 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1912 /* Sienna_Cichlid */
1913 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1914 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1915 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1916 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1917 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1918 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1919 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1920 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1921 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1922 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1923 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1924 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1925 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1928 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
1931 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1932 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1935 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1936 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1937 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1938 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1939 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1940 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1941 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1942 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1943 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1945 /* DIMGREY_CAVEFISH */
1946 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1947 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1948 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1949 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1950 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1951 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1952 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1953 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1954 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1955 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1956 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1957 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1960 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1961 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1962 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1963 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1965 /* CYAN_SKILLFISH */
1966 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1967 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1970 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1971 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1972 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1973 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1974 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1975 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1977 { PCI_DEVICE(0x1002, PCI_ANY_ID),
1978 .class = PCI_CLASS_DISPLAY_VGA << 8,
1979 .class_mask = 0xffffff,
1980 .driver_data = CHIP_IP_DISCOVERY },
1982 { PCI_DEVICE(0x1002, PCI_ANY_ID),
1983 .class = PCI_CLASS_DISPLAY_OTHER << 8,
1984 .class_mask = 0xffffff,
1985 .driver_data = CHIP_IP_DISCOVERY },
1990 MODULE_DEVICE_TABLE(pci, pciidlist);
1992 static const struct drm_driver amdgpu_kms_driver;
1994 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
1996 struct pci_dev *p = NULL;
2004 for (i = 1; i < 4; i++) {
2005 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2006 adev->pdev->bus->number, i);
2008 pm_runtime_get_sync(&p->dev);
2009 pm_runtime_mark_last_busy(&p->dev);
2010 pm_runtime_put_autosuspend(&p->dev);
2016 static int amdgpu_pci_probe(struct pci_dev *pdev,
2017 const struct pci_device_id *ent)
2019 struct drm_device *ddev;
2020 struct amdgpu_device *adev;
2021 unsigned long flags = ent->driver_data;
2022 int ret, retry = 0, i;
2023 bool supports_atomic = false;
2025 /* skip devices which are owned by radeon */
2026 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2027 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2031 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2034 if (amdgpu_virtual_display ||
2035 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2036 supports_atomic = true;
2038 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2039 DRM_INFO("This hardware requires experimental hardware support.\n"
2040 "See modparam exp_hw_support\n");
2044 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2045 * however, SME requires an indirect IOMMU mapping because the encryption
2046 * bit is beyond the DMA mask of the chip.
2048 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2049 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2050 dev_info(&pdev->dev,
2051 "SME is not compatible with RAVEN\n");
2055 #ifdef CONFIG_DRM_AMDGPU_SI
2056 if (!amdgpu_si_support) {
2057 switch (flags & AMD_ASIC_MASK) {
2063 dev_info(&pdev->dev,
2064 "SI support provided by radeon.\n");
2065 dev_info(&pdev->dev,
2066 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2072 #ifdef CONFIG_DRM_AMDGPU_CIK
2073 if (!amdgpu_cik_support) {
2074 switch (flags & AMD_ASIC_MASK) {
2080 dev_info(&pdev->dev,
2081 "CIK support provided by radeon.\n");
2082 dev_info(&pdev->dev,
2083 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2090 /* Get rid of things like offb */
2091 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver);
2095 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2097 return PTR_ERR(adev);
2099 adev->dev = &pdev->dev;
2101 ddev = adev_to_drm(adev);
2103 if (!supports_atomic)
2104 ddev->driver_features &= ~DRIVER_ATOMIC;
2106 ret = pci_enable_device(pdev);
2110 pci_set_drvdata(pdev, ddev);
2112 ret = amdgpu_driver_load_kms(adev, ent->driver_data);
2117 ret = drm_dev_register(ddev, ent->driver_data);
2118 if (ret == -EAGAIN && ++retry <= 3) {
2119 DRM_INFO("retry init %d\n", retry);
2120 /* Don't request EX mode too frequently which is attacking */
2128 * 1. don't init fbdev on hw without DCE
2129 * 2. don't init fbdev if there are no connectors
2131 if (adev->mode_info.mode_config_initialized &&
2132 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2133 /* select 8 bpp console on low vram cards */
2134 if (adev->gmc.real_vram_size <= (32*1024*1024))
2135 drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2137 drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2140 ret = amdgpu_debugfs_init(adev);
2142 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2144 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2145 /* only need to skip on ATPX */
2146 if (amdgpu_device_supports_px(ddev))
2147 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2148 /* we want direct complete for BOCO */
2149 if (amdgpu_device_supports_boco(ddev))
2150 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2151 DPM_FLAG_SMART_SUSPEND |
2152 DPM_FLAG_MAY_SKIP_RESUME);
2153 pm_runtime_use_autosuspend(ddev->dev);
2154 pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2156 pm_runtime_allow(ddev->dev);
2158 pm_runtime_mark_last_busy(ddev->dev);
2159 pm_runtime_put_autosuspend(ddev->dev);
2162 * For runpm implemented via BACO, PMFW will handle the
2163 * timing for BACO in and out:
2164 * - put ASIC into BACO state only when both video and
2165 * audio functions are in D3 state.
2166 * - pull ASIC out of BACO state when either video or
2167 * audio function is in D0 state.
2168 * Also, at startup, PMFW assumes both functions are in
2171 * So if snd driver was loaded prior to amdgpu driver
2172 * and audio function was put into D3 state, there will
2173 * be no PMFW-aware D-state transition(D0->D3) on runpm
2174 * suspend. Thus the BACO will be not correctly kicked in.
2176 * Via amdgpu_get_secondary_funcs(), the audio dev is put
2177 * into D0 state. Then there will be a PMFW-aware D-state
2178 * transition(D0->D3) on runpm suspend.
2180 if (amdgpu_device_supports_baco(ddev) &&
2181 !(adev->flags & AMD_IS_APU) &&
2182 (adev->asic_type >= CHIP_NAVI10))
2183 amdgpu_get_secondary_funcs(adev);
2189 pci_disable_device(pdev);
2194 amdgpu_pci_remove(struct pci_dev *pdev)
2196 struct drm_device *dev = pci_get_drvdata(pdev);
2197 struct amdgpu_device *adev = drm_to_adev(dev);
2199 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2200 pm_runtime_get_sync(dev->dev);
2201 pm_runtime_forbid(dev->dev);
2204 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) {
2205 bool need_to_reset_gpu = false;
2207 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2208 struct amdgpu_hive_info *hive;
2210 hive = amdgpu_get_xgmi_hive(adev);
2211 if (hive->device_remove_count == 0)
2212 need_to_reset_gpu = true;
2213 hive->device_remove_count++;
2214 amdgpu_put_xgmi_hive(hive);
2216 need_to_reset_gpu = true;
2219 /* Workaround for ASICs need to reset SMU.
2220 * Called only when the first device is removed.
2222 if (need_to_reset_gpu) {
2223 struct amdgpu_reset_context reset_context;
2225 adev->shutdown = true;
2226 memset(&reset_context, 0, sizeof(reset_context));
2227 reset_context.method = AMD_RESET_METHOD_NONE;
2228 reset_context.reset_req_dev = adev;
2229 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2230 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags);
2231 amdgpu_device_gpu_recover(adev, NULL, &reset_context);
2235 amdgpu_driver_unload_kms(dev);
2237 drm_dev_unplug(dev);
2240 * Flush any in flight DMA operations from device.
2241 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2242 * StatusTransactions Pending bit.
2244 pci_disable_device(pdev);
2245 pci_wait_for_pending_transaction(pdev);
2249 amdgpu_pci_shutdown(struct pci_dev *pdev)
2251 struct drm_device *dev = pci_get_drvdata(pdev);
2252 struct amdgpu_device *adev = drm_to_adev(dev);
2254 if (amdgpu_ras_intr_triggered())
2257 /* if we are running in a VM, make sure the device
2258 * torn down properly on reboot/shutdown.
2259 * unfortunately we can't detect certain
2260 * hypervisors so just do this all the time.
2262 if (!amdgpu_passthrough(adev))
2263 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2264 amdgpu_device_ip_suspend(adev);
2265 adev->mp1_state = PP_MP1_STATE_NONE;
2269 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2271 * @work: work_struct.
2273 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2275 struct list_head device_list;
2276 struct amdgpu_device *adev;
2278 struct amdgpu_reset_context reset_context;
2280 memset(&reset_context, 0, sizeof(reset_context));
2282 mutex_lock(&mgpu_info.mutex);
2283 if (mgpu_info.pending_reset == true) {
2284 mutex_unlock(&mgpu_info.mutex);
2287 mgpu_info.pending_reset = true;
2288 mutex_unlock(&mgpu_info.mutex);
2290 /* Use a common context, just need to make sure full reset is done */
2291 reset_context.method = AMD_RESET_METHOD_NONE;
2292 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2294 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2295 adev = mgpu_info.gpu_ins[i].adev;
2296 reset_context.reset_req_dev = adev;
2297 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
2299 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2300 r, adev_to_drm(adev)->unique);
2302 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2305 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2306 adev = mgpu_info.gpu_ins[i].adev;
2307 flush_work(&adev->xgmi_reset_work);
2308 adev->gmc.xgmi.pending_reset = false;
2311 /* reset function will rebuild the xgmi hive info , clear it now */
2312 for (i = 0; i < mgpu_info.num_dgpu; i++)
2313 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2315 INIT_LIST_HEAD(&device_list);
2317 for (i = 0; i < mgpu_info.num_dgpu; i++)
2318 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2320 /* unregister the GPU first, reset function will add them back */
2321 list_for_each_entry(adev, &device_list, reset_list)
2322 amdgpu_unregister_gpu_instance(adev);
2324 /* Use a common context, just need to make sure full reset is done */
2325 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2326 r = amdgpu_do_asic_reset(&device_list, &reset_context);
2329 DRM_ERROR("reinit gpus failure");
2332 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2333 adev = mgpu_info.gpu_ins[i].adev;
2334 if (!adev->kfd.init_complete)
2335 amdgpu_amdkfd_device_init(adev);
2336 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2341 static int amdgpu_pmops_prepare(struct device *dev)
2343 struct drm_device *drm_dev = dev_get_drvdata(dev);
2344 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2346 /* Return a positive number here so
2347 * DPM_FLAG_SMART_SUSPEND works properly
2349 if (amdgpu_device_supports_boco(drm_dev))
2350 return pm_runtime_suspended(dev);
2352 /* if we will not support s3 or s2i for the device
2355 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2356 !amdgpu_acpi_is_s3_active(adev))
2362 static void amdgpu_pmops_complete(struct device *dev)
2367 static int amdgpu_pmops_suspend(struct device *dev)
2369 struct drm_device *drm_dev = dev_get_drvdata(dev);
2370 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2372 if (amdgpu_acpi_is_s0ix_active(adev))
2373 adev->in_s0ix = true;
2376 return amdgpu_device_suspend(drm_dev, true);
2379 static int amdgpu_pmops_suspend_noirq(struct device *dev)
2381 struct drm_device *drm_dev = dev_get_drvdata(dev);
2382 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2384 if (amdgpu_acpi_should_gpu_reset(adev))
2385 return amdgpu_asic_reset(adev);
2390 static int amdgpu_pmops_resume(struct device *dev)
2392 struct drm_device *drm_dev = dev_get_drvdata(dev);
2393 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2396 /* Avoids registers access if device is physically gone */
2397 if (!pci_device_is_present(adev->pdev))
2398 adev->no_hw_access = true;
2400 r = amdgpu_device_resume(drm_dev, true);
2401 if (amdgpu_acpi_is_s0ix_active(adev))
2402 adev->in_s0ix = false;
2404 adev->in_s3 = false;
2408 static int amdgpu_pmops_freeze(struct device *dev)
2410 struct drm_device *drm_dev = dev_get_drvdata(dev);
2411 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2415 r = amdgpu_device_suspend(drm_dev, true);
2416 adev->in_s4 = false;
2419 return amdgpu_asic_reset(adev);
2422 static int amdgpu_pmops_thaw(struct device *dev)
2424 struct drm_device *drm_dev = dev_get_drvdata(dev);
2426 return amdgpu_device_resume(drm_dev, true);
2429 static int amdgpu_pmops_poweroff(struct device *dev)
2431 struct drm_device *drm_dev = dev_get_drvdata(dev);
2433 return amdgpu_device_suspend(drm_dev, true);
2436 static int amdgpu_pmops_restore(struct device *dev)
2438 struct drm_device *drm_dev = dev_get_drvdata(dev);
2440 return amdgpu_device_resume(drm_dev, true);
2443 static int amdgpu_runtime_idle_check_display(struct device *dev)
2445 struct pci_dev *pdev = to_pci_dev(dev);
2446 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2447 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2449 if (adev->mode_info.num_crtc) {
2450 struct drm_connector *list_connector;
2451 struct drm_connector_list_iter iter;
2454 /* XXX: Return busy if any displays are connected to avoid
2455 * possible display wakeups after runtime resume due to
2456 * hotplug events in case any displays were connected while
2457 * the GPU was in suspend. Remove this once that is fixed.
2459 mutex_lock(&drm_dev->mode_config.mutex);
2460 drm_connector_list_iter_begin(drm_dev, &iter);
2461 drm_for_each_connector_iter(list_connector, &iter) {
2462 if (list_connector->status == connector_status_connected) {
2467 drm_connector_list_iter_end(&iter);
2468 mutex_unlock(&drm_dev->mode_config.mutex);
2473 if (amdgpu_device_has_dc_support(adev)) {
2474 struct drm_crtc *crtc;
2476 drm_for_each_crtc(crtc, drm_dev) {
2477 drm_modeset_lock(&crtc->mutex, NULL);
2478 if (crtc->state->active)
2480 drm_modeset_unlock(&crtc->mutex);
2485 mutex_lock(&drm_dev->mode_config.mutex);
2486 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2488 drm_connector_list_iter_begin(drm_dev, &iter);
2489 drm_for_each_connector_iter(list_connector, &iter) {
2490 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2496 drm_connector_list_iter_end(&iter);
2498 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2499 mutex_unlock(&drm_dev->mode_config.mutex);
2508 static int amdgpu_pmops_runtime_suspend(struct device *dev)
2510 struct pci_dev *pdev = to_pci_dev(dev);
2511 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2512 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2515 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2516 pm_runtime_forbid(dev);
2520 ret = amdgpu_runtime_idle_check_display(dev);
2524 /* wait for all rings to drain before suspending */
2525 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2526 struct amdgpu_ring *ring = adev->rings[i];
2527 if (ring && ring->sched.ready) {
2528 ret = amdgpu_fence_wait_empty(ring);
2534 adev->in_runpm = true;
2535 if (amdgpu_device_supports_px(drm_dev))
2536 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2539 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2540 * proper cleanups and put itself into a state ready for PNP. That
2541 * can address some random resuming failure observed on BOCO capable
2543 * TODO: this may be also needed for PX capable platform.
2545 if (amdgpu_device_supports_boco(drm_dev))
2546 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2548 ret = amdgpu_device_suspend(drm_dev, false);
2550 adev->in_runpm = false;
2551 if (amdgpu_device_supports_boco(drm_dev))
2552 adev->mp1_state = PP_MP1_STATE_NONE;
2556 if (amdgpu_device_supports_boco(drm_dev))
2557 adev->mp1_state = PP_MP1_STATE_NONE;
2559 if (amdgpu_device_supports_px(drm_dev)) {
2560 /* Only need to handle PCI state in the driver for ATPX
2561 * PCI core handles it for _PR3.
2563 amdgpu_device_cache_pci_state(pdev);
2564 pci_disable_device(pdev);
2565 pci_ignore_hotplug(pdev);
2566 pci_set_power_state(pdev, PCI_D3cold);
2567 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2568 } else if (amdgpu_device_supports_boco(drm_dev)) {
2570 } else if (amdgpu_device_supports_baco(drm_dev)) {
2571 amdgpu_device_baco_enter(drm_dev);
2577 static int amdgpu_pmops_runtime_resume(struct device *dev)
2579 struct pci_dev *pdev = to_pci_dev(dev);
2580 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2581 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2584 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
2587 /* Avoids registers access if device is physically gone */
2588 if (!pci_device_is_present(adev->pdev))
2589 adev->no_hw_access = true;
2591 if (amdgpu_device_supports_px(drm_dev)) {
2592 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2594 /* Only need to handle PCI state in the driver for ATPX
2595 * PCI core handles it for _PR3.
2597 pci_set_power_state(pdev, PCI_D0);
2598 amdgpu_device_load_pci_state(pdev);
2599 ret = pci_enable_device(pdev);
2602 pci_set_master(pdev);
2603 } else if (amdgpu_device_supports_boco(drm_dev)) {
2604 /* Only need to handle PCI state in the driver for ATPX
2605 * PCI core handles it for _PR3.
2607 pci_set_master(pdev);
2608 } else if (amdgpu_device_supports_baco(drm_dev)) {
2609 amdgpu_device_baco_exit(drm_dev);
2611 ret = amdgpu_device_resume(drm_dev, false);
2613 if (amdgpu_device_supports_px(drm_dev))
2614 pci_disable_device(pdev);
2618 if (amdgpu_device_supports_px(drm_dev))
2619 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2620 adev->in_runpm = false;
2624 static int amdgpu_pmops_runtime_idle(struct device *dev)
2626 struct drm_device *drm_dev = dev_get_drvdata(dev);
2627 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2628 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2631 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2632 pm_runtime_forbid(dev);
2636 ret = amdgpu_runtime_idle_check_display(dev);
2638 pm_runtime_mark_last_busy(dev);
2639 pm_runtime_autosuspend(dev);
2643 long amdgpu_drm_ioctl(struct file *filp,
2644 unsigned int cmd, unsigned long arg)
2646 struct drm_file *file_priv = filp->private_data;
2647 struct drm_device *dev;
2649 dev = file_priv->minor->dev;
2650 ret = pm_runtime_get_sync(dev->dev);
2654 ret = drm_ioctl(filp, cmd, arg);
2656 pm_runtime_mark_last_busy(dev->dev);
2658 pm_runtime_put_autosuspend(dev->dev);
2662 static const struct dev_pm_ops amdgpu_pm_ops = {
2663 .prepare = amdgpu_pmops_prepare,
2664 .complete = amdgpu_pmops_complete,
2665 .suspend = amdgpu_pmops_suspend,
2666 .suspend_noirq = amdgpu_pmops_suspend_noirq,
2667 .resume = amdgpu_pmops_resume,
2668 .freeze = amdgpu_pmops_freeze,
2669 .thaw = amdgpu_pmops_thaw,
2670 .poweroff = amdgpu_pmops_poweroff,
2671 .restore = amdgpu_pmops_restore,
2672 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2673 .runtime_resume = amdgpu_pmops_runtime_resume,
2674 .runtime_idle = amdgpu_pmops_runtime_idle,
2677 static int amdgpu_flush(struct file *f, fl_owner_t id)
2679 struct drm_file *file_priv = f->private_data;
2680 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2681 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
2683 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2684 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
2686 return timeout >= 0 ? 0 : timeout;
2689 static const struct file_operations amdgpu_driver_kms_fops = {
2690 .owner = THIS_MODULE,
2692 .flush = amdgpu_flush,
2693 .release = drm_release,
2694 .unlocked_ioctl = amdgpu_drm_ioctl,
2695 .mmap = drm_gem_mmap,
2698 #ifdef CONFIG_COMPAT
2699 .compat_ioctl = amdgpu_kms_compat_ioctl,
2701 #ifdef CONFIG_PROC_FS
2702 .show_fdinfo = amdgpu_show_fdinfo
2706 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2708 struct drm_file *file;
2713 if (filp->f_op != &amdgpu_driver_kms_fops) {
2717 file = filp->private_data;
2718 *fpriv = file->driver_priv;
2722 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2723 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2724 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2725 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2726 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2727 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2728 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2730 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2731 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2732 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2733 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2734 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2735 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2736 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2737 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2738 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2739 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2742 static const struct drm_driver amdgpu_kms_driver = {
2746 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2747 DRIVER_SYNCOBJ_TIMELINE,
2748 .open = amdgpu_driver_open_kms,
2749 .postclose = amdgpu_driver_postclose_kms,
2750 .lastclose = amdgpu_driver_lastclose_kms,
2751 .ioctls = amdgpu_ioctls_kms,
2752 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2753 .dumb_create = amdgpu_mode_dumb_create,
2754 .dumb_map_offset = amdgpu_mode_dumb_mmap,
2755 .fops = &amdgpu_driver_kms_fops,
2756 .release = &amdgpu_driver_release_kms,
2758 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2759 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2760 .gem_prime_import = amdgpu_gem_prime_import,
2761 .gem_prime_mmap = drm_gem_prime_mmap,
2763 .name = DRIVER_NAME,
2764 .desc = DRIVER_DESC,
2765 .date = DRIVER_DATE,
2766 .major = KMS_DRIVER_MAJOR,
2767 .minor = KMS_DRIVER_MINOR,
2768 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2771 static struct pci_error_handlers amdgpu_pci_err_handler = {
2772 .error_detected = amdgpu_pci_error_detected,
2773 .mmio_enabled = amdgpu_pci_mmio_enabled,
2774 .slot_reset = amdgpu_pci_slot_reset,
2775 .resume = amdgpu_pci_resume,
2778 extern const struct attribute_group amdgpu_vram_mgr_attr_group;
2779 extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
2780 extern const struct attribute_group amdgpu_vbios_version_attr_group;
2782 static const struct attribute_group *amdgpu_sysfs_groups[] = {
2783 &amdgpu_vram_mgr_attr_group,
2784 &amdgpu_gtt_mgr_attr_group,
2785 &amdgpu_vbios_version_attr_group,
2790 static struct pci_driver amdgpu_kms_pci_driver = {
2791 .name = DRIVER_NAME,
2792 .id_table = pciidlist,
2793 .probe = amdgpu_pci_probe,
2794 .remove = amdgpu_pci_remove,
2795 .shutdown = amdgpu_pci_shutdown,
2796 .driver.pm = &amdgpu_pm_ops,
2797 .err_handler = &amdgpu_pci_err_handler,
2798 .dev_groups = amdgpu_sysfs_groups,
2801 static int __init amdgpu_init(void)
2805 if (drm_firmware_drivers_only())
2808 r = amdgpu_sync_init();
2812 r = amdgpu_fence_slab_init();
2816 DRM_INFO("amdgpu kernel modesetting enabled.\n");
2817 amdgpu_register_atpx_handler();
2818 amdgpu_acpi_detect();
2820 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2821 amdgpu_amdkfd_init();
2823 /* let modprobe override vga console setting */
2824 return pci_register_driver(&amdgpu_kms_pci_driver);
2833 static void __exit amdgpu_exit(void)
2835 amdgpu_amdkfd_fini();
2836 pci_unregister_driver(&amdgpu_kms_pci_driver);
2837 amdgpu_unregister_atpx_handler();
2839 amdgpu_fence_slab_fini();
2840 mmu_notifier_synchronize();
2843 module_init(amdgpu_init);
2844 module_exit(amdgpu_exit);
2846 MODULE_AUTHOR(DRIVER_AUTHOR);
2847 MODULE_DESCRIPTION(DRIVER_DESC);
2848 MODULE_LICENSE("GPL and additional rights");
projects / platform / kernel / linux-starfive.git / blob