2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
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25 #include <drm/amdgpu_drm.h>
26 #include <drm/drm_drv.h>
27 #include <drm/drm_fbdev_generic.h>
28 #include <drm/drm_gem.h>
29 #include <drm/drm_vblank.h>
30 #include <drm/drm_managed.h>
31 #include "amdgpu_drv.h"
33 #include <drm/drm_pciids.h>
34 #include <linux/module.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_probe_helper.h>
38 #include <linux/mmu_notifier.h>
39 #include <linux/suspend.h>
40 #include <linux/cc_platform.h>
41 #include <linux/dynamic_debug.h>
44 #include "amdgpu_irq.h"
45 #include "amdgpu_dma_buf.h"
46 #include "amdgpu_sched.h"
47 #include "amdgpu_fdinfo.h"
48 #include "amdgpu_amdkfd.h"
50 #include "amdgpu_ras.h"
51 #include "amdgpu_xgmi.h"
52 #include "amdgpu_reset.h"
56 * - 3.0.0 - initial driver
57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
60 * - 3.3.0 - Add VM support for UVD on supported hardware.
61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
62 * - 3.5.0 - Add support for new UVD_NO_OP register.
63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
64 * - 3.7.0 - Add support for VCE clock list packet
65 * - 3.8.0 - Add support raster config init in the kernel
66 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
69 * - 3.12.0 - Add query for double offchip LDS buffers
70 * - 3.13.0 - Add PRT support
71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
72 * - 3.15.0 - Export more gpu info for gfx9
73 * - 3.16.0 - Add reserved vmid support
74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
75 * - 3.18.0 - Export gpu always on cu bitmap
76 * - 3.19.0 - Add support for UVD MJPEG decode
77 * - 3.20.0 - Add support for local BOs
78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
80 * - 3.23.0 - Add query for VRAM lost counter
81 * - 3.24.0 - Add high priority compute support for gfx9
82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
84 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
93 * - 3.36.0 - Allow reading more status registers on si/cik
94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
98 * - 3.41.0 - Add video codec query
99 * - 3.42.0 - Add 16bpc fixed point display support
100 * - 3.43.0 - Add device hot plug/unplug support
101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
102 * - 3.45.0 - Add context ioctl stable pstate interface
103 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
104 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
105 * - 3.48.0 - Add IP discovery version info to HW INFO
106 * - 3.49.0 - Add gang submit into CS IOCTL
107 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
108 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
109 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
110 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
111 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size,
112 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi
113 * 3.53.0 - Support for GFX11 CP GFX shadowing
115 #define KMS_DRIVER_MAJOR 3
116 #define KMS_DRIVER_MINOR 53
117 #define KMS_DRIVER_PATCHLEVEL 0
119 unsigned int amdgpu_vram_limit = UINT_MAX;
120 int amdgpu_vis_vram_limit;
121 int amdgpu_gart_size = -1; /* auto */
122 int amdgpu_gtt_size = -1; /* auto */
123 int amdgpu_moverate = -1; /* auto */
124 int amdgpu_audio = -1;
125 int amdgpu_disp_priority;
127 int amdgpu_pcie_gen2 = -1;
129 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
131 int amdgpu_fw_load_type = -1;
132 int amdgpu_aspm = -1;
133 int amdgpu_runtime_pm = -1;
134 uint amdgpu_ip_block_mask = 0xffffffff;
135 int amdgpu_bapm = -1;
136 int amdgpu_deep_color;
137 int amdgpu_vm_size = -1;
138 int amdgpu_vm_fragment_size = -1;
139 int amdgpu_vm_block_size = -1;
140 int amdgpu_vm_fault_stop;
142 int amdgpu_vm_update_mode = -1;
143 int amdgpu_exp_hw_support;
145 int amdgpu_sched_jobs = 32;
146 int amdgpu_sched_hw_submission = 2;
147 uint amdgpu_pcie_gen_cap;
148 uint amdgpu_pcie_lane_cap;
149 u64 amdgpu_cg_mask = 0xffffffffffffffff;
150 uint amdgpu_pg_mask = 0xffffffff;
151 uint amdgpu_sdma_phase_quantum = 32;
152 char *amdgpu_disable_cu;
153 char *amdgpu_virtual_display;
156 * OverDrive(bit 14) disabled by default
157 * GFX DCS(bit 19) disabled by default
159 uint amdgpu_pp_feature_mask = 0xfff7bfff;
160 uint amdgpu_force_long_training;
161 int amdgpu_lbpw = -1;
162 int amdgpu_compute_multipipe = -1;
163 int amdgpu_gpu_recovery = -1; /* auto */
165 uint amdgpu_smu_memory_pool_size;
166 int amdgpu_smu_pptable_id = -1;
168 * FBC (bit 0) disabled by default
169 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
170 * - With this, for multiple monitors in sync(e.g. with the same model),
171 * mclk switching will be allowed. And the mclk will be not foced to the
172 * highest. That helps saving some idle power.
173 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
174 * PSR (bit 3) disabled by default
175 * EDP NO POWER SEQUENCING (bit 4) disabled by default
177 uint amdgpu_dc_feature_mask = 2;
178 uint amdgpu_dc_debug_mask;
179 uint amdgpu_dc_visual_confirm;
180 int amdgpu_async_gfx_ring = 1;
182 int amdgpu_discovery = -1;
185 int amdgpu_noretry = -1;
186 int amdgpu_force_asic_type = -1;
187 int amdgpu_tmz = -1; /* auto */
188 uint amdgpu_freesync_vid_mode;
189 int amdgpu_reset_method = -1; /* auto */
190 int amdgpu_num_kcq = -1;
191 int amdgpu_smartshift_bias;
192 int amdgpu_use_xgmi_p2p = 1;
193 int amdgpu_vcnfw_log;
194 int amdgpu_sg_display = -1; /* auto */
196 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
198 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
210 struct amdgpu_mgpu_info mgpu_info = {
211 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
212 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
213 mgpu_info.delayed_reset_work,
214 amdgpu_drv_delayed_reset_work_handler, 0),
216 int amdgpu_ras_enable = -1;
217 uint amdgpu_ras_mask = 0xffffffff;
218 int amdgpu_bad_page_threshold = -1;
219 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
220 .timeout_fatal_disable = false,
221 .period = 0x0, /* default to 0x0 (timeout disable) */
225 * DOC: vramlimit (int)
226 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
228 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
229 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
232 * DOC: vis_vramlimit (int)
233 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
235 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
236 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
239 * DOC: gartsize (uint)
240 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing.
241 * The default is -1 (The size depends on asic).
243 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
244 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
248 * Restrict the size of GTT domain (for userspace use) in MiB for testing.
249 * The default is -1 (Use 1/2 RAM, minimum value is 3GB).
251 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
252 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
255 * DOC: moverate (int)
256 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
258 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
259 module_param_named(moverate, amdgpu_moverate, int, 0600);
263 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
265 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
266 module_param_named(audio, amdgpu_audio, int, 0444);
269 * DOC: disp_priority (int)
270 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
272 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
273 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
277 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
279 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
280 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
283 * DOC: pcie_gen2 (int)
284 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
286 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
287 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
291 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
293 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
294 module_param_named(msi, amdgpu_msi, int, 0444);
297 * DOC: lockup_timeout (string)
298 * Set GPU scheduler timeout value in ms.
300 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
301 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
302 * to the default timeout.
304 * - With one value specified, the setting will apply to all non-compute jobs.
305 * - With multiple values specified, the first one will be for GFX.
306 * The second one is for Compute. The third and fourth ones are
307 * for SDMA and Video.
309 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
310 * jobs is 10000. The timeout for compute is 60000.
312 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
313 "for passthrough or sriov, 10000 for all jobs."
314 " 0: keep default value. negative: infinity timeout), "
315 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
316 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
317 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
321 * Override for dynamic power management setting
322 * (0 = disable, 1 = enable)
323 * The default is -1 (auto).
325 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
326 module_param_named(dpm, amdgpu_dpm, int, 0444);
329 * DOC: fw_load_type (int)
330 * Set different firmware loading type for debugging, if supported.
331 * Set to 0 to force direct loading if supported by the ASIC. Set
332 * to -1 to select the default loading mode for the ASIC, as defined
333 * by the driver. The default is -1 (auto).
335 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
336 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
340 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
342 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
343 module_param_named(aspm, amdgpu_aspm, int, 0444);
347 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
348 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
349 * Setting the value to 0 disables this functionality.
351 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
352 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
355 * DOC: ip_block_mask (uint)
356 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
357 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
358 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
359 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
361 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
362 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
366 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
367 * The default -1 (auto, enabled)
369 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
370 module_param_named(bapm, amdgpu_bapm, int, 0444);
373 * DOC: deep_color (int)
374 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
376 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
377 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
381 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
383 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
384 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
387 * DOC: vm_fragment_size (int)
388 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
390 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
391 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
394 * DOC: vm_block_size (int)
395 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
397 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
398 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
401 * DOC: vm_fault_stop (int)
402 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
404 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
405 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
408 * DOC: vm_debug (int)
409 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
411 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
412 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
415 * DOC: vm_update_mode (int)
416 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
417 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
419 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
420 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
423 * DOC: exp_hw_support (int)
424 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
426 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
427 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
431 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
433 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
434 module_param_named(dc, amdgpu_dc, int, 0444);
437 * DOC: sched_jobs (int)
438 * Override the max number of jobs supported in the sw queue. The default is 32.
440 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
441 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
444 * DOC: sched_hw_submission (int)
445 * Override the max number of HW submissions. The default is 2.
447 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
448 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
451 * DOC: ppfeaturemask (hexint)
452 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
453 * The default is the current set of stable power features.
455 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
456 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
459 * DOC: forcelongtraining (uint)
460 * Force long memory training in resume.
461 * The default is zero, indicates short training in resume.
463 MODULE_PARM_DESC(forcelongtraining, "force memory long training");
464 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
467 * DOC: pcie_gen_cap (uint)
468 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
469 * The default is 0 (automatic for each asic).
471 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
472 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
475 * DOC: pcie_lane_cap (uint)
476 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
477 * The default is 0 (automatic for each asic).
479 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
480 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
483 * DOC: cg_mask (ullong)
484 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
485 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
487 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
488 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
491 * DOC: pg_mask (uint)
492 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
493 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
495 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
496 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
499 * DOC: sdma_phase_quantum (uint)
500 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
502 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
503 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
506 * DOC: disable_cu (charp)
507 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
509 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
510 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
513 * DOC: virtual_display (charp)
514 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
515 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
516 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
517 * device at 26:00.0. The default is NULL.
519 MODULE_PARM_DESC(virtual_display,
520 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
521 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
525 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
527 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
528 module_param_named(lbpw, amdgpu_lbpw, int, 0444);
530 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
531 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
534 * DOC: gpu_recovery (int)
535 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
537 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
538 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
541 * DOC: emu_mode (int)
542 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
544 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
545 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
548 * DOC: ras_enable (int)
549 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
551 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
552 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
555 * DOC: ras_mask (uint)
556 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
557 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
559 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
560 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
563 * DOC: timeout_fatal_disable (bool)
564 * Disable Watchdog timeout fatal error event
566 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
567 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
570 * DOC: timeout_period (uint)
571 * Modify the watchdog timeout max_cycles as (1 << period)
573 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
574 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
577 * DOC: si_support (int)
578 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
579 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
580 * otherwise using amdgpu driver.
582 #ifdef CONFIG_DRM_AMDGPU_SI
584 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
585 int amdgpu_si_support = 0;
586 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
588 int amdgpu_si_support = 1;
589 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
592 module_param_named(si_support, amdgpu_si_support, int, 0444);
596 * DOC: cik_support (int)
597 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
598 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
599 * otherwise using amdgpu driver.
601 #ifdef CONFIG_DRM_AMDGPU_CIK
603 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
604 int amdgpu_cik_support = 0;
605 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
607 int amdgpu_cik_support = 1;
608 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
611 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
615 * DOC: smu_memory_pool_size (uint)
616 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
617 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
619 MODULE_PARM_DESC(smu_memory_pool_size,
620 "reserve gtt for smu debug usage, 0 = disable,"
621 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
622 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
625 * DOC: async_gfx_ring (int)
626 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
628 MODULE_PARM_DESC(async_gfx_ring,
629 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
630 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
634 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
636 MODULE_PARM_DESC(mcbp,
637 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
638 module_param_named(mcbp, amdgpu_mcbp, int, 0444);
641 * DOC: discovery (int)
642 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
643 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
645 MODULE_PARM_DESC(discovery,
646 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
647 module_param_named(discovery, amdgpu_discovery, int, 0444);
651 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
652 * (0 = disabled (default), 1 = enabled)
654 MODULE_PARM_DESC(mes,
655 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
656 module_param_named(mes, amdgpu_mes, int, 0444);
660 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
661 * (0 = disabled (default), 1 = enabled)
663 MODULE_PARM_DESC(mes_kiq,
664 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
665 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
669 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
670 * do not support per-process XNACK this also disables retry page faults.
671 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
673 MODULE_PARM_DESC(noretry,
674 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
675 module_param_named(noretry, amdgpu_noretry, int, 0644);
678 * DOC: force_asic_type (int)
679 * A non negative value used to specify the asic type for all supported GPUs.
681 MODULE_PARM_DESC(force_asic_type,
682 "A non negative value used to specify the asic type for all supported GPUs");
683 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
686 * DOC: use_xgmi_p2p (int)
687 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
689 MODULE_PARM_DESC(use_xgmi_p2p,
690 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
691 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
694 #ifdef CONFIG_HSA_AMD
696 * DOC: sched_policy (int)
697 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
698 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
699 * assigns queues to HQDs.
701 int sched_policy = KFD_SCHED_POLICY_HWS;
702 module_param(sched_policy, int, 0444);
703 MODULE_PARM_DESC(sched_policy,
704 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
707 * DOC: hws_max_conc_proc (int)
708 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
709 * number of VMIDs assigned to the HWS, which is also the default.
711 int hws_max_conc_proc = -1;
712 module_param(hws_max_conc_proc, int, 0444);
713 MODULE_PARM_DESC(hws_max_conc_proc,
714 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
717 * DOC: cwsr_enable (int)
718 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
719 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
723 module_param(cwsr_enable, int, 0444);
724 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
727 * DOC: max_num_of_queues_per_device (int)
728 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
731 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
732 module_param(max_num_of_queues_per_device, int, 0444);
733 MODULE_PARM_DESC(max_num_of_queues_per_device,
734 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
737 * DOC: send_sigterm (int)
738 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
739 * but just print errors on dmesg. Setting 1 enables sending sigterm.
742 module_param(send_sigterm, int, 0444);
743 MODULE_PARM_DESC(send_sigterm,
744 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
747 * DOC: debug_largebar (int)
748 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
749 * system. This limits the VRAM size reported to ROCm applications to the visible
750 * size, usually 256MB.
751 * Default value is 0, diabled.
754 module_param(debug_largebar, int, 0444);
755 MODULE_PARM_DESC(debug_largebar,
756 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
759 * DOC: ignore_crat (int)
760 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
761 * table to get information about AMD APUs. This option can serve as a workaround on
762 * systems with a broken CRAT table.
764 * Default is auto (according to asic type, iommu_v2, and crat table, to decide
768 module_param(ignore_crat, int, 0444);
769 MODULE_PARM_DESC(ignore_crat,
770 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
773 * DOC: halt_if_hws_hang (int)
774 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
775 * Setting 1 enables halt on hang.
777 int halt_if_hws_hang;
778 module_param(halt_if_hws_hang, int, 0644);
779 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
782 * DOC: hws_gws_support(bool)
783 * Assume that HWS supports GWS barriers regardless of what firmware version
784 * check says. Default value: false (rely on MEC2 firmware version check).
786 bool hws_gws_support;
787 module_param(hws_gws_support, bool, 0444);
788 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
791 * DOC: queue_preemption_timeout_ms (int)
792 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
794 int queue_preemption_timeout_ms = 9000;
795 module_param(queue_preemption_timeout_ms, int, 0644);
796 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
799 * DOC: debug_evictions(bool)
800 * Enable extra debug messages to help determine the cause of evictions
802 bool debug_evictions;
803 module_param(debug_evictions, bool, 0644);
804 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
807 * DOC: no_system_mem_limit(bool)
808 * Disable system memory limit, to support multiple process shared memory
810 bool no_system_mem_limit;
811 module_param(no_system_mem_limit, bool, 0644);
812 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
815 * DOC: no_queue_eviction_on_vm_fault (int)
816 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
818 int amdgpu_no_queue_eviction_on_vm_fault;
819 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
820 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
824 * DOC: pcie_p2p (bool)
825 * Enable PCIe P2P (requires large-BAR). Default value: true (on)
827 #ifdef CONFIG_HSA_AMD_P2P
828 bool pcie_p2p = true;
829 module_param(pcie_p2p, bool, 0444);
830 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
834 * DOC: dcfeaturemask (uint)
835 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
836 * The default is the current set of stable display features.
838 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
839 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
842 * DOC: dcdebugmask (uint)
843 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
845 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
846 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
848 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
849 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
852 * DOC: abmlevel (uint)
853 * Override the default ABM (Adaptive Backlight Management) level used for DC
854 * enabled hardware. Requires DMCU to be supported and loaded.
855 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
856 * default. Values 1-4 control the maximum allowable brightness reduction via
857 * the ABM algorithm, with 1 being the least reduction and 4 being the most
860 * Defaults to 0, or disabled. Userspace can still override this level later
863 uint amdgpu_dm_abm_level;
864 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
865 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
867 int amdgpu_backlight = -1;
868 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
869 module_param_named(backlight, amdgpu_backlight, bint, 0444);
873 * Trusted Memory Zone (TMZ) is a method to protect data being written
874 * to or read from memory.
876 * The default value: 0 (off). TODO: change to auto till it is completed.
878 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
879 module_param_named(tmz, amdgpu_tmz, int, 0444);
882 * DOC: freesync_video (uint)
883 * Enable the optimization to adjust front porch timing to achieve seamless
884 * mode change experience when setting a freesync supported mode for which full
885 * modeset is not needed.
887 * The Display Core will add a set of modes derived from the base FreeSync
888 * video mode into the corresponding connector's mode list based on commonly
889 * used refresh rates and VRR range of the connected display, when users enable
890 * this feature. From the userspace perspective, they can see a seamless mode
891 * change experience when the change between different refresh rates under the
892 * same resolution. Additionally, userspace applications such as Video playback
893 * can read this modeset list and change the refresh rate based on the video
894 * frame rate. Finally, the userspace can also derive an appropriate mode for a
895 * particular refresh rate based on the FreeSync Mode and add it to the
896 * connector's mode list.
898 * Note: This is an experimental feature.
900 * The default value: 0 (off).
904 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
905 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
908 * DOC: reset_method (int)
909 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
911 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
912 module_param_named(reset_method, amdgpu_reset_method, int, 0444);
915 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
916 * threshold value of faulty pages detected by RAS ECC, which may
917 * result in the GPU entering bad status when the number of total
918 * faulty pages by ECC exceeds the threshold value.
920 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)");
921 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
923 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
924 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
927 * DOC: vcnfw_log (int)
928 * Enable vcnfw log output for debugging, the default is disabled.
930 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
931 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
934 * DOC: sg_display (int)
935 * Disable S/G (scatter/gather) display (i.e., display from system memory).
936 * This option is only relevant on APUs. Set this option to 0 to disable
937 * S/G display if you experience flickering or other issues under memory
938 * pressure and report the issue.
940 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
941 module_param_named(sg_display, amdgpu_sg_display, int, 0444);
944 * DOC: smu_pptable_id (int)
945 * Used to override pptable id. id = 0 use VBIOS pptable.
946 * id > 0 use the soft pptable with specicfied id.
948 MODULE_PARM_DESC(smu_pptable_id,
949 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
950 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
952 /* These devices are not supported by amdgpu.
953 * They are supported by the mach64, r128, radeon drivers
955 static const u16 amdgpu_unsupported_pciidlist[] = {
1580 /* radeon secondary ids */
1663 static const struct pci_device_id pciidlist[] = {
1664 #ifdef CONFIG_DRM_AMDGPU_SI
1665 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1666 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1667 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1668 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1669 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1670 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1671 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1672 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1673 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1674 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1675 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1676 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1677 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1678 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1679 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1680 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1681 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1682 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1683 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1684 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1685 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1686 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1687 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1688 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1689 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1690 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1691 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1692 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1693 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1694 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1695 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1696 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1697 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1698 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1699 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1700 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1701 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1702 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1703 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1704 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1705 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1706 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1707 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1708 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1709 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1710 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1711 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1712 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1713 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1714 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1715 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1716 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1717 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1718 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1719 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1720 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1721 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1722 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1723 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1724 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1725 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1726 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1727 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1728 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1729 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1730 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1731 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1732 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1733 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1734 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1735 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1736 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1738 #ifdef CONFIG_DRM_AMDGPU_CIK
1740 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1741 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1742 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1743 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1744 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1745 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1746 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1747 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1748 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1749 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1750 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1751 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1752 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1753 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1754 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1755 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1756 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1757 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1758 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1759 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1760 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1761 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1763 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1764 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1765 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1766 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1767 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1768 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1769 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1770 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1771 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1772 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1773 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1775 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1776 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1777 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1778 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1779 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1780 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1781 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1782 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1783 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1784 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1785 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1786 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1788 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1789 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1790 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1791 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1792 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1793 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1794 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1795 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1796 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1797 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1798 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1799 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1800 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1801 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1802 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1803 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1805 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1806 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1807 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1808 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1809 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1810 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1811 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1812 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1813 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1814 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1815 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1816 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1817 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1818 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1819 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1820 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1823 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1824 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1825 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1826 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1827 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1829 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1830 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1831 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1832 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1833 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1834 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1835 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1836 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1837 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1839 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1840 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1842 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1843 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1844 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1845 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1846 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1848 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1850 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1851 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1852 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1853 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1854 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1855 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1856 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1857 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1858 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1860 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1861 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1862 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1863 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1864 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1865 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1866 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1867 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1868 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1869 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1870 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1871 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1872 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1874 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1875 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1876 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1877 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1878 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1879 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1880 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1881 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1883 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1884 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1885 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1887 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1888 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1889 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1890 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1891 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1892 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1893 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1894 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1895 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1896 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1897 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1898 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1899 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1900 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1901 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1903 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1904 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1905 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1906 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1907 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1909 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1910 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1911 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1912 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1913 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1914 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1915 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1917 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1918 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1920 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1921 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1922 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1923 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1925 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1926 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1927 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1928 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1929 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1930 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1931 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1932 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1934 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1935 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1936 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1937 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1940 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1941 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1942 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1943 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1946 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1947 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1949 /* Sienna_Cichlid */
1950 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1951 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1952 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1953 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1954 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1955 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1956 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1957 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1958 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1959 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1960 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1961 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1962 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1965 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1966 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1969 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1970 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1971 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1972 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1973 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1974 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1975 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1976 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1977 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1979 /* DIMGREY_CAVEFISH */
1980 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1981 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1982 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1983 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1984 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1985 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1986 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1987 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1988 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1989 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1990 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1991 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1994 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1995 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1996 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1997 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1999 /* CYAN_SKILLFISH */
2000 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2001 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
2004 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2005 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2006 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2007 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2008 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2009 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2011 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2012 .class = PCI_CLASS_DISPLAY_VGA << 8,
2013 .class_mask = 0xffffff,
2014 .driver_data = CHIP_IP_DISCOVERY },
2016 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2017 .class = PCI_CLASS_DISPLAY_OTHER << 8,
2018 .class_mask = 0xffffff,
2019 .driver_data = CHIP_IP_DISCOVERY },
2024 MODULE_DEVICE_TABLE(pci, pciidlist);
2026 static const struct drm_driver amdgpu_kms_driver;
2028 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
2030 struct pci_dev *p = NULL;
2038 for (i = 1; i < 4; i++) {
2039 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2040 adev->pdev->bus->number, i);
2042 pm_runtime_get_sync(&p->dev);
2043 pm_runtime_mark_last_busy(&p->dev);
2044 pm_runtime_put_autosuspend(&p->dev);
2050 static int amdgpu_pci_probe(struct pci_dev *pdev,
2051 const struct pci_device_id *ent)
2053 struct drm_device *ddev;
2054 struct amdgpu_device *adev;
2055 unsigned long flags = ent->driver_data;
2056 int ret, retry = 0, i;
2057 bool supports_atomic = false;
2059 /* skip devices which are owned by radeon */
2060 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2061 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2065 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2068 if (amdgpu_virtual_display ||
2069 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2070 supports_atomic = true;
2072 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
2073 DRM_INFO("This hardware requires experimental hardware support.\n"
2074 "See modparam exp_hw_support\n");
2077 /* differentiate between P10 and P11 asics with the same DID */
2078 if (pdev->device == 0x67FF &&
2079 (pdev->revision == 0xE3 ||
2080 pdev->revision == 0xE7 ||
2081 pdev->revision == 0xF3 ||
2082 pdev->revision == 0xF7)) {
2083 flags &= ~AMD_ASIC_MASK;
2084 flags |= CHIP_POLARIS10;
2087 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2088 * however, SME requires an indirect IOMMU mapping because the encryption
2089 * bit is beyond the DMA mask of the chip.
2091 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2092 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
2093 dev_info(&pdev->dev,
2094 "SME is not compatible with RAVEN\n");
2098 #ifdef CONFIG_DRM_AMDGPU_SI
2099 if (!amdgpu_si_support) {
2100 switch (flags & AMD_ASIC_MASK) {
2106 dev_info(&pdev->dev,
2107 "SI support provided by radeon.\n");
2108 dev_info(&pdev->dev,
2109 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2115 #ifdef CONFIG_DRM_AMDGPU_CIK
2116 if (!amdgpu_cik_support) {
2117 switch (flags & AMD_ASIC_MASK) {
2123 dev_info(&pdev->dev,
2124 "CIK support provided by radeon.\n");
2125 dev_info(&pdev->dev,
2126 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2133 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
2135 return PTR_ERR(adev);
2137 adev->dev = &pdev->dev;
2139 ddev = adev_to_drm(adev);
2141 if (!supports_atomic)
2142 ddev->driver_features &= ~DRIVER_ATOMIC;
2144 ret = pci_enable_device(pdev);
2148 pci_set_drvdata(pdev, ddev);
2150 ret = amdgpu_driver_load_kms(adev, flags);
2155 ret = drm_dev_register(ddev, flags);
2156 if (ret == -EAGAIN && ++retry <= 3) {
2157 DRM_INFO("retry init %d\n", retry);
2158 /* Don't request EX mode too frequently which is attacking */
2166 * 1. don't init fbdev on hw without DCE
2167 * 2. don't init fbdev if there are no connectors
2169 if (adev->mode_info.mode_config_initialized &&
2170 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2171 /* select 8 bpp console on low vram cards */
2172 if (adev->gmc.real_vram_size <= (32*1024*1024))
2173 drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2175 drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2178 ret = amdgpu_debugfs_init(adev);
2180 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2182 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2183 /* only need to skip on ATPX */
2184 if (amdgpu_device_supports_px(ddev))
2185 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2186 /* we want direct complete for BOCO */
2187 if (amdgpu_device_supports_boco(ddev))
2188 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2189 DPM_FLAG_SMART_SUSPEND |
2190 DPM_FLAG_MAY_SKIP_RESUME);
2191 pm_runtime_use_autosuspend(ddev->dev);
2192 pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2194 pm_runtime_allow(ddev->dev);
2196 pm_runtime_mark_last_busy(ddev->dev);
2197 pm_runtime_put_autosuspend(ddev->dev);
2200 * For runpm implemented via BACO, PMFW will handle the
2201 * timing for BACO in and out:
2202 * - put ASIC into BACO state only when both video and
2203 * audio functions are in D3 state.
2204 * - pull ASIC out of BACO state when either video or
2205 * audio function is in D0 state.
2206 * Also, at startup, PMFW assumes both functions are in
2209 * So if snd driver was loaded prior to amdgpu driver
2210 * and audio function was put into D3 state, there will
2211 * be no PMFW-aware D-state transition(D0->D3) on runpm
2212 * suspend. Thus the BACO will be not correctly kicked in.
2214 * Via amdgpu_get_secondary_funcs(), the audio dev is put
2215 * into D0 state. Then there will be a PMFW-aware D-state
2216 * transition(D0->D3) on runpm suspend.
2218 if (amdgpu_device_supports_baco(ddev) &&
2219 !(adev->flags & AMD_IS_APU) &&
2220 (adev->asic_type >= CHIP_NAVI10))
2221 amdgpu_get_secondary_funcs(adev);
2227 pci_disable_device(pdev);
2232 amdgpu_pci_remove(struct pci_dev *pdev)
2234 struct drm_device *dev = pci_get_drvdata(pdev);
2235 struct amdgpu_device *adev = drm_to_adev(dev);
2237 drm_dev_unplug(dev);
2239 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
2240 pm_runtime_get_sync(dev->dev);
2241 pm_runtime_forbid(dev->dev);
2244 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&
2245 !amdgpu_sriov_vf(adev)) {
2246 bool need_to_reset_gpu = false;
2248 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2249 struct amdgpu_hive_info *hive;
2251 hive = amdgpu_get_xgmi_hive(adev);
2252 if (hive->device_remove_count == 0)
2253 need_to_reset_gpu = true;
2254 hive->device_remove_count++;
2255 amdgpu_put_xgmi_hive(hive);
2257 need_to_reset_gpu = true;
2260 /* Workaround for ASICs need to reset SMU.
2261 * Called only when the first device is removed.
2263 if (need_to_reset_gpu) {
2264 struct amdgpu_reset_context reset_context;
2266 adev->shutdown = true;
2267 memset(&reset_context, 0, sizeof(reset_context));
2268 reset_context.method = AMD_RESET_METHOD_NONE;
2269 reset_context.reset_req_dev = adev;
2270 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2271 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags);
2272 amdgpu_device_gpu_recover(adev, NULL, &reset_context);
2276 amdgpu_driver_unload_kms(dev);
2279 * Flush any in flight DMA operations from device.
2280 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2281 * StatusTransactions Pending bit.
2283 pci_disable_device(pdev);
2284 pci_wait_for_pending_transaction(pdev);
2288 amdgpu_pci_shutdown(struct pci_dev *pdev)
2290 struct drm_device *dev = pci_get_drvdata(pdev);
2291 struct amdgpu_device *adev = drm_to_adev(dev);
2293 if (amdgpu_ras_intr_triggered())
2296 /* if we are running in a VM, make sure the device
2297 * torn down properly on reboot/shutdown.
2298 * unfortunately we can't detect certain
2299 * hypervisors so just do this all the time.
2301 if (!amdgpu_passthrough(adev))
2302 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2303 amdgpu_device_ip_suspend(adev);
2304 adev->mp1_state = PP_MP1_STATE_NONE;
2308 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2310 * @work: work_struct.
2312 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2314 struct list_head device_list;
2315 struct amdgpu_device *adev;
2317 struct amdgpu_reset_context reset_context;
2319 memset(&reset_context, 0, sizeof(reset_context));
2321 mutex_lock(&mgpu_info.mutex);
2322 if (mgpu_info.pending_reset == true) {
2323 mutex_unlock(&mgpu_info.mutex);
2326 mgpu_info.pending_reset = true;
2327 mutex_unlock(&mgpu_info.mutex);
2329 /* Use a common context, just need to make sure full reset is done */
2330 reset_context.method = AMD_RESET_METHOD_NONE;
2331 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2333 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2334 adev = mgpu_info.gpu_ins[i].adev;
2335 reset_context.reset_req_dev = adev;
2336 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
2338 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2339 r, adev_to_drm(adev)->unique);
2341 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2344 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2345 adev = mgpu_info.gpu_ins[i].adev;
2346 flush_work(&adev->xgmi_reset_work);
2347 adev->gmc.xgmi.pending_reset = false;
2350 /* reset function will rebuild the xgmi hive info , clear it now */
2351 for (i = 0; i < mgpu_info.num_dgpu; i++)
2352 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2354 INIT_LIST_HEAD(&device_list);
2356 for (i = 0; i < mgpu_info.num_dgpu; i++)
2357 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2359 /* unregister the GPU first, reset function will add them back */
2360 list_for_each_entry(adev, &device_list, reset_list)
2361 amdgpu_unregister_gpu_instance(adev);
2363 /* Use a common context, just need to make sure full reset is done */
2364 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2365 r = amdgpu_do_asic_reset(&device_list, &reset_context);
2368 DRM_ERROR("reinit gpus failure");
2371 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2372 adev = mgpu_info.gpu_ins[i].adev;
2373 if (!adev->kfd.init_complete)
2374 amdgpu_amdkfd_device_init(adev);
2375 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2380 static int amdgpu_pmops_prepare(struct device *dev)
2382 struct drm_device *drm_dev = dev_get_drvdata(dev);
2383 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2385 /* Return a positive number here so
2386 * DPM_FLAG_SMART_SUSPEND works properly
2388 if (amdgpu_device_supports_boco(drm_dev))
2389 return pm_runtime_suspended(dev);
2391 /* if we will not support s3 or s2i for the device
2394 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2395 !amdgpu_acpi_is_s3_active(adev))
2401 static void amdgpu_pmops_complete(struct device *dev)
2406 static int amdgpu_pmops_suspend(struct device *dev)
2408 struct drm_device *drm_dev = dev_get_drvdata(dev);
2409 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2411 if (amdgpu_acpi_is_s0ix_active(adev))
2412 adev->in_s0ix = true;
2413 else if (amdgpu_acpi_is_s3_active(adev))
2415 if (!adev->in_s0ix && !adev->in_s3)
2417 return amdgpu_device_suspend(drm_dev, true);
2420 static int amdgpu_pmops_suspend_noirq(struct device *dev)
2422 struct drm_device *drm_dev = dev_get_drvdata(dev);
2423 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2425 if (amdgpu_acpi_should_gpu_reset(adev))
2426 return amdgpu_asic_reset(adev);
2431 static int amdgpu_pmops_resume(struct device *dev)
2433 struct drm_device *drm_dev = dev_get_drvdata(dev);
2434 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2437 if (!adev->in_s0ix && !adev->in_s3)
2440 /* Avoids registers access if device is physically gone */
2441 if (!pci_device_is_present(adev->pdev))
2442 adev->no_hw_access = true;
2444 r = amdgpu_device_resume(drm_dev, true);
2445 if (amdgpu_acpi_is_s0ix_active(adev))
2446 adev->in_s0ix = false;
2448 adev->in_s3 = false;
2452 static int amdgpu_pmops_freeze(struct device *dev)
2454 struct drm_device *drm_dev = dev_get_drvdata(dev);
2455 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2459 r = amdgpu_device_suspend(drm_dev, true);
2460 adev->in_s4 = false;
2464 if (amdgpu_acpi_should_gpu_reset(adev))
2465 return amdgpu_asic_reset(adev);
2469 static int amdgpu_pmops_thaw(struct device *dev)
2471 struct drm_device *drm_dev = dev_get_drvdata(dev);
2473 return amdgpu_device_resume(drm_dev, true);
2476 static int amdgpu_pmops_poweroff(struct device *dev)
2478 struct drm_device *drm_dev = dev_get_drvdata(dev);
2480 return amdgpu_device_suspend(drm_dev, true);
2483 static int amdgpu_pmops_restore(struct device *dev)
2485 struct drm_device *drm_dev = dev_get_drvdata(dev);
2487 return amdgpu_device_resume(drm_dev, true);
2490 static int amdgpu_runtime_idle_check_display(struct device *dev)
2492 struct pci_dev *pdev = to_pci_dev(dev);
2493 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2494 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2496 if (adev->mode_info.num_crtc) {
2497 struct drm_connector *list_connector;
2498 struct drm_connector_list_iter iter;
2501 /* XXX: Return busy if any displays are connected to avoid
2502 * possible display wakeups after runtime resume due to
2503 * hotplug events in case any displays were connected while
2504 * the GPU was in suspend. Remove this once that is fixed.
2506 mutex_lock(&drm_dev->mode_config.mutex);
2507 drm_connector_list_iter_begin(drm_dev, &iter);
2508 drm_for_each_connector_iter(list_connector, &iter) {
2509 if (list_connector->status == connector_status_connected) {
2514 drm_connector_list_iter_end(&iter);
2515 mutex_unlock(&drm_dev->mode_config.mutex);
2520 if (adev->dc_enabled) {
2521 struct drm_crtc *crtc;
2523 drm_for_each_crtc(crtc, drm_dev) {
2524 drm_modeset_lock(&crtc->mutex, NULL);
2525 if (crtc->state->active)
2527 drm_modeset_unlock(&crtc->mutex);
2532 mutex_lock(&drm_dev->mode_config.mutex);
2533 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2535 drm_connector_list_iter_begin(drm_dev, &iter);
2536 drm_for_each_connector_iter(list_connector, &iter) {
2537 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2543 drm_connector_list_iter_end(&iter);
2545 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2546 mutex_unlock(&drm_dev->mode_config.mutex);
2555 static int amdgpu_pmops_runtime_suspend(struct device *dev)
2557 struct pci_dev *pdev = to_pci_dev(dev);
2558 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2559 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2562 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2563 pm_runtime_forbid(dev);
2567 ret = amdgpu_runtime_idle_check_display(dev);
2571 /* wait for all rings to drain before suspending */
2572 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2573 struct amdgpu_ring *ring = adev->rings[i];
2574 if (ring && ring->sched.ready) {
2575 ret = amdgpu_fence_wait_empty(ring);
2581 adev->in_runpm = true;
2582 if (amdgpu_device_supports_px(drm_dev))
2583 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2586 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2587 * proper cleanups and put itself into a state ready for PNP. That
2588 * can address some random resuming failure observed on BOCO capable
2590 * TODO: this may be also needed for PX capable platform.
2592 if (amdgpu_device_supports_boco(drm_dev))
2593 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2595 ret = amdgpu_device_suspend(drm_dev, false);
2597 adev->in_runpm = false;
2598 if (amdgpu_device_supports_boco(drm_dev))
2599 adev->mp1_state = PP_MP1_STATE_NONE;
2603 if (amdgpu_device_supports_boco(drm_dev))
2604 adev->mp1_state = PP_MP1_STATE_NONE;
2606 if (amdgpu_device_supports_px(drm_dev)) {
2607 /* Only need to handle PCI state in the driver for ATPX
2608 * PCI core handles it for _PR3.
2610 amdgpu_device_cache_pci_state(pdev);
2611 pci_disable_device(pdev);
2612 pci_ignore_hotplug(pdev);
2613 pci_set_power_state(pdev, PCI_D3cold);
2614 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
2615 } else if (amdgpu_device_supports_boco(drm_dev)) {
2617 } else if (amdgpu_device_supports_baco(drm_dev)) {
2618 amdgpu_device_baco_enter(drm_dev);
2621 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");
2626 static int amdgpu_pmops_runtime_resume(struct device *dev)
2628 struct pci_dev *pdev = to_pci_dev(dev);
2629 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2630 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2633 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
2636 /* Avoids registers access if device is physically gone */
2637 if (!pci_device_is_present(adev->pdev))
2638 adev->no_hw_access = true;
2640 if (amdgpu_device_supports_px(drm_dev)) {
2641 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2643 /* Only need to handle PCI state in the driver for ATPX
2644 * PCI core handles it for _PR3.
2646 pci_set_power_state(pdev, PCI_D0);
2647 amdgpu_device_load_pci_state(pdev);
2648 ret = pci_enable_device(pdev);
2651 pci_set_master(pdev);
2652 } else if (amdgpu_device_supports_boco(drm_dev)) {
2653 /* Only need to handle PCI state in the driver for ATPX
2654 * PCI core handles it for _PR3.
2656 pci_set_master(pdev);
2657 } else if (amdgpu_device_supports_baco(drm_dev)) {
2658 amdgpu_device_baco_exit(drm_dev);
2660 ret = amdgpu_device_resume(drm_dev, false);
2662 if (amdgpu_device_supports_px(drm_dev))
2663 pci_disable_device(pdev);
2667 if (amdgpu_device_supports_px(drm_dev))
2668 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
2669 adev->in_runpm = false;
2673 static int amdgpu_pmops_runtime_idle(struct device *dev)
2675 struct drm_device *drm_dev = dev_get_drvdata(dev);
2676 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2677 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2680 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
2681 pm_runtime_forbid(dev);
2685 ret = amdgpu_runtime_idle_check_display(dev);
2687 pm_runtime_mark_last_busy(dev);
2688 pm_runtime_autosuspend(dev);
2692 long amdgpu_drm_ioctl(struct file *filp,
2693 unsigned int cmd, unsigned long arg)
2695 struct drm_file *file_priv = filp->private_data;
2696 struct drm_device *dev;
2698 dev = file_priv->minor->dev;
2699 ret = pm_runtime_get_sync(dev->dev);
2703 ret = drm_ioctl(filp, cmd, arg);
2705 pm_runtime_mark_last_busy(dev->dev);
2707 pm_runtime_put_autosuspend(dev->dev);
2711 static const struct dev_pm_ops amdgpu_pm_ops = {
2712 .prepare = amdgpu_pmops_prepare,
2713 .complete = amdgpu_pmops_complete,
2714 .suspend = amdgpu_pmops_suspend,
2715 .suspend_noirq = amdgpu_pmops_suspend_noirq,
2716 .resume = amdgpu_pmops_resume,
2717 .freeze = amdgpu_pmops_freeze,
2718 .thaw = amdgpu_pmops_thaw,
2719 .poweroff = amdgpu_pmops_poweroff,
2720 .restore = amdgpu_pmops_restore,
2721 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2722 .runtime_resume = amdgpu_pmops_runtime_resume,
2723 .runtime_idle = amdgpu_pmops_runtime_idle,
2726 static int amdgpu_flush(struct file *f, fl_owner_t id)
2728 struct drm_file *file_priv = f->private_data;
2729 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
2730 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
2732 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2733 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
2735 return timeout >= 0 ? 0 : timeout;
2738 static const struct file_operations amdgpu_driver_kms_fops = {
2739 .owner = THIS_MODULE,
2741 .flush = amdgpu_flush,
2742 .release = drm_release,
2743 .unlocked_ioctl = amdgpu_drm_ioctl,
2744 .mmap = drm_gem_mmap,
2747 #ifdef CONFIG_COMPAT
2748 .compat_ioctl = amdgpu_kms_compat_ioctl,
2750 #ifdef CONFIG_PROC_FS
2751 .show_fdinfo = amdgpu_show_fdinfo
2755 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2757 struct drm_file *file;
2762 if (filp->f_op != &amdgpu_driver_kms_fops) {
2766 file = filp->private_data;
2767 *fpriv = file->driver_priv;
2771 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2772 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2773 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2774 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2775 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2776 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2777 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2779 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2780 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2781 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2782 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2783 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2784 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2785 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2786 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2787 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2788 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2791 static const struct drm_driver amdgpu_kms_driver = {
2795 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2796 DRIVER_SYNCOBJ_TIMELINE,
2797 .open = amdgpu_driver_open_kms,
2798 .postclose = amdgpu_driver_postclose_kms,
2799 .lastclose = amdgpu_driver_lastclose_kms,
2800 .ioctls = amdgpu_ioctls_kms,
2801 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2802 .dumb_create = amdgpu_mode_dumb_create,
2803 .dumb_map_offset = amdgpu_mode_dumb_mmap,
2804 .fops = &amdgpu_driver_kms_fops,
2805 .release = &amdgpu_driver_release_kms,
2807 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2808 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2809 .gem_prime_import = amdgpu_gem_prime_import,
2810 .gem_prime_mmap = drm_gem_prime_mmap,
2812 .name = DRIVER_NAME,
2813 .desc = DRIVER_DESC,
2814 .date = DRIVER_DATE,
2815 .major = KMS_DRIVER_MAJOR,
2816 .minor = KMS_DRIVER_MINOR,
2817 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2820 static struct pci_error_handlers amdgpu_pci_err_handler = {
2821 .error_detected = amdgpu_pci_error_detected,
2822 .mmio_enabled = amdgpu_pci_mmio_enabled,
2823 .slot_reset = amdgpu_pci_slot_reset,
2824 .resume = amdgpu_pci_resume,
2827 extern const struct attribute_group amdgpu_vram_mgr_attr_group;
2828 extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
2829 extern const struct attribute_group amdgpu_vbios_version_attr_group;
2831 static const struct attribute_group *amdgpu_sysfs_groups[] = {
2832 &amdgpu_vram_mgr_attr_group,
2833 &amdgpu_gtt_mgr_attr_group,
2834 &amdgpu_vbios_version_attr_group,
2839 static struct pci_driver amdgpu_kms_pci_driver = {
2840 .name = DRIVER_NAME,
2841 .id_table = pciidlist,
2842 .probe = amdgpu_pci_probe,
2843 .remove = amdgpu_pci_remove,
2844 .shutdown = amdgpu_pci_shutdown,
2845 .driver.pm = &amdgpu_pm_ops,
2846 .err_handler = &amdgpu_pci_err_handler,
2847 .dev_groups = amdgpu_sysfs_groups,
2850 static int __init amdgpu_init(void)
2854 if (drm_firmware_drivers_only())
2857 r = amdgpu_sync_init();
2861 r = amdgpu_fence_slab_init();
2865 DRM_INFO("amdgpu kernel modesetting enabled.\n");
2866 amdgpu_register_atpx_handler();
2867 amdgpu_acpi_detect();
2869 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2870 amdgpu_amdkfd_init();
2872 /* let modprobe override vga console setting */
2873 return pci_register_driver(&amdgpu_kms_pci_driver);
2882 static void __exit amdgpu_exit(void)
2884 amdgpu_amdkfd_fini();
2885 pci_unregister_driver(&amdgpu_kms_pci_driver);
2886 amdgpu_unregister_atpx_handler();
2888 amdgpu_fence_slab_fini();
2889 mmu_notifier_synchronize();
2892 module_init(amdgpu_init);
2893 module_exit(amdgpu_exit);
2895 MODULE_AUTHOR(DRIVER_AUTHOR);
2896 MODULE_DESCRIPTION(DRIVER_DESC);
2897 MODULE_LICENSE("GPL and additional rights");
projects / platform / kernel / linux-starfive.git / blob