1 // SPDX-License-Identifier: MIT
3 * Copyright 2022 Advanced Micro Devices, Inc.
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28 * amdgpu_mm_rdoorbell - read a doorbell dword
30 * @adev: amdgpu_device pointer
31 * @index: doorbell index
33 * Returns the value in the doorbell aperture at the
34 * requested doorbell index (CIK).
36 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
38 if (amdgpu_device_skip_hw_access(adev))
41 if (index < adev->doorbell.num_kernel_doorbells)
42 return readl(adev->doorbell.cpu_addr + index);
44 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
49 * amdgpu_mm_wdoorbell - write a doorbell dword
51 * @adev: amdgpu_device pointer
52 * @index: doorbell index
55 * Writes @v to the doorbell aperture at the
56 * requested doorbell index (CIK).
58 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
60 if (amdgpu_device_skip_hw_access(adev))
63 if (index < adev->doorbell.num_kernel_doorbells)
64 writel(v, adev->doorbell.cpu_addr + index);
66 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
70 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
72 * @adev: amdgpu_device pointer
73 * @index: doorbell index
75 * Returns the value in the doorbell aperture at the
76 * requested doorbell index (VEGA10+).
78 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
80 if (amdgpu_device_skip_hw_access(adev))
83 if (index < adev->doorbell.num_kernel_doorbells)
84 return atomic64_read((atomic64_t *)(adev->doorbell.cpu_addr + index));
86 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
91 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
93 * @adev: amdgpu_device pointer
94 * @index: doorbell index
97 * Writes @v to the doorbell aperture at the
98 * requested doorbell index (VEGA10+).
100 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
102 if (amdgpu_device_skip_hw_access(adev))
105 if (index < adev->doorbell.num_kernel_doorbells)
106 atomic64_set((atomic64_t *)(adev->doorbell.cpu_addr + index), v);
108 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
112 * amdgpu_doorbell_index_on_bar - Find doorbell's absolute offset in BAR
114 * @adev: amdgpu_device pointer
115 * @db_bo: doorbell object's bo
116 * @db_index: doorbell relative index in this doorbell object
118 * returns doorbell's absolute index in BAR
120 uint32_t amdgpu_doorbell_index_on_bar(struct amdgpu_device *adev,
121 struct amdgpu_bo *db_bo,
122 uint32_t doorbell_index)
126 db_bo_offset = amdgpu_bo_gpu_offset_no_check(db_bo);
128 /* doorbell index is 32 bit but doorbell's size is 64-bit, so *2 */
129 return db_bo_offset / sizeof(u32) + doorbell_index * 2;
133 * amdgpu_doorbell_create_kernel_doorbells - Create kernel doorbells for graphics
135 * @adev: amdgpu_device pointer
137 * Creates doorbells for graphics driver usages.
138 * returns 0 on success, error otherwise.
140 int amdgpu_doorbell_create_kernel_doorbells(struct amdgpu_device *adev)
145 /* Reserve first num_kernel_doorbells (page-aligned) for kernel ops */
146 size = ALIGN(adev->doorbell.num_kernel_doorbells * sizeof(u32), PAGE_SIZE);
148 /* Allocate an extra page for MES kernel usages (ring test) */
149 adev->mes.db_start_dw_offset = size / sizeof(u32);
152 r = amdgpu_bo_create_kernel(adev,
155 AMDGPU_GEM_DOMAIN_DOORBELL,
156 &adev->doorbell.kernel_doorbells,
158 (void **)&adev->doorbell.cpu_addr);
160 DRM_ERROR("Failed to allocate kernel doorbells, err=%d\n", r);
164 adev->doorbell.num_kernel_doorbells = size / sizeof(u32);
169 * GPU doorbell aperture helpers function.
172 * amdgpu_doorbell_init - Init doorbell driver information.
174 * @adev: amdgpu_device pointer
176 * Init doorbell driver information (CIK)
177 * Returns 0 on success, error on failure.
179 int amdgpu_doorbell_init(struct amdgpu_device *adev)
182 /* No doorbell on SI hardware generation */
183 if (adev->asic_type < CHIP_BONAIRE) {
184 adev->doorbell.base = 0;
185 adev->doorbell.size = 0;
186 adev->doorbell.num_kernel_doorbells = 0;
190 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
193 amdgpu_asic_init_doorbell_index(adev);
195 /* doorbell bar mapping */
196 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
197 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
199 adev->doorbell.num_kernel_doorbells =
200 min_t(u32, adev->doorbell.size / sizeof(u32),
201 adev->doorbell_index.max_assignment + 1);
202 if (adev->doorbell.num_kernel_doorbells == 0)
206 * For Vega, reserve and map two pages on doorbell BAR since SDMA
207 * paging queue doorbell use the second page. The
208 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
209 * doorbells are in the first page. So with paging queue enabled,
210 * the max num_kernel_doorbells should + 1 page (0x400 in dword)
212 if (adev->asic_type >= CHIP_VEGA10)
213 adev->doorbell.num_kernel_doorbells += 0x400;
219 * amdgpu_doorbell_fini - Tear down doorbell driver information.
221 * @adev: amdgpu_device pointer
223 * Tear down doorbell driver information (CIK)
225 void amdgpu_doorbell_fini(struct amdgpu_device *adev)
227 amdgpu_bo_free_kernel(&adev->doorbell.kernel_doorbells,
229 (void **)&adev->doorbell.cpu_addr);