2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * based on nouveau_prime.c
24 * Authors: Alex Deucher
28 * DOC: PRIME Buffer Sharing
30 * The following callback implementations are used for :ref:`sharing GEM buffer
31 * objects between different devices via PRIME <prime_buffer_sharing>`.
35 #include "amdgpu_display.h"
36 #include "amdgpu_gem.h"
37 #include "amdgpu_dma_buf.h"
38 #include "amdgpu_xgmi.h"
39 #include <drm/amdgpu_drm.h>
40 #include <linux/dma-buf.h>
41 #include <linux/dma-fence-array.h>
42 #include <linux/pci-p2pdma.h>
43 #include <linux/pm_runtime.h>
46 * amdgpu_gem_prime_mmap - &drm_driver.gem_prime_mmap implementation
48 * @vma: Virtual memory area
50 * Sets up a userspace mapping of the BO's memory in the given
51 * virtual memory area.
54 * 0 on success or a negative error code on failure.
56 int amdgpu_gem_prime_mmap(struct drm_gem_object *obj,
57 struct vm_area_struct *vma)
59 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
60 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
61 unsigned asize = amdgpu_bo_size(bo);
70 /* Check for valid size. */
71 if (asize < vma->vm_end - vma->vm_start)
74 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
75 (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
78 vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT;
80 /* prime mmap does not need to check access, so allow here */
81 ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data);
85 ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev);
86 drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data);
92 __dma_resv_make_exclusive(struct dma_resv *obj)
94 struct dma_fence **fences;
98 if (!dma_resv_get_list(obj)) /* no shared fences to convert */
101 r = dma_resv_get_fences_rcu(obj, NULL, &count, &fences);
106 /* Now that was unexpected. */
107 } else if (count == 1) {
108 dma_resv_add_excl_fence(obj, fences[0]);
109 dma_fence_put(fences[0]);
112 struct dma_fence_array *array;
114 array = dma_fence_array_create(count, fences,
115 dma_fence_context_alloc(1), 0,
120 dma_resv_add_excl_fence(obj, &array->base);
121 dma_fence_put(&array->base);
128 dma_fence_put(fences[count]);
134 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
136 * @dmabuf: DMA-buf where we attach to
137 * @attach: attachment to add
139 * Add the attachment as user to the exported DMA-buf.
141 static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
142 struct dma_buf_attachment *attach)
144 struct drm_gem_object *obj = dmabuf->priv;
145 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
146 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
149 if (pci_p2pdma_distance_many(adev->pdev, &attach->dev, 1, true) < 0)
150 attach->peer2peer = false;
152 if (attach->dev->driver == adev->dev->driver)
155 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
159 r = amdgpu_bo_reserve(bo, false);
160 if (unlikely(r != 0))
164 * We only create shared fences for internal use, but importers
165 * of the dmabuf rely on exclusive fences for implicitly
166 * tracking write hazards. As any of the current fences may
167 * correspond to a write, we need to convert all existing
168 * fences on the reservation object into a single exclusive
171 r = __dma_resv_make_exclusive(bo->tbo.base.resv);
175 bo->prime_shared_count++;
176 amdgpu_bo_unreserve(bo);
180 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
185 * amdgpu_dma_buf_detach - &dma_buf_ops.detach implementation
187 * @dmabuf: DMA-buf where we remove the attachment from
188 * @attach: the attachment to remove
190 * Called when an attachment is removed from the DMA-buf.
192 static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,
193 struct dma_buf_attachment *attach)
195 struct drm_gem_object *obj = dmabuf->priv;
196 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
197 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
199 if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count)
200 bo->prime_shared_count--;
202 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
203 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
207 * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation
209 * @attach: attachment to pin down
211 * Pin the BO which is backing the DMA-buf so that it can't move any more.
213 static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
215 struct drm_gem_object *obj = attach->dmabuf->priv;
216 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
218 /* pin buffer into GTT */
219 return amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
223 * amdgpu_dma_buf_unpin - &dma_buf_ops.unpin implementation
225 * @attach: attachment to unpin
227 * Unpin a previously pinned BO to make it movable again.
229 static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach)
231 struct drm_gem_object *obj = attach->dmabuf->priv;
232 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
238 * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation
239 * @attach: DMA-buf attachment
240 * @dir: DMA direction
242 * Makes sure that the shared DMA buffer can be accessed by the target device.
243 * For now, simply pins it to the GTT domain, where it should be accessible by
247 * sg_table filled with the DMA addresses to use or ERR_PRT with negative error
250 static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
251 enum dma_data_direction dir)
253 struct dma_buf *dma_buf = attach->dmabuf;
254 struct drm_gem_object *obj = dma_buf->priv;
255 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
256 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
257 struct sg_table *sgt;
260 if (!bo->tbo.pin_count) {
261 /* move buffer into GTT or VRAM */
262 struct ttm_operation_ctx ctx = { false, false };
263 unsigned domains = AMDGPU_GEM_DOMAIN_GTT;
265 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
267 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
268 domains |= AMDGPU_GEM_DOMAIN_VRAM;
270 amdgpu_bo_placement_from_domain(bo, domains);
271 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
275 } else if (!(amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type) &
276 AMDGPU_GEM_DOMAIN_GTT)) {
277 return ERR_PTR(-EBUSY);
280 switch (bo->tbo.mem.mem_type) {
282 sgt = drm_prime_pages_to_sg(obj->dev,
284 bo->tbo.ttm->num_pages);
288 if (dma_map_sgtable(attach->dev, sgt, dir,
289 DMA_ATTR_SKIP_CPU_SYNC))
294 r = amdgpu_vram_mgr_alloc_sgt(adev, &bo->tbo.mem, attach->dev,
300 return ERR_PTR(-EINVAL);
308 return ERR_PTR(-EBUSY);
312 * amdgpu_dma_buf_unmap - &dma_buf_ops.unmap_dma_buf implementation
313 * @attach: DMA-buf attachment
314 * @sgt: sg_table to unmap
315 * @dir: DMA direction
317 * This is called when a shared DMA buffer no longer needs to be accessible by
318 * another device. For now, simply unpins the buffer from GTT.
320 static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,
321 struct sg_table *sgt,
322 enum dma_data_direction dir)
324 struct dma_buf *dma_buf = attach->dmabuf;
325 struct drm_gem_object *obj = dma_buf->priv;
326 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
327 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
329 if (sgt->sgl->page_link) {
330 dma_unmap_sgtable(attach->dev, sgt, dir, 0);
334 amdgpu_vram_mgr_free_sgt(adev, attach->dev, dir, sgt);
339 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
340 * @dma_buf: Shared DMA buffer
341 * @direction: Direction of DMA transfer
343 * This is called before CPU access to the shared DMA buffer's memory. If it's
344 * a read access, the buffer is moved to the GTT domain if possible, for optimal
345 * CPU read performance.
348 * 0 on success or a negative error code on failure.
350 static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
351 enum dma_data_direction direction)
353 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
354 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
355 struct ttm_operation_ctx ctx = { true, false };
356 u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
358 bool reads = (direction == DMA_BIDIRECTIONAL ||
359 direction == DMA_FROM_DEVICE);
361 if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
365 ret = amdgpu_bo_reserve(bo, false);
366 if (unlikely(ret != 0))
369 if (!bo->tbo.pin_count &&
370 (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
371 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
372 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
375 amdgpu_bo_unreserve(bo);
379 const struct dma_buf_ops amdgpu_dmabuf_ops = {
380 .attach = amdgpu_dma_buf_attach,
381 .detach = amdgpu_dma_buf_detach,
382 .pin = amdgpu_dma_buf_pin,
383 .unpin = amdgpu_dma_buf_unpin,
384 .map_dma_buf = amdgpu_dma_buf_map,
385 .unmap_dma_buf = amdgpu_dma_buf_unmap,
386 .release = drm_gem_dmabuf_release,
387 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
388 .mmap = drm_gem_dmabuf_mmap,
389 .vmap = drm_gem_dmabuf_vmap,
390 .vunmap = drm_gem_dmabuf_vunmap,
394 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
396 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
398 * The main work is done by the &drm_gem_prime_export helper.
401 * Shared DMA buffer representing the GEM BO from the given device.
403 struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
406 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
409 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
410 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
411 return ERR_PTR(-EPERM);
413 buf = drm_gem_prime_export(gobj, flags);
415 buf->ops = &amdgpu_dmabuf_ops;
421 * amdgpu_dma_buf_create_obj - create BO for DMA-buf import
426 * Creates an empty SG BO for DMA-buf import.
429 * A new GEM BO of the given DRM device, representing the memory
430 * described by the given DMA-buf attachment and scatter/gather table.
432 static struct drm_gem_object *
433 amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
435 struct dma_resv *resv = dma_buf->resv;
436 struct amdgpu_device *adev = drm_to_adev(dev);
437 struct amdgpu_bo *bo;
438 struct amdgpu_bo_param bp;
439 struct drm_gem_object *gobj;
442 memset(&bp, 0, sizeof(bp));
443 bp.size = dma_buf->size;
444 bp.byte_align = PAGE_SIZE;
445 bp.domain = AMDGPU_GEM_DOMAIN_CPU;
447 bp.type = ttm_bo_type_sg;
449 dma_resv_lock(resv, NULL);
450 ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
451 AMDGPU_GEM_DOMAIN_CPU,
452 0, ttm_bo_type_sg, resv, &gobj);
456 bo = gem_to_amdgpu_bo(gobj);
457 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
458 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
459 if (dma_buf->ops != &amdgpu_dmabuf_ops)
460 bo->prime_shared_count = 1;
462 dma_resv_unlock(resv);
466 dma_resv_unlock(resv);
471 * amdgpu_dma_buf_move_notify - &attach.move_notify implementation
473 * @attach: the DMA-buf attachment
475 * Invalidate the DMA-buf attachment, making sure that the we re-create the
476 * mapping before the next use.
479 amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
481 struct drm_gem_object *obj = attach->importer_priv;
482 struct ww_acquire_ctx *ticket = dma_resv_locking_ctx(obj->resv);
483 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
484 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
485 struct ttm_operation_ctx ctx = { false, false };
486 struct ttm_placement placement = {};
487 struct amdgpu_vm_bo_base *bo_base;
490 if (bo->tbo.mem.mem_type == TTM_PL_SYSTEM)
493 r = ttm_bo_validate(&bo->tbo, &placement, &ctx);
495 DRM_ERROR("Failed to invalidate DMA-buf import (%d))\n", r);
499 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
500 struct amdgpu_vm *vm = bo_base->vm;
501 struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
504 /* When we get an error here it means that somebody
505 * else is holding the VM lock and updating page tables
506 * So we can just continue here.
508 r = dma_resv_lock(resv, ticket);
513 /* TODO: This is more problematic and we actually need
514 * to allow page tables updates without holding the
517 if (!dma_resv_trylock(resv))
521 r = amdgpu_vm_clear_freed(adev, vm, NULL);
523 r = amdgpu_vm_handle_moved(adev, vm);
525 if (r && r != -EBUSY)
526 DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
529 dma_resv_unlock(resv);
533 static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = {
534 .allow_peer2peer = true,
535 .move_notify = amdgpu_dma_buf_move_notify
539 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
541 * @dma_buf: Shared DMA buffer
543 * Import a dma_buf into a the driver and potentially create a new GEM object.
546 * GEM BO representing the shared DMA buffer for the given device.
548 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
549 struct dma_buf *dma_buf)
551 struct dma_buf_attachment *attach;
552 struct drm_gem_object *obj;
554 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
556 if (obj->dev == dev) {
558 * Importing dmabuf exported from out own gem increases
559 * refcount on gem itself instead of f_count of dmabuf.
561 drm_gem_object_get(obj);
566 obj = amdgpu_dma_buf_create_obj(dev, dma_buf);
570 attach = dma_buf_dynamic_attach(dma_buf, dev->dev,
571 &amdgpu_dma_buf_attach_ops, obj);
572 if (IS_ERR(attach)) {
573 drm_gem_object_put(obj);
574 return ERR_CAST(attach);
577 get_dma_buf(dma_buf);
578 obj->import_attach = attach;
583 * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer
585 * @adev: amdgpu_device pointer of the importer
586 * @bo: amdgpu buffer object
589 * True if dmabuf accessible over xgmi, false otherwise.
591 bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
592 struct amdgpu_bo *bo)
594 struct drm_gem_object *obj = &bo->tbo.base;
595 struct drm_gem_object *gobj;
597 if (obj->import_attach) {
598 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
600 if (dma_buf->ops != &amdgpu_dmabuf_ops)
601 /* No XGMI with non AMD GPUs */
604 gobj = dma_buf->priv;
605 bo = gem_to_amdgpu_bo(gobj);
608 if (amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
609 (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM))