drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_i2c.h"
  30 #include "atom.h"
  31 #include "amdgpu_connectors.h"
  32 #include "amdgpu_display.h"
  33 #include "soc15_common.h"
  34 #include "gc/gc_11_0_0_offset.h"
  35 #include "gc/gc_11_0_0_sh_mask.h"
  36 #include <asm/div64.h>
  37
  38 #include <linux/pci.h>
  39 #include <linux/pm_runtime.h>
  40 #include <drm/drm_crtc_helper.h>
  41 #include <drm/drm_edid.h>
  42 #include <drm/drm_gem_framebuffer_helper.h>
  43 #include <drm/drm_fb_helper.h>
  44 #include <drm/drm_fourcc.h>
  45 #include <drm/drm_vblank.h>
  46
  47 /**
  48  * amdgpu_display_hotplug_work_func - work handler for display hotplug event
  49  *
  50  * @work: work struct pointer
  51  *
  52  * This is the hotplug event work handler (all ASICs).
  53  * The work gets scheduled from the IRQ handler if there
  54  * was a hotplug interrupt.  It walks through the connector table
  55  * and calls hotplug handler for each connector. After this, it sends
  56  * a DRM hotplug event to alert userspace.
  57  *
  58  * This design approach is required in order to defer hotplug event handling
  59  * from the IRQ handler to a work handler because hotplug handler has to use
  60  * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
  61  * sleep).
  62  */
  63 void amdgpu_display_hotplug_work_func(struct work_struct *work)
  64 {
  65         struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
  66                                                   hotplug_work);
  67         struct drm_device *dev = adev_to_drm(adev);
  68         struct drm_mode_config *mode_config = &dev->mode_config;
  69         struct drm_connector *connector;
  70         struct drm_connector_list_iter iter;
  71
  72         mutex_lock(&mode_config->mutex);
  73         drm_connector_list_iter_begin(dev, &iter);
  74         drm_for_each_connector_iter(connector, &iter)
  75                 amdgpu_connector_hotplug(connector);
  76         drm_connector_list_iter_end(&iter);
  77         mutex_unlock(&mode_config->mutex);
  78         /* Just fire off a uevent and let userspace tell us what to do */
  79         drm_helper_hpd_irq_event(dev);
  80 }
  81
  82 static int amdgpu_display_framebuffer_init(struct drm_device *dev,
  83                                            struct amdgpu_framebuffer *rfb,
  84                                            const struct drm_mode_fb_cmd2 *mode_cmd,
  85                                            struct drm_gem_object *obj);
  86
  87 static void amdgpu_display_flip_callback(struct dma_fence *f,
  88                                          struct dma_fence_cb *cb)
  89 {
  90         struct amdgpu_flip_work *work =
  91                 container_of(cb, struct amdgpu_flip_work, cb);
  92
  93         dma_fence_put(f);
  94         schedule_work(&work->flip_work.work);
  95 }
  96
  97 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
  98                                              struct dma_fence **f)
  99 {
 100         struct dma_fence *fence= *f;
 101
 102         if (fence == NULL)
 103                 return false;
 104
 105         *f = NULL;
 106
 107         if (!dma_fence_add_callback(fence, &work->cb,
 108                                     amdgpu_display_flip_callback))
 109                 return true;
 110
 111         dma_fence_put(fence);
 112         return false;
 113 }
 114
 115 static void amdgpu_display_flip_work_func(struct work_struct *__work)
 116 {
 117         struct delayed_work *delayed_work =
 118                 container_of(__work, struct delayed_work, work);
 119         struct amdgpu_flip_work *work =
 120                 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
 121         struct amdgpu_device *adev = work->adev;
 122         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
 123
 124         struct drm_crtc *crtc = &amdgpu_crtc->base;
 125         unsigned long flags;
 126         unsigned i;
 127         int vpos, hpos;
 128
 129         for (i = 0; i < work->shared_count; ++i)
 130                 if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
 131                         return;
 132
 133         /* Wait until we're out of the vertical blank period before the one
 134          * targeted by the flip
 135          */
 136         if (amdgpu_crtc->enabled &&
 137             (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
 138                                                 &vpos, &hpos, NULL, NULL,
 139                                                 &crtc->hwmode)
 140              & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
 141             (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
 142             (int)(work->target_vblank -
 143                   amdgpu_get_vblank_counter_kms(crtc)) > 0) {
 144                 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
 145                 return;
 146         }
 147
 148         /* We borrow the event spin lock for protecting flip_status */
 149         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 150
 151         /* Do the flip (mmio) */
 152         adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
 153
 154         /* Set the flip status */
 155         amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
 156         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 157
 158
 159         drm_dbg_vbl(adev_to_drm(adev),
 160                     "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
 161                     amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 162
 163 }
 164
 165 /*
 166  * Handle unpin events outside the interrupt handler proper.
 167  */
 168 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
 169 {
 170         struct amdgpu_flip_work *work =
 171                 container_of(__work, struct amdgpu_flip_work, unpin_work);
 172         int r;
 173
 174         /* unpin of the old buffer */
 175         r = amdgpu_bo_reserve(work->old_abo, true);
 176         if (likely(r == 0)) {
 177                 amdgpu_bo_unpin(work->old_abo);
 178                 amdgpu_bo_unreserve(work->old_abo);
 179         } else
 180                 DRM_ERROR("failed to reserve buffer after flip\n");
 181
 182         amdgpu_bo_unref(&work->old_abo);
 183         kfree(work->shared);
 184         kfree(work);
 185 }
 186
 187 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
 188                                 struct drm_framebuffer *fb,
 189                                 struct drm_pending_vblank_event *event,
 190                                 uint32_t page_flip_flags, uint32_t target,
 191                                 struct drm_modeset_acquire_ctx *ctx)
 192 {
 193         struct drm_device *dev = crtc->dev;
 194         struct amdgpu_device *adev = drm_to_adev(dev);
 195         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 196         struct drm_gem_object *obj;
 197         struct amdgpu_flip_work *work;
 198         struct amdgpu_bo *new_abo;
 199         unsigned long flags;
 200         u64 tiling_flags;
 201         int i, r;
 202
 203         work = kzalloc(sizeof *work, GFP_KERNEL);
 204         if (work == NULL)
 205                 return -ENOMEM;
 206
 207         INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
 208         INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
 209
 210         work->event = event;
 211         work->adev = adev;
 212         work->crtc_id = amdgpu_crtc->crtc_id;
 213         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 214
 215         /* schedule unpin of the old buffer */
 216         obj = crtc->primary->fb->obj[0];
 217
 218         /* take a reference to the old object */
 219         work->old_abo = gem_to_amdgpu_bo(obj);
 220         amdgpu_bo_ref(work->old_abo);
 221
 222         obj = fb->obj[0];
 223         new_abo = gem_to_amdgpu_bo(obj);
 224
 225         /* pin the new buffer */
 226         r = amdgpu_bo_reserve(new_abo, false);
 227         if (unlikely(r != 0)) {
 228                 DRM_ERROR("failed to reserve new abo buffer before flip\n");
 229                 goto cleanup;
 230         }
 231
 232         if (!adev->enable_virtual_display) {
 233                 r = amdgpu_bo_pin(new_abo,
 234                                   amdgpu_display_supported_domains(adev, new_abo->flags));
 235                 if (unlikely(r != 0)) {
 236                         DRM_ERROR("failed to pin new abo buffer before flip\n");
 237                         goto unreserve;
 238                 }
 239         }
 240
 241         r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
 242         if (unlikely(r != 0)) {
 243                 DRM_ERROR("%p bind failed\n", new_abo);
 244                 goto unpin;
 245         }
 246
 247         r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE,
 248                                 &work->shared_count,
 249                                 &work->shared);
 250         if (unlikely(r != 0)) {
 251                 DRM_ERROR("failed to get fences for buffer\n");
 252                 goto unpin;
 253         }
 254
 255         amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
 256         amdgpu_bo_unreserve(new_abo);
 257
 258         if (!adev->enable_virtual_display)
 259                 work->base = amdgpu_bo_gpu_offset(new_abo);
 260         work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
 261                 amdgpu_get_vblank_counter_kms(crtc);
 262
 263         /* we borrow the event spin lock for protecting flip_wrok */
 264         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 265         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
 266                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 267                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 268                 r = -EBUSY;
 269                 goto pflip_cleanup;
 270         }
 271
 272         amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
 273         amdgpu_crtc->pflip_works = work;
 274
 275
 276         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
 277                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 278         /* update crtc fb */
 279         crtc->primary->fb = fb;
 280         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 281         amdgpu_display_flip_work_func(&work->flip_work.work);
 282         return 0;
 283
 284 pflip_cleanup:
 285         if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
 286                 DRM_ERROR("failed to reserve new abo in error path\n");
 287                 goto cleanup;
 288         }
 289 unpin:
 290         if (!adev->enable_virtual_display)
 291                 amdgpu_bo_unpin(new_abo);
 292
 293 unreserve:
 294         amdgpu_bo_unreserve(new_abo);
 295
 296 cleanup:
 297         amdgpu_bo_unref(&work->old_abo);
 298         for (i = 0; i < work->shared_count; ++i)
 299                 dma_fence_put(work->shared[i]);
 300         kfree(work->shared);
 301         kfree(work);
 302
 303         return r;
 304 }
 305
 306 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
 307                                    struct drm_modeset_acquire_ctx *ctx)
 308 {
 309         struct drm_device *dev;
 310         struct amdgpu_device *adev;
 311         struct drm_crtc *crtc;
 312         bool active = false;
 313         int ret;
 314
 315         if (!set || !set->crtc)
 316                 return -EINVAL;
 317
 318         dev = set->crtc->dev;
 319
 320         ret = pm_runtime_get_sync(dev->dev);
 321         if (ret < 0)
 322                 goto out;
 323
 324         ret = drm_crtc_helper_set_config(set, ctx);
 325
 326         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 327                 if (crtc->enabled)
 328                         active = true;
 329
 330         pm_runtime_mark_last_busy(dev->dev);
 331
 332         adev = drm_to_adev(dev);
 333         /* if we have active crtcs and we don't have a power ref,
 334            take the current one */
 335         if (active && !adev->have_disp_power_ref) {
 336                 adev->have_disp_power_ref = true;
 337                 return ret;
 338         }
 339         /* if we have no active crtcs, then drop the power ref
 340            we got before */
 341         if (!active && adev->have_disp_power_ref) {
 342                 pm_runtime_put_autosuspend(dev->dev);
 343                 adev->have_disp_power_ref = false;
 344         }
 345
 346 out:
 347         /* drop the power reference we got coming in here */
 348         pm_runtime_put_autosuspend(dev->dev);
 349         return ret;
 350 }
 351
 352 static const char *encoder_names[41] = {
 353         "NONE",
 354         "INTERNAL_LVDS",
 355         "INTERNAL_TMDS1",
 356         "INTERNAL_TMDS2",
 357         "INTERNAL_DAC1",
 358         "INTERNAL_DAC2",
 359         "INTERNAL_SDVOA",
 360         "INTERNAL_SDVOB",
 361         "SI170B",
 362         "CH7303",
 363         "CH7301",
 364         "INTERNAL_DVO1",
 365         "EXTERNAL_SDVOA",
 366         "EXTERNAL_SDVOB",
 367         "TITFP513",
 368         "INTERNAL_LVTM1",
 369         "VT1623",
 370         "HDMI_SI1930",
 371         "HDMI_INTERNAL",
 372         "INTERNAL_KLDSCP_TMDS1",
 373         "INTERNAL_KLDSCP_DVO1",
 374         "INTERNAL_KLDSCP_DAC1",
 375         "INTERNAL_KLDSCP_DAC2",
 376         "SI178",
 377         "MVPU_FPGA",
 378         "INTERNAL_DDI",
 379         "VT1625",
 380         "HDMI_SI1932",
 381         "DP_AN9801",
 382         "DP_DP501",
 383         "INTERNAL_UNIPHY",
 384         "INTERNAL_KLDSCP_LVTMA",
 385         "INTERNAL_UNIPHY1",
 386         "INTERNAL_UNIPHY2",
 387         "NUTMEG",
 388         "TRAVIS",
 389         "INTERNAL_VCE",
 390         "INTERNAL_UNIPHY3",
 391         "HDMI_ANX9805",
 392         "INTERNAL_AMCLK",
 393         "VIRTUAL",
 394 };
 395
 396 static const char *hpd_names[6] = {
 397         "HPD1",
 398         "HPD2",
 399         "HPD3",
 400         "HPD4",
 401         "HPD5",
 402         "HPD6",
 403 };
 404
 405 void amdgpu_display_print_display_setup(struct drm_device *dev)
 406 {
 407         struct drm_connector *connector;
 408         struct amdgpu_connector *amdgpu_connector;
 409         struct drm_encoder *encoder;
 410         struct amdgpu_encoder *amdgpu_encoder;
 411         struct drm_connector_list_iter iter;
 412         uint32_t devices;
 413         int i = 0;
 414
 415         drm_connector_list_iter_begin(dev, &iter);
 416         DRM_INFO("AMDGPU Display Connectors\n");
 417         drm_for_each_connector_iter(connector, &iter) {
 418                 amdgpu_connector = to_amdgpu_connector(connector);
 419                 DRM_INFO("Connector %d:\n", i);
 420                 DRM_INFO("  %s\n", connector->name);
 421                 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
 422                         DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
 423                 if (amdgpu_connector->ddc_bus) {
 424                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 425                                  amdgpu_connector->ddc_bus->rec.mask_clk_reg,
 426                                  amdgpu_connector->ddc_bus->rec.mask_data_reg,
 427                                  amdgpu_connector->ddc_bus->rec.a_clk_reg,
 428                                  amdgpu_connector->ddc_bus->rec.a_data_reg,
 429                                  amdgpu_connector->ddc_bus->rec.en_clk_reg,
 430                                  amdgpu_connector->ddc_bus->rec.en_data_reg,
 431                                  amdgpu_connector->ddc_bus->rec.y_clk_reg,
 432                                  amdgpu_connector->ddc_bus->rec.y_data_reg);
 433                         if (amdgpu_connector->router.ddc_valid)
 434                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 435                                          amdgpu_connector->router.ddc_mux_control_pin,
 436                                          amdgpu_connector->router.ddc_mux_state);
 437                         if (amdgpu_connector->router.cd_valid)
 438                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 439                                          amdgpu_connector->router.cd_mux_control_pin,
 440                                          amdgpu_connector->router.cd_mux_state);
 441                 } else {
 442                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 443                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 444                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 445                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 446                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 447                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 448                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 449                 }
 450                 DRM_INFO("  Encoders:\n");
 451                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 452                         amdgpu_encoder = to_amdgpu_encoder(encoder);
 453                         devices = amdgpu_encoder->devices & amdgpu_connector->devices;
 454                         if (devices) {
 455                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 456                                         DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 457                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 458                                         DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 459                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 460                                         DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 461                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 462                                         DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 463                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 464                                         DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 465                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 466                                         DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 467                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 468                                         DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 469                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 470                                         DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 471                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 472                                         DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 473                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 474                                         DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 475                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 476                                         DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 477                         }
 478                 }
 479                 i++;
 480         }
 481         drm_connector_list_iter_end(&iter);
 482 }
 483
 484 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
 485                               bool use_aux)
 486 {
 487         u8 out = 0x0;
 488         u8 buf[8];
 489         int ret;
 490         struct i2c_msg msgs[] = {
 491                 {
 492                         .addr = DDC_ADDR,
 493                         .flags = 0,
 494                         .len = 1,
 495                         .buf = &out,
 496                 },
 497                 {
 498                         .addr = DDC_ADDR,
 499                         .flags = I2C_M_RD,
 500                         .len = 8,
 501                         .buf = buf,
 502                 }
 503         };
 504
 505         /* on hw with routers, select right port */
 506         if (amdgpu_connector->router.ddc_valid)
 507                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 508
 509         if (use_aux) {
 510                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
 511         } else {
 512                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
 513         }
 514
 515         if (ret != 2)
 516                 /* Couldn't find an accessible DDC on this connector */
 517                 return false;
 518         /* Probe also for valid EDID header
 519          * EDID header starts with:
 520          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
 521          * Only the first 6 bytes must be valid as
 522          * drm_edid_block_valid() can fix the last 2 bytes */
 523         if (drm_edid_header_is_valid(buf) < 6) {
 524                 /* Couldn't find an accessible EDID on this
 525                  * connector */
 526                 return false;
 527         }
 528         return true;
 529 }
 530
 531 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
 532         .destroy = drm_gem_fb_destroy,
 533         .create_handle = drm_gem_fb_create_handle,
 534 };
 535
 536 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 537                                           uint64_t bo_flags)
 538 {
 539         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 540
 541 #if defined(CONFIG_DRM_AMD_DC)
 542         /*
 543          * if amdgpu_bo_support_uswc returns false it means that USWC mappings
 544          * is not supported for this board. But this mapping is required
 545          * to avoid hang caused by placement of scanout BO in GTT on certain
 546          * APUs. So force the BO placement to VRAM in case this architecture
 547          * will not allow USWC mappings.
 548          * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
 549          */
 550         if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
 551             amdgpu_bo_support_uswc(bo_flags) &&
 552             adev->dc_enabled &&
 553             adev->mode_info.gpu_vm_support)
 554                 domain |= AMDGPU_GEM_DOMAIN_GTT;
 555 #endif
 556
 557         return domain;
 558 }
 559
 560 static const struct drm_format_info dcc_formats[] = {
 561         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 562           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 563          { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
 564           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 565         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
 566           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 567            .has_alpha = true, },
 568         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
 569           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 570           .has_alpha = true, },
 571         { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
 572           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 573           .has_alpha = true, },
 574         { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
 575           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 576         { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
 577           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 578         { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
 579           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 580           .has_alpha = true, },
 581         { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
 582           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 583           .has_alpha = true, },
 584         { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
 585           .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 586 };
 587
 588 static const struct drm_format_info dcc_retile_formats[] = {
 589         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
 590           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 591          { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
 592           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 593         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
 594           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 595            .has_alpha = true, },
 596         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
 597           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 598           .has_alpha = true, },
 599         { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
 600           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 601           .has_alpha = true, },
 602         { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
 603           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 604         { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
 605           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 606         { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
 607           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 608           .has_alpha = true, },
 609         { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
 610           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 611           .has_alpha = true, },
 612         { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
 613           .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 614 };
 615
 616 static const struct drm_format_info *
 617 lookup_format_info(const struct drm_format_info formats[],
 618                   int num_formats, u32 format)
 619 {
 620         int i;
 621
 622         for (i = 0; i < num_formats; i++) {
 623                 if (formats[i].format == format)
 624                         return &formats[i];
 625         }
 626
 627         return NULL;
 628 }
 629
 630 const struct drm_format_info *
 631 amdgpu_lookup_format_info(u32 format, uint64_t modifier)
 632 {
 633         if (!IS_AMD_FMT_MOD(modifier))
 634                 return NULL;
 635
 636         if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
 637                 return lookup_format_info(dcc_retile_formats,
 638                                           ARRAY_SIZE(dcc_retile_formats),
 639                                           format);
 640
 641         if (AMD_FMT_MOD_GET(DCC, modifier))
 642                 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
 643                                           format);
 644
 645         /* returning NULL will cause the default format structs to be used. */
 646         return NULL;
 647 }
 648
 649
 650 /*
 651  * Tries to extract the renderable DCC offset from the opaque metadata attached
 652  * to the buffer.
 653  */
 654 static int
 655 extract_render_dcc_offset(struct amdgpu_device *adev,
 656                           struct drm_gem_object *obj,
 657                           uint64_t *offset)
 658 {
 659         struct amdgpu_bo *rbo;
 660         int r = 0;
 661         uint32_t metadata[10]; /* Something that fits a descriptor + header. */
 662         uint32_t size;
 663
 664         rbo = gem_to_amdgpu_bo(obj);
 665         r = amdgpu_bo_reserve(rbo, false);
 666
 667         if (unlikely(r)) {
 668                 /* Don't show error message when returning -ERESTARTSYS */
 669                 if (r != -ERESTARTSYS)
 670                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
 671                 return r;
 672         }
 673
 674         r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
 675         amdgpu_bo_unreserve(rbo);
 676
 677         if (r)
 678                 return r;
 679
 680         /*
 681          * The first word is the metadata version, and we need space for at least
 682          * the version + pci vendor+device id + 8 words for a descriptor.
 683          */
 684         if (size < 40  || metadata[0] != 1)
 685                 return -EINVAL;
 686
 687         if (adev->family >= AMDGPU_FAMILY_NV) {
 688                 /* resource word 6/7 META_DATA_ADDRESS{_LO} */
 689                 *offset = ((u64)metadata[9] << 16u) |
 690                           ((metadata[8] & 0xFF000000u) >> 16);
 691         } else {
 692                 /* resource word 5/7 META_DATA_ADDRESS */
 693                 *offset = ((u64)metadata[9] << 8u) |
 694                           ((u64)(metadata[7] & 0x1FE0000u) << 23);
 695         }
 696
 697         return 0;
 698 }
 699
 700 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 701 {
 702         struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
 703         uint64_t modifier = 0;
 704         int num_pipes = 0;
 705         int num_pkrs = 0;
 706
 707         num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
 708         num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes;
 709
 710         if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
 711                 modifier = DRM_FORMAT_MOD_LINEAR;
 712         } else {
 713                 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
 714                 bool has_xor = swizzle >= 16;
 715                 int block_size_bits;
 716                 int version;
 717                 int pipe_xor_bits = 0;
 718                 int bank_xor_bits = 0;
 719                 int packers = 0;
 720                 int rb = 0;
 721                 int pipes = ilog2(num_pipes);
 722                 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
 723
 724                 switch (swizzle >> 2) {
 725                 case 0: /* 256B */
 726                         block_size_bits = 8;
 727                         break;
 728                 case 1: /* 4KiB */
 729                 case 5: /* 4KiB _X */
 730                         block_size_bits = 12;
 731                         break;
 732                 case 2: /* 64KiB */
 733                 case 4: /* 64 KiB _T */
 734                 case 6: /* 64 KiB _X */
 735                         block_size_bits = 16;
 736                         break;
 737                 case 7: /* 256 KiB */
 738                         block_size_bits = 18;
 739                         break;
 740                 default:
 741                         /* RESERVED or VAR */
 742                         return -EINVAL;
 743                 }
 744
 745                 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
 746                         version = AMD_FMT_MOD_TILE_VER_GFX11;
 747                 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
 748                         version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 749                 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0))
 750                         version = AMD_FMT_MOD_TILE_VER_GFX10;
 751                 else
 752                         version = AMD_FMT_MOD_TILE_VER_GFX9;
 753
 754                 switch (swizzle & 3) {
 755                 case 0: /* Z microtiling */
 756                         return -EINVAL;
 757                 case 1: /* S microtiling */
 758                         if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
 759                                 if (!has_xor)
 760                                         version = AMD_FMT_MOD_TILE_VER_GFX9;
 761                         }
 762                         break;
 763                 case 2:
 764                         if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) {
 765                                 if (!has_xor && afb->base.format->cpp[0] != 4)
 766                                         version = AMD_FMT_MOD_TILE_VER_GFX9;
 767                         }
 768                         break;
 769                 case 3:
 770                         break;
 771                 }
 772
 773                 if (has_xor) {
 774                         if (num_pipes == num_pkrs && num_pkrs == 0) {
 775                                 DRM_ERROR("invalid number of pipes and packers\n");
 776                                 return -EINVAL;
 777                         }
 778
 779                         switch (version) {
 780                         case AMD_FMT_MOD_TILE_VER_GFX11:
 781                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 782                                 packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
 783                                 break;
 784                         case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
 785                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 786                                 packers = min(block_size_bits - 8 - pipe_xor_bits,
 787                                               ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
 788                                 break;
 789                         case AMD_FMT_MOD_TILE_VER_GFX10:
 790                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 791                                 break;
 792                         case AMD_FMT_MOD_TILE_VER_GFX9:
 793                                 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
 794                                      ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
 795                                 pipe_xor_bits = min(block_size_bits - 8, pipes +
 796                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
 797                                 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
 798                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
 799                                 break;
 800                         }
 801                 }
 802
 803                 modifier = AMD_FMT_MOD |
 804                            AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
 805                            AMD_FMT_MOD_SET(TILE_VERSION, version) |
 806                            AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
 807                            AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
 808                            AMD_FMT_MOD_SET(PACKERS, packers);
 809
 810                 if (dcc_offset != 0) {
 811                         bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
 812                         bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 813                         const struct drm_format_info *format_info;
 814                         u64 render_dcc_offset;
 815
 816                         /* Enable constant encode on RAVEN2 and later. */
 817                         bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN ||
 818                                                    (adev->asic_type == CHIP_RAVEN &&
 819                                                     adev->external_rev_id >= 0x81)) &&
 820                                                     adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0);
 821
 822                         int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
 823                                               dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
 824                                               AMD_FMT_MOD_DCC_BLOCK_256B;
 825
 826                         modifier |= AMD_FMT_MOD_SET(DCC, 1) |
 827                                     AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
 828                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
 829                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
 830                                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
 831
 832                         afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
 833                         afb->base.pitches[1] =
 834                                 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
 835
 836                         /*
 837                          * If the userspace driver uses retiling the tiling flags do not contain
 838                          * info on the renderable DCC buffer. Luckily the opaque metadata contains
 839                          * the info so we can try to extract it. The kernel does not use this info
 840                          * but we should convert it to a modifier plane for getfb2, so the
 841                          * userspace driver that gets it doesn't have to juggle around another DCC
 842                          * plane internally.
 843                          */
 844                         if (extract_render_dcc_offset(adev, afb->base.obj[0],
 845                                                       &render_dcc_offset) == 0 &&
 846                             render_dcc_offset != 0 &&
 847                             render_dcc_offset != afb->base.offsets[1] &&
 848                             render_dcc_offset < UINT_MAX) {
 849                                 uint32_t dcc_block_bits;  /* of base surface data */
 850
 851                                 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
 852                                 afb->base.offsets[2] = render_dcc_offset;
 853
 854                                 if (adev->family >= AMDGPU_FAMILY_NV) {
 855                                         int extra_pipe = 0;
 856
 857                                         if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) &&
 858                                             pipes == packers && pipes > 1)
 859                                                 extra_pipe = 1;
 860
 861                                         dcc_block_bits = max(20, 16 + pipes + extra_pipe);
 862                                 } else {
 863                                         modifier |= AMD_FMT_MOD_SET(RB, rb) |
 864                                                     AMD_FMT_MOD_SET(PIPE, pipes);
 865                                         dcc_block_bits = max(20, 18 + rb);
 866                                 }
 867
 868                                 dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
 869                                 afb->base.pitches[2] = ALIGN(afb->base.width,
 870                                                              1u << ((dcc_block_bits + 1) / 2));
 871                         }
 872                         format_info = amdgpu_lookup_format_info(afb->base.format->format,
 873                                                                 modifier);
 874                         if (!format_info)
 875                                 return -EINVAL;
 876
 877                         afb->base.format = format_info;
 878                 }
 879         }
 880
 881         afb->base.modifier = modifier;
 882         afb->base.flags |= DRM_MODE_FB_MODIFIERS;
 883         return 0;
 884 }
 885
 886 /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */
 887 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
 888 {
 889         u64 micro_tile_mode;
 890
 891         /* Zero swizzle mode means linear */
 892         if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0)
 893                 return 0;
 894
 895         micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
 896         switch (micro_tile_mode) {
 897         case 0: /* DISPLAY */
 898         case 3: /* RENDER */
 899                 return 0;
 900         default:
 901                 drm_dbg_kms(afb->base.dev,
 902                             "Micro tile mode %llu not supported for scanout\n",
 903                             micro_tile_mode);
 904                 return -EINVAL;
 905         }
 906 }
 907
 908 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
 909                                  unsigned int *width, unsigned int *height)
 910 {
 911         unsigned int cpp_log2 = ilog2(cpp);
 912         unsigned int pixel_log2 = block_log2 - cpp_log2;
 913         unsigned int width_log2 = (pixel_log2 + 1) / 2;
 914         unsigned int height_log2 = pixel_log2 - width_log2;
 915
 916         *width = 1 << width_log2;
 917         *height = 1 << height_log2;
 918 }
 919
 920 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
 921                                        bool pipe_aligned)
 922 {
 923         unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
 924
 925         switch (ver) {
 926         case AMD_FMT_MOD_TILE_VER_GFX9: {
 927                 /*
 928                  * TODO: for pipe aligned we may need to check the alignment of the
 929                  * total size of the surface, which may need to be bigger than the
 930                  * natural alignment due to some HW workarounds
 931                  */
 932                 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
 933         }
 934         case AMD_FMT_MOD_TILE_VER_GFX10:
 935         case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
 936         case AMD_FMT_MOD_TILE_VER_GFX11: {
 937                 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
 938
 939                 if (ver >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
 940                     AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
 941                         ++pipes_log2;
 942
 943                 return max(8 + (pipe_aligned ? pipes_log2 : 0), 12);
 944         }
 945         default:
 946                 return 0;
 947         }
 948 }
 949
 950 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,
 951                                        const struct drm_format_info *format,
 952                                        unsigned int block_width, unsigned int block_height,
 953                                        unsigned int block_size_log2)
 954 {
 955         unsigned int width = rfb->base.width /
 956                 ((plane && plane < format->num_planes) ? format->hsub : 1);
 957         unsigned int height = rfb->base.height /
 958                 ((plane && plane < format->num_planes) ? format->vsub : 1);
 959         unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1;
 960         unsigned int block_pitch = block_width * cpp;
 961         unsigned int min_pitch = ALIGN(width * cpp, block_pitch);
 962         unsigned int block_size = 1 << block_size_log2;
 963         uint64_t size;
 964
 965         if (rfb->base.pitches[plane] % block_pitch) {
 966                 drm_dbg_kms(rfb->base.dev,
 967                             "pitch %d for plane %d is not a multiple of block pitch %d\n",
 968                             rfb->base.pitches[plane], plane, block_pitch);
 969                 return -EINVAL;
 970         }
 971         if (rfb->base.pitches[plane] < min_pitch) {
 972                 drm_dbg_kms(rfb->base.dev,
 973                             "pitch %d for plane %d is less than minimum pitch %d\n",
 974                             rfb->base.pitches[plane], plane, min_pitch);
 975                 return -EINVAL;
 976         }
 977
 978         /* Force at least natural alignment. */
 979         if (rfb->base.offsets[plane] % block_size) {
 980                 drm_dbg_kms(rfb->base.dev,
 981                             "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n",
 982                             rfb->base.offsets[plane], plane, block_size);
 983                 return -EINVAL;
 984         }
 985
 986         size = rfb->base.offsets[plane] +
 987                 (uint64_t)rfb->base.pitches[plane] / block_pitch *
 988                 block_size * DIV_ROUND_UP(height, block_height);
 989
 990         if (rfb->base.obj[0]->size < size) {
 991                 drm_dbg_kms(rfb->base.dev,
 992                             "BO size 0x%zx is less than 0x%llx required for plane %d\n",
 993                             rfb->base.obj[0]->size, size, plane);
 994                 return -EINVAL;
 995         }
 996
 997         return 0;
 998 }
 999
1000
1001 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
1002 {
1003         const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format);
1004         uint64_t modifier = rfb->base.modifier;
1005         int ret;
1006         unsigned int i, block_width, block_height, block_size_log2;
1007
1008         if (rfb->base.dev->mode_config.fb_modifiers_not_supported)
1009                 return 0;
1010
1011         for (i = 0; i < format_info->num_planes; ++i) {
1012                 if (modifier == DRM_FORMAT_MOD_LINEAR) {
1013                         block_width = 256 / format_info->cpp[i];
1014                         block_height = 1;
1015                         block_size_log2 = 8;
1016                 } else {
1017                         int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
1018
1019                         switch ((swizzle & ~3) + 1) {
1020                         case DC_SW_256B_S:
1021                                 block_size_log2 = 8;
1022                                 break;
1023                         case DC_SW_4KB_S:
1024                         case DC_SW_4KB_S_X:
1025                                 block_size_log2 = 12;
1026                                 break;
1027                         case DC_SW_64KB_S:
1028                         case DC_SW_64KB_S_T:
1029                         case DC_SW_64KB_S_X:
1030                                 block_size_log2 = 16;
1031                                 break;
1032                         case DC_SW_VAR_S_X:
1033                                 block_size_log2 = 18;
1034                                 break;
1035                         default:
1036                                 drm_dbg_kms(rfb->base.dev,
1037                                             "Swizzle mode with unknown block size: %d\n", swizzle);
1038                                 return -EINVAL;
1039                         }
1040
1041                         get_block_dimensions(block_size_log2, format_info->cpp[i],
1042                                              &block_width, &block_height);
1043                 }
1044
1045                 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1046                                                   block_width, block_height, block_size_log2);
1047                 if (ret)
1048                         return ret;
1049         }
1050
1051         if (AMD_FMT_MOD_GET(DCC, modifier)) {
1052                 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
1053                         block_size_log2 = get_dcc_block_size(modifier, false, false);
1054                         get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1055                                              &block_width, &block_height);
1056                         ret = amdgpu_display_verify_plane(rfb, i, format_info,
1057                                                           block_width, block_height,
1058                                                           block_size_log2);
1059                         if (ret)
1060                                 return ret;
1061
1062                         ++i;
1063                         block_size_log2 = get_dcc_block_size(modifier, true, true);
1064                 } else {
1065                         bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
1066
1067                         block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);
1068                 }
1069                 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
1070                                      &block_width, &block_height);
1071                 ret = amdgpu_display_verify_plane(rfb, i, format_info,
1072                                                   block_width, block_height, block_size_log2);
1073                 if (ret)
1074                         return ret;
1075         }
1076
1077         return 0;
1078 }
1079
1080 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1081                                       uint64_t *tiling_flags, bool *tmz_surface)
1082 {
1083         struct amdgpu_bo *rbo;
1084         int r;
1085
1086         if (!amdgpu_fb) {
1087                 *tiling_flags = 0;
1088                 *tmz_surface = false;
1089                 return 0;
1090         }
1091
1092         rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1093         r = amdgpu_bo_reserve(rbo, false);
1094
1095         if (unlikely(r)) {
1096                 /* Don't show error message when returning -ERESTARTSYS */
1097                 if (r != -ERESTARTSYS)
1098                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
1099                 return r;
1100         }
1101
1102         if (tiling_flags)
1103                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1104
1105         if (tmz_surface)
1106                 *tmz_surface = amdgpu_bo_encrypted(rbo);
1107
1108         amdgpu_bo_unreserve(rbo);
1109
1110         return r;
1111 }
1112
1113 static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,
1114                                                  struct amdgpu_framebuffer *rfb,
1115                                                  struct drm_file *file_priv,
1116                                                  const struct drm_mode_fb_cmd2 *mode_cmd,
1117                                                  struct drm_gem_object *obj)
1118 {
1119         int ret;
1120
1121         rfb->base.obj[0] = obj;
1122         drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1123         /* Verify that the modifier is supported. */
1124         if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
1125                                       mode_cmd->modifier[0])) {
1126                 drm_dbg_kms(dev,
1127                             "unsupported pixel format %p4cc / modifier 0x%llx\n",
1128                             &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1129
1130                 ret = -EINVAL;
1131                 goto err;
1132         }
1133
1134         ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1135         if (ret)
1136                 goto err;
1137
1138         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1139
1140         if (ret)
1141                 goto err;
1142
1143         return 0;
1144 err:
1145         drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
1146         rfb->base.obj[0] = NULL;
1147         return ret;
1148 }
1149
1150 static int amdgpu_display_framebuffer_init(struct drm_device *dev,
1151                                            struct amdgpu_framebuffer *rfb,
1152                                            const struct drm_mode_fb_cmd2 *mode_cmd,
1153                                            struct drm_gem_object *obj)
1154 {
1155         struct amdgpu_device *adev = drm_to_adev(dev);
1156         int ret, i;
1157
1158         /*
1159          * This needs to happen before modifier conversion as that might change
1160          * the number of planes.
1161          */
1162         for (i = 1; i < rfb->base.format->num_planes; ++i) {
1163                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1164                         drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
1165                                     i, mode_cmd->handles[0], mode_cmd->handles[i]);
1166                         ret = -EINVAL;
1167                         return ret;
1168                 }
1169         }
1170
1171         ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
1172         if (ret)
1173                 return ret;
1174
1175         if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) {
1176                 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
1177                               "GFX9+ requires FB check based on format modifier\n");
1178                 ret = check_tiling_flags_gfx6(rfb);
1179                 if (ret)
1180                         return ret;
1181         }
1182
1183         if (!dev->mode_config.fb_modifiers_not_supported &&
1184             !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
1185                 ret = convert_tiling_flags_to_modifier(rfb);
1186                 if (ret) {
1187                         drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
1188                                     rfb->tiling_flags);
1189                         return ret;
1190                 }
1191         }
1192
1193         ret = amdgpu_display_verify_sizes(rfb);
1194         if (ret)
1195                 return ret;
1196
1197         for (i = 0; i < rfb->base.format->num_planes; ++i) {
1198                 drm_gem_object_get(rfb->base.obj[0]);
1199                 rfb->base.obj[i] = rfb->base.obj[0];
1200         }
1201
1202         return 0;
1203 }
1204
1205 struct drm_framebuffer *
1206 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
1207                                        struct drm_file *file_priv,
1208                                        const struct drm_mode_fb_cmd2 *mode_cmd)
1209 {
1210         struct amdgpu_framebuffer *amdgpu_fb;
1211         struct drm_gem_object *obj;
1212         struct amdgpu_bo *bo;
1213         uint32_t domains;
1214         int ret;
1215
1216         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1217         if (obj ==  NULL) {
1218                 drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, "
1219                             "can't create framebuffer\n", mode_cmd->handles[0]);
1220                 return ERR_PTR(-ENOENT);
1221         }
1222
1223         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1224         bo = gem_to_amdgpu_bo(obj);
1225         domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
1226         if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
1227                 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
1228                 drm_gem_object_put(obj);
1229                 return ERR_PTR(-EINVAL);
1230         }
1231
1232         amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
1233         if (amdgpu_fb == NULL) {
1234                 drm_gem_object_put(obj);
1235                 return ERR_PTR(-ENOMEM);
1236         }
1237
1238         ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,
1239                                                     mode_cmd, obj);
1240         if (ret) {
1241                 kfree(amdgpu_fb);
1242                 drm_gem_object_put(obj);
1243                 return ERR_PTR(ret);
1244         }
1245
1246         drm_gem_object_put(obj);
1247         return &amdgpu_fb->base;
1248 }
1249
1250 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
1251         .fb_create = amdgpu_display_user_framebuffer_create,
1252         .output_poll_changed = drm_fb_helper_output_poll_changed,
1253 };
1254
1255 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
1256 {       { UNDERSCAN_OFF, "off" },
1257         { UNDERSCAN_ON, "on" },
1258         { UNDERSCAN_AUTO, "auto" },
1259 };
1260
1261 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
1262 {       { AMDGPU_AUDIO_DISABLE, "off" },
1263         { AMDGPU_AUDIO_ENABLE, "on" },
1264         { AMDGPU_AUDIO_AUTO, "auto" },
1265 };
1266
1267 /* XXX support different dither options? spatial, temporal, both, etc. */
1268 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
1269 {       { AMDGPU_FMT_DITHER_DISABLE, "off" },
1270         { AMDGPU_FMT_DITHER_ENABLE, "on" },
1271 };
1272
1273 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
1274 {
1275         int sz;
1276
1277         adev->mode_info.coherent_mode_property =
1278                 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
1279         if (!adev->mode_info.coherent_mode_property)
1280                 return -ENOMEM;
1281
1282         adev->mode_info.load_detect_property =
1283                 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
1284         if (!adev->mode_info.load_detect_property)
1285                 return -ENOMEM;
1286
1287         drm_mode_create_scaling_mode_property(adev_to_drm(adev));
1288
1289         sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
1290         adev->mode_info.underscan_property =
1291                 drm_property_create_enum(adev_to_drm(adev), 0,
1292                                          "underscan",
1293                                          amdgpu_underscan_enum_list, sz);
1294
1295         adev->mode_info.underscan_hborder_property =
1296                 drm_property_create_range(adev_to_drm(adev), 0,
1297                                           "underscan hborder", 0, 128);
1298         if (!adev->mode_info.underscan_hborder_property)
1299                 return -ENOMEM;
1300
1301         adev->mode_info.underscan_vborder_property =
1302                 drm_property_create_range(adev_to_drm(adev), 0,
1303                                           "underscan vborder", 0, 128);
1304         if (!adev->mode_info.underscan_vborder_property)
1305                 return -ENOMEM;
1306
1307         sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1308         adev->mode_info.audio_property =
1309                 drm_property_create_enum(adev_to_drm(adev), 0,
1310                                          "audio",
1311                                          amdgpu_audio_enum_list, sz);
1312
1313         sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1314         adev->mode_info.dither_property =
1315                 drm_property_create_enum(adev_to_drm(adev), 0,
1316                                          "dither",
1317                                          amdgpu_dither_enum_list, sz);
1318
1319         if (adev->dc_enabled) {
1320                 adev->mode_info.abm_level_property =
1321                         drm_property_create_range(adev_to_drm(adev), 0,
1322                                                   "abm level", 0, 4);
1323                 if (!adev->mode_info.abm_level_property)
1324                         return -ENOMEM;
1325         }
1326
1327         return 0;
1328 }
1329
1330 void amdgpu_display_update_priority(struct amdgpu_device *adev)
1331 {
1332         /* adjustment options for the display watermarks */
1333         if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1334                 adev->mode_info.disp_priority = 0;
1335         else
1336                 adev->mode_info.disp_priority = amdgpu_disp_priority;
1337
1338 }
1339
1340 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1341 {
1342         /* try and guess if this is a tv or a monitor */
1343         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1344             (mode->vdisplay == 576) || /* 576p */
1345             (mode->vdisplay == 720) || /* 720p */
1346             (mode->vdisplay == 1080)) /* 1080p */
1347                 return true;
1348         else
1349                 return false;
1350 }
1351
1352 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1353                                         const struct drm_display_mode *mode,
1354                                         struct drm_display_mode *adjusted_mode)
1355 {
1356         struct drm_device *dev = crtc->dev;
1357         struct drm_encoder *encoder;
1358         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1359         struct amdgpu_encoder *amdgpu_encoder;
1360         struct drm_connector *connector;
1361         u32 src_v = 1, dst_v = 1;
1362         u32 src_h = 1, dst_h = 1;
1363
1364         amdgpu_crtc->h_border = 0;
1365         amdgpu_crtc->v_border = 0;
1366
1367         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1368                 if (encoder->crtc != crtc)
1369                         continue;
1370                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1371                 connector = amdgpu_get_connector_for_encoder(encoder);
1372
1373                 /* set scaling */
1374                 if (amdgpu_encoder->rmx_type == RMX_OFF)
1375                         amdgpu_crtc->rmx_type = RMX_OFF;
1376                 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1377                          mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1378                         amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1379                 else
1380                         amdgpu_crtc->rmx_type = RMX_OFF;
1381                 /* copy native mode */
1382                 memcpy(&amdgpu_crtc->native_mode,
1383                        &amdgpu_encoder->native_mode,
1384                        sizeof(struct drm_display_mode));
1385                 src_v = crtc->mode.vdisplay;
1386                 dst_v = amdgpu_crtc->native_mode.vdisplay;
1387                 src_h = crtc->mode.hdisplay;
1388                 dst_h = amdgpu_crtc->native_mode.hdisplay;
1389
1390                 /* fix up for overscan on hdmi */
1391                 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1392                     ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1393                      ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
1394                       connector->display_info.is_hdmi &&
1395                       amdgpu_display_is_hdtv_mode(mode)))) {
1396                         if (amdgpu_encoder->underscan_hborder != 0)
1397                                 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1398                         else
1399                                 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1400                         if (amdgpu_encoder->underscan_vborder != 0)
1401                                 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1402                         else
1403                                 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1404                         amdgpu_crtc->rmx_type = RMX_FULL;
1405                         src_v = crtc->mode.vdisplay;
1406                         dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1407                         src_h = crtc->mode.hdisplay;
1408                         dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1409                 }
1410         }
1411         if (amdgpu_crtc->rmx_type != RMX_OFF) {
1412                 fixed20_12 a, b;
1413                 a.full = dfixed_const(src_v);
1414                 b.full = dfixed_const(dst_v);
1415                 amdgpu_crtc->vsc.full = dfixed_div(a, b);
1416                 a.full = dfixed_const(src_h);
1417                 b.full = dfixed_const(dst_h);
1418                 amdgpu_crtc->hsc.full = dfixed_div(a, b);
1419         } else {
1420                 amdgpu_crtc->vsc.full = dfixed_const(1);
1421                 amdgpu_crtc->hsc.full = dfixed_const(1);
1422         }
1423         return true;
1424 }
1425
1426 /*
1427  * Retrieve current video scanout position of crtc on a given gpu, and
1428  * an optional accurate timestamp of when query happened.
1429  *
1430  * \param dev Device to query.
1431  * \param pipe Crtc to query.
1432  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1433  *              For driver internal use only also supports these flags:
1434  *
1435  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1436  *              of a fudged earlier start of vblank.
1437  *
1438  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1439  *              fudged earlier start of vblank in *vpos and the distance
1440  *              to true start of vblank in *hpos.
1441  *
1442  * \param *vpos Location where vertical scanout position should be stored.
1443  * \param *hpos Location where horizontal scanout position should go.
1444  * \param *stime Target location for timestamp taken immediately before
1445  *               scanout position query. Can be NULL to skip timestamp.
1446  * \param *etime Target location for timestamp taken immediately after
1447  *               scanout position query. Can be NULL to skip timestamp.
1448  *
1449  * Returns vpos as a positive number while in active scanout area.
1450  * Returns vpos as a negative number inside vblank, counting the number
1451  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1452  * until start of active scanout / end of vblank."
1453  *
1454  * \return Flags, or'ed together as follows:
1455  *
1456  * DRM_SCANOUTPOS_VALID = Query successful.
1457  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1458  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1459  * this flag means that returned position may be offset by a constant but
1460  * unknown small number of scanlines wrt. real scanout position.
1461  *
1462  */
1463 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1464                         unsigned int pipe, unsigned int flags, int *vpos,
1465                         int *hpos, ktime_t *stime, ktime_t *etime,
1466                         const struct drm_display_mode *mode)
1467 {
1468         u32 vbl = 0, position = 0;
1469         int vbl_start, vbl_end, vtotal, ret = 0;
1470         bool in_vbl = true;
1471
1472         struct amdgpu_device *adev = drm_to_adev(dev);
1473
1474         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1475
1476         /* Get optional system timestamp before query. */
1477         if (stime)
1478                 *stime = ktime_get();
1479
1480         if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1481                 ret |= DRM_SCANOUTPOS_VALID;
1482
1483         /* Get optional system timestamp after query. */
1484         if (etime)
1485                 *etime = ktime_get();
1486
1487         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1488
1489         /* Decode into vertical and horizontal scanout position. */
1490         *vpos = position & 0x1fff;
1491         *hpos = (position >> 16) & 0x1fff;
1492
1493         /* Valid vblank area boundaries from gpu retrieved? */
1494         if (vbl > 0) {
1495                 /* Yes: Decode. */
1496                 ret |= DRM_SCANOUTPOS_ACCURATE;
1497                 vbl_start = vbl & 0x1fff;
1498                 vbl_end = (vbl >> 16) & 0x1fff;
1499         }
1500         else {
1501                 /* No: Fake something reasonable which gives at least ok results. */
1502                 vbl_start = mode->crtc_vdisplay;
1503                 vbl_end = 0;
1504         }
1505
1506         /* Called from driver internal vblank counter query code? */
1507         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1508             /* Caller wants distance from real vbl_start in *hpos */
1509             *hpos = *vpos - vbl_start;
1510         }
1511
1512         /* Fudge vblank to start a few scanlines earlier to handle the
1513          * problem that vblank irqs fire a few scanlines before start
1514          * of vblank. Some driver internal callers need the true vblank
1515          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1516          *
1517          * The cause of the "early" vblank irq is that the irq is triggered
1518          * by the line buffer logic when the line buffer read position enters
1519          * the vblank, whereas our crtc scanout position naturally lags the
1520          * line buffer read position.
1521          */
1522         if (!(flags & USE_REAL_VBLANKSTART))
1523                 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1524
1525         /* Test scanout position against vblank region. */
1526         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1527                 in_vbl = false;
1528
1529         /* In vblank? */
1530         if (in_vbl)
1531             ret |= DRM_SCANOUTPOS_IN_VBLANK;
1532
1533         /* Called from driver internal vblank counter query code? */
1534         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1535                 /* Caller wants distance from fudged earlier vbl_start */
1536                 *vpos -= vbl_start;
1537                 return ret;
1538         }
1539
1540         /* Check if inside vblank area and apply corrective offsets:
1541          * vpos will then be >=0 in video scanout area, but negative
1542          * within vblank area, counting down the number of lines until
1543          * start of scanout.
1544          */
1545
1546         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1547         if (in_vbl && (*vpos >= vbl_start)) {
1548                 vtotal = mode->crtc_vtotal;
1549
1550                 /* With variable refresh rate displays the vpos can exceed
1551                  * the vtotal value. Clamp to 0 to return -vbl_end instead
1552                  * of guessing the remaining number of lines until scanout.
1553                  */
1554                 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1555         }
1556
1557         /* Correct for shifted end of vbl at vbl_end. */
1558         *vpos = *vpos - vbl_end;
1559
1560         return ret;
1561 }
1562
1563 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1564 {
1565         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1566                 return AMDGPU_CRTC_IRQ_NONE;
1567
1568         switch (crtc) {
1569         case 0:
1570                 return AMDGPU_CRTC_IRQ_VBLANK1;
1571         case 1:
1572                 return AMDGPU_CRTC_IRQ_VBLANK2;
1573         case 2:
1574                 return AMDGPU_CRTC_IRQ_VBLANK3;
1575         case 3:
1576                 return AMDGPU_CRTC_IRQ_VBLANK4;
1577         case 4:
1578                 return AMDGPU_CRTC_IRQ_VBLANK5;
1579         case 5:
1580                 return AMDGPU_CRTC_IRQ_VBLANK6;
1581         default:
1582                 return AMDGPU_CRTC_IRQ_NONE;
1583         }
1584 }
1585
1586 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1587                         bool in_vblank_irq, int *vpos,
1588                         int *hpos, ktime_t *stime, ktime_t *etime,
1589                         const struct drm_display_mode *mode)
1590 {
1591         struct drm_device *dev = crtc->dev;
1592         unsigned int pipe = crtc->index;
1593
1594         return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1595                                                   stime, etime, mode);
1596 }
1597
1598 static bool
1599 amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
1600 {
1601         struct drm_device *dev = adev_to_drm(adev);
1602         struct drm_fb_helper *fb_helper = dev->fb_helper;
1603
1604         if (!fb_helper || !fb_helper->buffer)
1605                 return false;
1606
1607         if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj)
1608                 return false;
1609
1610         return true;
1611 }
1612
1613 int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
1614 {
1615         struct drm_device *dev = adev_to_drm(adev);
1616         struct drm_crtc *crtc;
1617         struct drm_connector *connector;
1618         struct drm_connector_list_iter iter;
1619         int r;
1620
1621         /* turn off display hw */
1622         drm_modeset_lock_all(dev);
1623         drm_connector_list_iter_begin(dev, &iter);
1624         drm_for_each_connector_iter(connector, &iter)
1625                 drm_helper_connector_dpms(connector,
1626                                           DRM_MODE_DPMS_OFF);
1627         drm_connector_list_iter_end(&iter);
1628         drm_modeset_unlock_all(dev);
1629         /* unpin the front buffers and cursors */
1630         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1631                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1632                 struct drm_framebuffer *fb = crtc->primary->fb;
1633                 struct amdgpu_bo *robj;
1634
1635                 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1636                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1637                         r = amdgpu_bo_reserve(aobj, true);
1638                         if (r == 0) {
1639                                 amdgpu_bo_unpin(aobj);
1640                                 amdgpu_bo_unreserve(aobj);
1641                         }
1642                 }
1643
1644                 if (fb == NULL || fb->obj[0] == NULL) {
1645                         continue;
1646                 }
1647                 robj = gem_to_amdgpu_bo(fb->obj[0]);
1648                 if (!amdgpu_display_robj_is_fb(adev, robj)) {
1649                         r = amdgpu_bo_reserve(robj, true);
1650                         if (r == 0) {
1651                                 amdgpu_bo_unpin(robj);
1652                                 amdgpu_bo_unreserve(robj);
1653                         }
1654                 }
1655         }
1656         return 0;
1657 }
1658
1659 int amdgpu_display_resume_helper(struct amdgpu_device *adev)
1660 {
1661         struct drm_device *dev = adev_to_drm(adev);
1662         struct drm_connector *connector;
1663         struct drm_connector_list_iter iter;
1664         struct drm_crtc *crtc;
1665         int r;
1666
1667         /* pin cursors */
1668         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1669                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1670
1671                 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1672                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1673                         r = amdgpu_bo_reserve(aobj, true);
1674                         if (r == 0) {
1675                                 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
1676                                 if (r != 0)
1677                                         dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
1678                                 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
1679                                 amdgpu_bo_unreserve(aobj);
1680                         }
1681                 }
1682         }
1683
1684         drm_helper_resume_force_mode(dev);
1685
1686         /* turn on display hw */
1687         drm_modeset_lock_all(dev);
1688
1689         drm_connector_list_iter_begin(dev, &iter);
1690         drm_for_each_connector_iter(connector, &iter)
1691                 drm_helper_connector_dpms(connector,
1692                                           DRM_MODE_DPMS_ON);
1693         drm_connector_list_iter_end(&iter);
1694
1695         drm_modeset_unlock_all(dev);
1696
1697         return 0;
1698 }
1699