2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
42 #include "amdgpu_atombios.h"
43 #include "amdgpu_atomfirmware.h"
45 #ifdef CONFIG_DRM_AMDGPU_SI
48 #ifdef CONFIG_DRM_AMDGPU_CIK
53 #include "bif/bif_4_1_d.h"
54 #include <linux/pci.h>
55 #include <linux/firmware.h>
57 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
58 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
60 #define AMDGPU_RESUME_MS 2000
62 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
63 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
65 static const char *amdgpu_asic_name[] = {
89 bool amdgpu_device_is_px(struct drm_device *dev)
91 struct amdgpu_device *adev = dev->dev_private;
93 if (adev->flags & AMD_IS_PX)
99 * MMIO register access helper functions.
101 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
106 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
107 BUG_ON(in_interrupt());
108 return amdgpu_virt_kiq_rreg(adev, reg);
111 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
112 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
116 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
117 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
118 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
119 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
121 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
125 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
128 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
130 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) {
131 BUG_ON(in_interrupt());
132 return amdgpu_virt_kiq_wreg(adev, reg, v);
135 if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
136 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
140 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
141 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
142 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
143 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
147 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
149 if ((reg * 4) < adev->rio_mem_size)
150 return ioread32(adev->rio_mem + (reg * 4));
152 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
153 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
157 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
160 if ((reg * 4) < adev->rio_mem_size)
161 iowrite32(v, adev->rio_mem + (reg * 4));
163 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
164 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
169 * amdgpu_mm_rdoorbell - read a doorbell dword
171 * @adev: amdgpu_device pointer
172 * @index: doorbell index
174 * Returns the value in the doorbell aperture at the
175 * requested doorbell index (CIK).
177 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
179 if (index < adev->doorbell.num_doorbells) {
180 return readl(adev->doorbell.ptr + index);
182 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
188 * amdgpu_mm_wdoorbell - write a doorbell dword
190 * @adev: amdgpu_device pointer
191 * @index: doorbell index
194 * Writes @v to the doorbell aperture at the
195 * requested doorbell index (CIK).
197 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
199 if (index < adev->doorbell.num_doorbells) {
200 writel(v, adev->doorbell.ptr + index);
202 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
207 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
209 * @adev: amdgpu_device pointer
210 * @index: doorbell index
212 * Returns the value in the doorbell aperture at the
213 * requested doorbell index (VEGA10+).
215 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
217 if (index < adev->doorbell.num_doorbells) {
218 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
220 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
226 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
228 * @adev: amdgpu_device pointer
229 * @index: doorbell index
232 * Writes @v to the doorbell aperture at the
233 * requested doorbell index (VEGA10+).
235 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
237 if (index < adev->doorbell.num_doorbells) {
238 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
240 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
245 * amdgpu_invalid_rreg - dummy reg read function
247 * @adev: amdgpu device pointer
248 * @reg: offset of register
250 * Dummy register read function. Used for register blocks
251 * that certain asics don't have (all asics).
252 * Returns the value in the register.
254 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
256 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
262 * amdgpu_invalid_wreg - dummy reg write function
264 * @adev: amdgpu device pointer
265 * @reg: offset of register
266 * @v: value to write to the register
268 * Dummy register read function. Used for register blocks
269 * that certain asics don't have (all asics).
271 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
273 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
279 * amdgpu_block_invalid_rreg - dummy reg read function
281 * @adev: amdgpu device pointer
282 * @block: offset of instance
283 * @reg: offset of register
285 * Dummy register read function. Used for register blocks
286 * that certain asics don't have (all asics).
287 * Returns the value in the register.
289 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
290 uint32_t block, uint32_t reg)
292 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
299 * amdgpu_block_invalid_wreg - dummy reg write function
301 * @adev: amdgpu device pointer
302 * @block: offset of instance
303 * @reg: offset of register
304 * @v: value to write to the register
306 * Dummy register read function. Used for register blocks
307 * that certain asics don't have (all asics).
309 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
311 uint32_t reg, uint32_t v)
313 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
318 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
322 if (adev->vram_scratch.robj == NULL) {
323 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
324 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
325 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
326 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
327 NULL, NULL, &adev->vram_scratch.robj);
333 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
334 if (unlikely(r != 0))
336 r = amdgpu_bo_pin(adev->vram_scratch.robj,
337 AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
339 amdgpu_bo_unreserve(adev->vram_scratch.robj);
342 r = amdgpu_bo_kmap(adev->vram_scratch.robj,
343 (void **)&adev->vram_scratch.ptr);
345 amdgpu_bo_unpin(adev->vram_scratch.robj);
346 amdgpu_bo_unreserve(adev->vram_scratch.robj);
351 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
355 if (adev->vram_scratch.robj == NULL) {
358 r = amdgpu_bo_reserve(adev->vram_scratch.robj, true);
359 if (likely(r == 0)) {
360 amdgpu_bo_kunmap(adev->vram_scratch.robj);
361 amdgpu_bo_unpin(adev->vram_scratch.robj);
362 amdgpu_bo_unreserve(adev->vram_scratch.robj);
364 amdgpu_bo_unref(&adev->vram_scratch.robj);
368 * amdgpu_program_register_sequence - program an array of registers.
370 * @adev: amdgpu_device pointer
371 * @registers: pointer to the register array
372 * @array_size: size of the register array
374 * Programs an array or registers with and and or masks.
375 * This is a helper for setting golden registers.
377 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
378 const u32 *registers,
379 const u32 array_size)
381 u32 tmp, reg, and_mask, or_mask;
387 for (i = 0; i < array_size; i +=3) {
388 reg = registers[i + 0];
389 and_mask = registers[i + 1];
390 or_mask = registers[i + 2];
392 if (and_mask == 0xffffffff) {
403 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
405 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
409 * GPU doorbell aperture helpers function.
412 * amdgpu_doorbell_init - Init doorbell driver information.
414 * @adev: amdgpu_device pointer
416 * Init doorbell driver information (CIK)
417 * Returns 0 on success, error on failure.
419 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
421 /* doorbell bar mapping */
422 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
423 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
425 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
426 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
427 if (adev->doorbell.num_doorbells == 0)
430 adev->doorbell.ptr = ioremap(adev->doorbell.base,
431 adev->doorbell.num_doorbells *
433 if (adev->doorbell.ptr == NULL)
440 * amdgpu_doorbell_fini - Tear down doorbell driver information.
442 * @adev: amdgpu_device pointer
444 * Tear down doorbell driver information (CIK)
446 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
448 iounmap(adev->doorbell.ptr);
449 adev->doorbell.ptr = NULL;
453 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
456 * @adev: amdgpu_device pointer
457 * @aperture_base: output returning doorbell aperture base physical address
458 * @aperture_size: output returning doorbell aperture size in bytes
459 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
461 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
462 * takes doorbells required for its own rings and reports the setup to amdkfd.
463 * amdgpu reserved doorbells are at the start of the doorbell aperture.
465 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
466 phys_addr_t *aperture_base,
467 size_t *aperture_size,
468 size_t *start_offset)
471 * The first num_doorbells are used by amdgpu.
472 * amdkfd takes whatever's left in the aperture.
474 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
475 *aperture_base = adev->doorbell.base;
476 *aperture_size = adev->doorbell.size;
477 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
487 * Writeback is the method by which the GPU updates special pages in memory
488 * with the status of certain GPU events (fences, ring pointers,etc.).
492 * amdgpu_wb_fini - Disable Writeback and free memory
494 * @adev: amdgpu_device pointer
496 * Disables Writeback and frees the Writeback memory (all asics).
497 * Used at driver shutdown.
499 static void amdgpu_wb_fini(struct amdgpu_device *adev)
501 if (adev->wb.wb_obj) {
502 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
504 (void **)&adev->wb.wb);
505 adev->wb.wb_obj = NULL;
510 * amdgpu_wb_init- Init Writeback driver info and allocate memory
512 * @adev: amdgpu_device pointer
514 * Initializes writeback and allocates writeback memory (all asics).
515 * Used at driver startup.
516 * Returns 0 on success or an -error on failure.
518 static int amdgpu_wb_init(struct amdgpu_device *adev)
522 if (adev->wb.wb_obj == NULL) {
523 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t),
524 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
525 &adev->wb.wb_obj, &adev->wb.gpu_addr,
526 (void **)&adev->wb.wb);
528 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
532 adev->wb.num_wb = AMDGPU_MAX_WB;
533 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
535 /* clear wb memory */
536 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
543 * amdgpu_wb_get - Allocate a wb entry
545 * @adev: amdgpu_device pointer
548 * Allocate a wb slot for use by the driver (all asics).
549 * Returns 0 on success or -EINVAL on failure.
551 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
553 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
554 if (offset < adev->wb.num_wb) {
555 __set_bit(offset, adev->wb.used);
564 * amdgpu_wb_get_64bit - Allocate a wb entry
566 * @adev: amdgpu_device pointer
569 * Allocate a wb slot for use by the driver (all asics).
570 * Returns 0 on success or -EINVAL on failure.
572 int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb)
574 unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used,
575 adev->wb.num_wb, 0, 2, 7, 0);
576 if ((offset + 1) < adev->wb.num_wb) {
577 __set_bit(offset, adev->wb.used);
578 __set_bit(offset + 1, adev->wb.used);
587 * amdgpu_wb_free - Free a wb entry
589 * @adev: amdgpu_device pointer
592 * Free a wb slot allocated for use by the driver (all asics)
594 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
596 if (wb < adev->wb.num_wb)
597 __clear_bit(wb, adev->wb.used);
601 * amdgpu_wb_free_64bit - Free a wb entry
603 * @adev: amdgpu_device pointer
606 * Free a wb slot allocated for use by the driver (all asics)
608 void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb)
610 if ((wb + 1) < adev->wb.num_wb) {
611 __clear_bit(wb, adev->wb.used);
612 __clear_bit(wb + 1, adev->wb.used);
617 * amdgpu_vram_location - try to find VRAM location
618 * @adev: amdgpu device structure holding all necessary informations
619 * @mc: memory controller structure holding memory informations
620 * @base: base address at which to put VRAM
622 * Function will try to place VRAM at base address provided
623 * as parameter (which is so far either PCI aperture address or
624 * for IGP TOM base address).
626 * If there is not enough space to fit the unvisible VRAM in the 32bits
627 * address space then we limit the VRAM size to the aperture.
629 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
630 * this shouldn't be a problem as we are using the PCI aperture as a reference.
631 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
634 * Note: we use mc_vram_size as on some board we need to program the mc to
635 * cover the whole aperture even if VRAM size is inferior to aperture size
636 * Novell bug 204882 + along with lots of ubuntu ones
638 * Note: when limiting vram it's safe to overwritte real_vram_size because
639 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
640 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
643 * Note: IGP TOM addr should be the same as the aperture addr, we don't
644 * explicitly check for that though.
646 * FIXME: when reducing VRAM size align new size on power of 2.
648 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
650 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
652 mc->vram_start = base;
653 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
654 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
655 mc->real_vram_size = mc->aper_size;
656 mc->mc_vram_size = mc->aper_size;
658 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
659 if (limit && limit < mc->real_vram_size)
660 mc->real_vram_size = limit;
661 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
662 mc->mc_vram_size >> 20, mc->vram_start,
663 mc->vram_end, mc->real_vram_size >> 20);
667 * amdgpu_gtt_location - try to find GTT location
668 * @adev: amdgpu device structure holding all necessary informations
669 * @mc: memory controller structure holding memory informations
671 * Function will place try to place GTT before or after VRAM.
673 * If GTT size is bigger than space left then we ajust GTT size.
674 * Thus function will never fails.
676 * FIXME: when reducing GTT size align new size on power of 2.
678 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
680 u64 size_af, size_bf;
682 size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
683 size_bf = mc->vram_start & ~mc->gtt_base_align;
684 if (size_bf > size_af) {
685 if (mc->gtt_size > size_bf) {
686 dev_warn(adev->dev, "limiting GTT\n");
687 mc->gtt_size = size_bf;
691 if (mc->gtt_size > size_af) {
692 dev_warn(adev->dev, "limiting GTT\n");
693 mc->gtt_size = size_af;
695 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
697 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
698 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
699 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
703 * GPU helpers function.
706 * amdgpu_need_post - check if the hw need post or not
708 * @adev: amdgpu_device pointer
710 * Check if the asic has been initialized (all asics) at driver startup
711 * or post is needed if hw reset is performed.
712 * Returns true if need or false if not.
714 bool amdgpu_need_post(struct amdgpu_device *adev)
718 if (adev->has_hw_reset) {
719 adev->has_hw_reset = false;
722 /* then check MEM_SIZE, in case the crtcs are off */
723 reg = amdgpu_asic_get_config_memsize(adev);
725 if ((reg != 0) && (reg != 0xffffffff))
732 static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
734 if (amdgpu_sriov_vf(adev))
737 if (amdgpu_passthrough(adev)) {
738 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
739 * some old smc fw still need driver do vPost otherwise gpu hang, while
740 * those smc fw version above 22.15 doesn't have this flaw, so we force
741 * vpost executed for smc version below 22.15
743 if (adev->asic_type == CHIP_FIJI) {
746 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
747 /* force vPost if error occured */
751 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
752 if (fw_ver < 0x00160e00)
756 return amdgpu_need_post(adev);
760 * amdgpu_dummy_page_init - init dummy page used by the driver
762 * @adev: amdgpu_device pointer
764 * Allocate the dummy page used by the driver (all asics).
765 * This dummy page is used by the driver as a filler for gart entries
766 * when pages are taken out of the GART
767 * Returns 0 on sucess, -ENOMEM on failure.
769 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
771 if (adev->dummy_page.page)
773 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
774 if (adev->dummy_page.page == NULL)
776 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
777 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
778 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
779 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
780 __free_page(adev->dummy_page.page);
781 adev->dummy_page.page = NULL;
788 * amdgpu_dummy_page_fini - free dummy page used by the driver
790 * @adev: amdgpu_device pointer
792 * Frees the dummy page used by the driver (all asics).
794 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
796 if (adev->dummy_page.page == NULL)
798 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
799 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
800 __free_page(adev->dummy_page.page);
801 adev->dummy_page.page = NULL;
805 /* ATOM accessor methods */
807 * ATOM is an interpreted byte code stored in tables in the vbios. The
808 * driver registers callbacks to access registers and the interpreter
809 * in the driver parses the tables and executes then to program specific
810 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
811 * atombios.h, and atom.c
815 * cail_pll_read - read PLL register
817 * @info: atom card_info pointer
818 * @reg: PLL register offset
820 * Provides a PLL register accessor for the atom interpreter (r4xx+).
821 * Returns the value of the PLL register.
823 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
829 * cail_pll_write - write PLL register
831 * @info: atom card_info pointer
832 * @reg: PLL register offset
833 * @val: value to write to the pll register
835 * Provides a PLL register accessor for the atom interpreter (r4xx+).
837 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
843 * cail_mc_read - read MC (Memory Controller) register
845 * @info: atom card_info pointer
846 * @reg: MC register offset
848 * Provides an MC register accessor for the atom interpreter (r4xx+).
849 * Returns the value of the MC register.
851 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
857 * cail_mc_write - write MC (Memory Controller) register
859 * @info: atom card_info pointer
860 * @reg: MC register offset
861 * @val: value to write to the pll register
863 * Provides a MC register accessor for the atom interpreter (r4xx+).
865 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
871 * cail_reg_write - write MMIO register
873 * @info: atom card_info pointer
874 * @reg: MMIO register offset
875 * @val: value to write to the pll register
877 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
879 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
881 struct amdgpu_device *adev = info->dev->dev_private;
887 * cail_reg_read - read MMIO register
889 * @info: atom card_info pointer
890 * @reg: MMIO register offset
892 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
893 * Returns the value of the MMIO register.
895 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
897 struct amdgpu_device *adev = info->dev->dev_private;
905 * cail_ioreg_write - write IO register
907 * @info: atom card_info pointer
908 * @reg: IO register offset
909 * @val: value to write to the pll register
911 * Provides a IO register accessor for the atom interpreter (r4xx+).
913 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
915 struct amdgpu_device *adev = info->dev->dev_private;
921 * cail_ioreg_read - read IO register
923 * @info: atom card_info pointer
924 * @reg: IO register offset
926 * Provides an IO register accessor for the atom interpreter (r4xx+).
927 * Returns the value of the IO register.
929 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
931 struct amdgpu_device *adev = info->dev->dev_private;
939 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
941 * @adev: amdgpu_device pointer
943 * Frees the driver info and register access callbacks for the ATOM
944 * interpreter (r4xx+).
945 * Called at driver shutdown.
947 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
949 if (adev->mode_info.atom_context) {
950 kfree(adev->mode_info.atom_context->scratch);
951 kfree(adev->mode_info.atom_context->iio);
953 kfree(adev->mode_info.atom_context);
954 adev->mode_info.atom_context = NULL;
955 kfree(adev->mode_info.atom_card_info);
956 adev->mode_info.atom_card_info = NULL;
960 * amdgpu_atombios_init - init the driver info and callbacks for atombios
962 * @adev: amdgpu_device pointer
964 * Initializes the driver info and register access callbacks for the
965 * ATOM interpreter (r4xx+).
966 * Returns 0 on sucess, -ENOMEM on failure.
967 * Called at driver startup.
969 static int amdgpu_atombios_init(struct amdgpu_device *adev)
971 struct card_info *atom_card_info =
972 kzalloc(sizeof(struct card_info), GFP_KERNEL);
977 adev->mode_info.atom_card_info = atom_card_info;
978 atom_card_info->dev = adev->ddev;
979 atom_card_info->reg_read = cail_reg_read;
980 atom_card_info->reg_write = cail_reg_write;
981 /* needed for iio ops */
983 atom_card_info->ioreg_read = cail_ioreg_read;
984 atom_card_info->ioreg_write = cail_ioreg_write;
986 DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
987 atom_card_info->ioreg_read = cail_reg_read;
988 atom_card_info->ioreg_write = cail_reg_write;
990 atom_card_info->mc_read = cail_mc_read;
991 atom_card_info->mc_write = cail_mc_write;
992 atom_card_info->pll_read = cail_pll_read;
993 atom_card_info->pll_write = cail_pll_write;
995 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
996 if (!adev->mode_info.atom_context) {
997 amdgpu_atombios_fini(adev);
1001 mutex_init(&adev->mode_info.atom_context->mutex);
1002 if (adev->is_atom_fw) {
1003 amdgpu_atomfirmware_scratch_regs_init(adev);
1004 amdgpu_atomfirmware_allocate_fb_scratch(adev);
1006 amdgpu_atombios_scratch_regs_init(adev);
1007 amdgpu_atombios_allocate_fb_scratch(adev);
1012 /* if we get transitioned to only one device, take VGA back */
1014 * amdgpu_vga_set_decode - enable/disable vga decode
1016 * @cookie: amdgpu_device pointer
1017 * @state: enable/disable vga decode
1019 * Enable/disable vga decode (all asics).
1020 * Returns VGA resource flags.
1022 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
1024 struct amdgpu_device *adev = cookie;
1025 amdgpu_asic_set_vga_state(adev, state);
1027 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1028 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1030 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1034 * amdgpu_check_pot_argument - check that argument is a power of two
1036 * @arg: value to check
1038 * Validates that a certain argument is a power of two (all asics).
1039 * Returns true if argument is valid.
1041 static bool amdgpu_check_pot_argument(int arg)
1043 return (arg & (arg - 1)) == 0;
1046 static void amdgpu_check_block_size(struct amdgpu_device *adev)
1048 /* defines number of bits in page table versus page directory,
1049 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1050 * page table and the remaining bits are in the page directory */
1051 if (amdgpu_vm_block_size == -1)
1054 if (amdgpu_vm_block_size < 9) {
1055 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1056 amdgpu_vm_block_size);
1060 if (amdgpu_vm_block_size > 24 ||
1061 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1062 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1063 amdgpu_vm_block_size);
1070 amdgpu_vm_block_size = -1;
1073 static void amdgpu_check_vm_size(struct amdgpu_device *adev)
1075 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
1076 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1081 if (amdgpu_vm_size < 1) {
1082 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1088 * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
1090 if (amdgpu_vm_size > 1024) {
1091 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1099 amdgpu_vm_size = -1;
1103 * amdgpu_check_arguments - validate module params
1105 * @adev: amdgpu_device pointer
1107 * Validates certain module parameters and updates
1108 * the associated values used by the driver (all asics).
1110 static void amdgpu_check_arguments(struct amdgpu_device *adev)
1112 if (amdgpu_sched_jobs < 4) {
1113 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1115 amdgpu_sched_jobs = 4;
1116 } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
1117 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1119 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1122 if (amdgpu_gart_size != -1) {
1123 /* gtt size must be greater or equal to 32M */
1124 if (amdgpu_gart_size < 32) {
1125 dev_warn(adev->dev, "gart size (%d) too small\n",
1127 amdgpu_gart_size = -1;
1131 amdgpu_check_vm_size(adev);
1133 amdgpu_check_block_size(adev);
1135 if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1136 !amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
1137 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1138 amdgpu_vram_page_split);
1139 amdgpu_vram_page_split = 1024;
1144 * amdgpu_switcheroo_set_state - set switcheroo state
1146 * @pdev: pci dev pointer
1147 * @state: vga_switcheroo state
1149 * Callback for the switcheroo driver. Suspends or resumes the
1150 * the asics before or after it is powered up using ACPI methods.
1152 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1154 struct drm_device *dev = pci_get_drvdata(pdev);
1156 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1159 if (state == VGA_SWITCHEROO_ON) {
1160 unsigned d3_delay = dev->pdev->d3_delay;
1162 pr_info("amdgpu: switched on\n");
1163 /* don't suspend or resume card normally */
1164 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1166 amdgpu_device_resume(dev, true, true);
1168 dev->pdev->d3_delay = d3_delay;
1170 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1171 drm_kms_helper_poll_enable(dev);
1173 pr_info("amdgpu: switched off\n");
1174 drm_kms_helper_poll_disable(dev);
1175 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1176 amdgpu_device_suspend(dev, true, true);
1177 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1182 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1184 * @pdev: pci dev pointer
1186 * Callback for the switcheroo driver. Check of the switcheroo
1187 * state can be changed.
1188 * Returns true if the state can be changed, false if not.
1190 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1192 struct drm_device *dev = pci_get_drvdata(pdev);
1195 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1196 * locking inversion with the driver load path. And the access here is
1197 * completely racy anyway. So don't bother with locking for now.
1199 return dev->open_count == 0;
1202 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1203 .set_gpu_state = amdgpu_switcheroo_set_state,
1205 .can_switch = amdgpu_switcheroo_can_switch,
1208 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1209 enum amd_ip_block_type block_type,
1210 enum amd_clockgating_state state)
1214 for (i = 0; i < adev->num_ip_blocks; i++) {
1215 if (!adev->ip_blocks[i].status.valid)
1217 if (adev->ip_blocks[i].version->type != block_type)
1219 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1221 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1222 (void *)adev, state);
1224 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1225 adev->ip_blocks[i].version->funcs->name, r);
1230 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1231 enum amd_ip_block_type block_type,
1232 enum amd_powergating_state state)
1236 for (i = 0; i < adev->num_ip_blocks; i++) {
1237 if (!adev->ip_blocks[i].status.valid)
1239 if (adev->ip_blocks[i].version->type != block_type)
1241 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1243 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1244 (void *)adev, state);
1246 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1247 adev->ip_blocks[i].version->funcs->name, r);
1252 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
1256 for (i = 0; i < adev->num_ip_blocks; i++) {
1257 if (!adev->ip_blocks[i].status.valid)
1259 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1260 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1264 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1265 enum amd_ip_block_type block_type)
1269 for (i = 0; i < adev->num_ip_blocks; i++) {
1270 if (!adev->ip_blocks[i].status.valid)
1272 if (adev->ip_blocks[i].version->type == block_type) {
1273 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1283 bool amdgpu_is_idle(struct amdgpu_device *adev,
1284 enum amd_ip_block_type block_type)
1288 for (i = 0; i < adev->num_ip_blocks; i++) {
1289 if (!adev->ip_blocks[i].status.valid)
1291 if (adev->ip_blocks[i].version->type == block_type)
1292 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1298 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1299 enum amd_ip_block_type type)
1303 for (i = 0; i < adev->num_ip_blocks; i++)
1304 if (adev->ip_blocks[i].version->type == type)
1305 return &adev->ip_blocks[i];
1311 * amdgpu_ip_block_version_cmp
1313 * @adev: amdgpu_device pointer
1314 * @type: enum amd_ip_block_type
1315 * @major: major version
1316 * @minor: minor version
1318 * return 0 if equal or greater
1319 * return 1 if smaller or the ip_block doesn't exist
1321 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1322 enum amd_ip_block_type type,
1323 u32 major, u32 minor)
1325 struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
1327 if (ip_block && ((ip_block->version->major > major) ||
1328 ((ip_block->version->major == major) &&
1329 (ip_block->version->minor >= minor))))
1336 * amdgpu_ip_block_add
1338 * @adev: amdgpu_device pointer
1339 * @ip_block_version: pointer to the IP to add
1341 * Adds the IP block driver information to the collection of IPs
1344 int amdgpu_ip_block_add(struct amdgpu_device *adev,
1345 const struct amdgpu_ip_block_version *ip_block_version)
1347 if (!ip_block_version)
1350 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1355 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1357 adev->enable_virtual_display = false;
1359 if (amdgpu_virtual_display) {
1360 struct drm_device *ddev = adev->ddev;
1361 const char *pci_address_name = pci_name(ddev->pdev);
1362 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1364 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1365 pciaddstr_tmp = pciaddstr;
1366 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1367 pciaddname = strsep(&pciaddname_tmp, ",");
1368 if (!strcmp("all", pciaddname)
1369 || !strcmp(pci_address_name, pciaddname)) {
1373 adev->enable_virtual_display = true;
1376 res = kstrtol(pciaddname_tmp, 10,
1384 adev->mode_info.num_crtc = num_crtc;
1386 adev->mode_info.num_crtc = 1;
1392 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1393 amdgpu_virtual_display, pci_address_name,
1394 adev->enable_virtual_display, adev->mode_info.num_crtc);
1400 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1402 const struct firmware *fw;
1403 const char *chip_name;
1406 const struct gpu_info_firmware_header_v1_0 *hdr;
1408 switch (adev->asic_type) {
1412 case CHIP_POLARIS11:
1413 case CHIP_POLARIS10:
1414 case CHIP_POLARIS12:
1417 #ifdef CONFIG_DRM_AMDGPU_SI
1424 #ifdef CONFIG_DRM_AMDGPU_CIK
1434 chip_name = "vega10";
1437 chip_name = "raven";
1441 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1442 err = request_firmware(&fw, fw_name, adev->dev);
1445 "Failed to load gpu_info firmware \"%s\"\n",
1449 err = amdgpu_ucode_validate(fw);
1452 "Failed to validate gpu_info firmware \"%s\"\n",
1457 hdr = (const struct gpu_info_firmware_header_v1_0 *)fw->data;
1458 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1460 switch (hdr->version_major) {
1463 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1464 (const struct gpu_info_firmware_v1_0 *)(fw->data +
1465 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1467 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1468 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1469 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1470 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1471 adev->gfx.config.max_texture_channel_caches =
1472 le32_to_cpu(gpu_info_fw->gc_num_tccs);
1473 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1474 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1475 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1476 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1477 adev->gfx.config.double_offchip_lds_buf =
1478 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1479 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1484 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1489 release_firmware(fw);
1495 static int amdgpu_early_init(struct amdgpu_device *adev)
1499 amdgpu_device_enable_virtual_display(adev);
1501 switch (adev->asic_type) {
1505 case CHIP_POLARIS11:
1506 case CHIP_POLARIS10:
1507 case CHIP_POLARIS12:
1510 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1511 adev->family = AMDGPU_FAMILY_CZ;
1513 adev->family = AMDGPU_FAMILY_VI;
1515 r = vi_set_ip_blocks(adev);
1519 #ifdef CONFIG_DRM_AMDGPU_SI
1525 adev->family = AMDGPU_FAMILY_SI;
1526 r = si_set_ip_blocks(adev);
1531 #ifdef CONFIG_DRM_AMDGPU_CIK
1537 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1538 adev->family = AMDGPU_FAMILY_CI;
1540 adev->family = AMDGPU_FAMILY_KV;
1542 r = cik_set_ip_blocks(adev);
1549 if (adev->asic_type == CHIP_RAVEN)
1550 adev->family = AMDGPU_FAMILY_RV;
1552 adev->family = AMDGPU_FAMILY_AI;
1554 r = soc15_set_ip_blocks(adev);
1559 /* FIXME: not supported yet */
1563 r = amdgpu_device_parse_gpu_info_fw(adev);
1567 if (amdgpu_sriov_vf(adev)) {
1568 r = amdgpu_virt_request_full_gpu(adev, true);
1573 for (i = 0; i < adev->num_ip_blocks; i++) {
1574 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1575 DRM_ERROR("disabled ip block: %d\n", i);
1576 adev->ip_blocks[i].status.valid = false;
1578 if (adev->ip_blocks[i].version->funcs->early_init) {
1579 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1581 adev->ip_blocks[i].status.valid = false;
1583 DRM_ERROR("early_init of IP block <%s> failed %d\n",
1584 adev->ip_blocks[i].version->funcs->name, r);
1587 adev->ip_blocks[i].status.valid = true;
1590 adev->ip_blocks[i].status.valid = true;
1595 adev->cg_flags &= amdgpu_cg_mask;
1596 adev->pg_flags &= amdgpu_pg_mask;
1601 static int amdgpu_init(struct amdgpu_device *adev)
1605 for (i = 0; i < adev->num_ip_blocks; i++) {
1606 if (!adev->ip_blocks[i].status.valid)
1608 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1610 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1611 adev->ip_blocks[i].version->funcs->name, r);
1614 adev->ip_blocks[i].status.sw = true;
1615 /* need to do gmc hw init early so we can allocate gpu mem */
1616 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1617 r = amdgpu_vram_scratch_init(adev);
1619 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1622 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1624 DRM_ERROR("hw_init %d failed %d\n", i, r);
1627 r = amdgpu_wb_init(adev);
1629 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1632 adev->ip_blocks[i].status.hw = true;
1634 /* right after GMC hw init, we create CSA */
1635 if (amdgpu_sriov_vf(adev)) {
1636 r = amdgpu_allocate_static_csa(adev);
1638 DRM_ERROR("allocate CSA failed %d\n", r);
1645 for (i = 0; i < adev->num_ip_blocks; i++) {
1646 if (!adev->ip_blocks[i].status.sw)
1648 /* gmc hw init is done early */
1649 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
1651 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1653 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1654 adev->ip_blocks[i].version->funcs->name, r);
1657 adev->ip_blocks[i].status.hw = true;
1663 static void amdgpu_fill_reset_magic(struct amdgpu_device *adev)
1665 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1668 static bool amdgpu_check_vram_lost(struct amdgpu_device *adev)
1670 return !!memcmp(adev->gart.ptr, adev->reset_magic,
1671 AMDGPU_RESET_MAGIC_NUM);
1674 static int amdgpu_late_set_cg_state(struct amdgpu_device *adev)
1678 for (i = 0; i < adev->num_ip_blocks; i++) {
1679 if (!adev->ip_blocks[i].status.valid)
1681 /* skip CG for VCE/UVD, it's handled specially */
1682 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1683 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1684 /* enable clockgating to save power */
1685 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1688 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1689 adev->ip_blocks[i].version->funcs->name, r);
1697 static int amdgpu_late_init(struct amdgpu_device *adev)
1701 for (i = 0; i < adev->num_ip_blocks; i++) {
1702 if (!adev->ip_blocks[i].status.valid)
1704 if (adev->ip_blocks[i].version->funcs->late_init) {
1705 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1707 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1708 adev->ip_blocks[i].version->funcs->name, r);
1711 adev->ip_blocks[i].status.late_initialized = true;
1715 mod_delayed_work(system_wq, &adev->late_init_work,
1716 msecs_to_jiffies(AMDGPU_RESUME_MS));
1718 amdgpu_fill_reset_magic(adev);
1723 static int amdgpu_fini(struct amdgpu_device *adev)
1727 /* need to disable SMC first */
1728 for (i = 0; i < adev->num_ip_blocks; i++) {
1729 if (!adev->ip_blocks[i].status.hw)
1731 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1732 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1733 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1734 AMD_CG_STATE_UNGATE);
1736 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1737 adev->ip_blocks[i].version->funcs->name, r);
1740 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1741 /* XXX handle errors */
1743 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1744 adev->ip_blocks[i].version->funcs->name, r);
1746 adev->ip_blocks[i].status.hw = false;
1751 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1752 if (!adev->ip_blocks[i].status.hw)
1754 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1755 amdgpu_wb_fini(adev);
1756 amdgpu_vram_scratch_fini(adev);
1759 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1760 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1761 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1762 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1763 AMD_CG_STATE_UNGATE);
1765 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1766 adev->ip_blocks[i].version->funcs->name, r);
1771 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1772 /* XXX handle errors */
1774 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1775 adev->ip_blocks[i].version->funcs->name, r);
1778 adev->ip_blocks[i].status.hw = false;
1781 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1782 if (!adev->ip_blocks[i].status.sw)
1784 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1785 /* XXX handle errors */
1787 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1788 adev->ip_blocks[i].version->funcs->name, r);
1790 adev->ip_blocks[i].status.sw = false;
1791 adev->ip_blocks[i].status.valid = false;
1794 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1795 if (!adev->ip_blocks[i].status.late_initialized)
1797 if (adev->ip_blocks[i].version->funcs->late_fini)
1798 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1799 adev->ip_blocks[i].status.late_initialized = false;
1802 if (amdgpu_sriov_vf(adev)) {
1803 amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL);
1804 amdgpu_virt_release_full_gpu(adev, false);
1810 static void amdgpu_late_init_func_handler(struct work_struct *work)
1812 struct amdgpu_device *adev =
1813 container_of(work, struct amdgpu_device, late_init_work.work);
1814 amdgpu_late_set_cg_state(adev);
1817 int amdgpu_suspend(struct amdgpu_device *adev)
1821 if (amdgpu_sriov_vf(adev))
1822 amdgpu_virt_request_full_gpu(adev, false);
1824 /* ungate SMC block first */
1825 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1826 AMD_CG_STATE_UNGATE);
1828 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1831 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1832 if (!adev->ip_blocks[i].status.valid)
1834 /* ungate blocks so that suspend can properly shut them down */
1835 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1836 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1837 AMD_CG_STATE_UNGATE);
1839 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1840 adev->ip_blocks[i].version->funcs->name, r);
1843 /* XXX handle errors */
1844 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1845 /* XXX handle errors */
1847 DRM_ERROR("suspend of IP block <%s> failed %d\n",
1848 adev->ip_blocks[i].version->funcs->name, r);
1852 if (amdgpu_sriov_vf(adev))
1853 amdgpu_virt_release_full_gpu(adev, false);
1858 static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
1862 static enum amd_ip_block_type ip_order[] = {
1863 AMD_IP_BLOCK_TYPE_GMC,
1864 AMD_IP_BLOCK_TYPE_COMMON,
1865 AMD_IP_BLOCK_TYPE_MMHUB,
1866 AMD_IP_BLOCK_TYPE_IH,
1869 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1871 struct amdgpu_ip_block *block;
1873 for (j = 0; j < adev->num_ip_blocks; j++) {
1874 block = &adev->ip_blocks[j];
1876 if (block->version->type != ip_order[i] ||
1877 !block->status.valid)
1880 r = block->version->funcs->hw_init(adev);
1881 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1888 static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
1892 static enum amd_ip_block_type ip_order[] = {
1893 AMD_IP_BLOCK_TYPE_SMC,
1894 AMD_IP_BLOCK_TYPE_DCE,
1895 AMD_IP_BLOCK_TYPE_GFX,
1896 AMD_IP_BLOCK_TYPE_SDMA,
1897 AMD_IP_BLOCK_TYPE_VCE,
1900 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1902 struct amdgpu_ip_block *block;
1904 for (j = 0; j < adev->num_ip_blocks; j++) {
1905 block = &adev->ip_blocks[j];
1907 if (block->version->type != ip_order[i] ||
1908 !block->status.valid)
1911 r = block->version->funcs->hw_init(adev);
1912 DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
1919 static int amdgpu_resume_phase1(struct amdgpu_device *adev)
1923 for (i = 0; i < adev->num_ip_blocks; i++) {
1924 if (!adev->ip_blocks[i].status.valid)
1926 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1927 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1928 adev->ip_blocks[i].version->type ==
1929 AMD_IP_BLOCK_TYPE_IH) {
1930 r = adev->ip_blocks[i].version->funcs->resume(adev);
1932 DRM_ERROR("resume of IP block <%s> failed %d\n",
1933 adev->ip_blocks[i].version->funcs->name, r);
1942 static int amdgpu_resume_phase2(struct amdgpu_device *adev)
1946 for (i = 0; i < adev->num_ip_blocks; i++) {
1947 if (!adev->ip_blocks[i].status.valid)
1949 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
1950 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
1951 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
1953 r = adev->ip_blocks[i].version->funcs->resume(adev);
1955 DRM_ERROR("resume of IP block <%s> failed %d\n",
1956 adev->ip_blocks[i].version->funcs->name, r);
1964 static int amdgpu_resume(struct amdgpu_device *adev)
1968 r = amdgpu_resume_phase1(adev);
1971 r = amdgpu_resume_phase2(adev);
1976 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1978 if (adev->is_atom_fw) {
1979 if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
1980 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1982 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1983 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1988 * amdgpu_device_init - initialize the driver
1990 * @adev: amdgpu_device pointer
1991 * @pdev: drm dev pointer
1992 * @pdev: pci dev pointer
1993 * @flags: driver flags
1995 * Initializes the driver info and hw (all asics).
1996 * Returns 0 for success or an error on failure.
1997 * Called at driver startup.
1999 int amdgpu_device_init(struct amdgpu_device *adev,
2000 struct drm_device *ddev,
2001 struct pci_dev *pdev,
2005 bool runtime = false;
2008 adev->shutdown = false;
2009 adev->dev = &pdev->dev;
2012 adev->flags = flags;
2013 adev->asic_type = flags & AMD_ASIC_MASK;
2014 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2015 adev->mc.gtt_size = 512 * 1024 * 1024;
2016 adev->accel_working = false;
2017 adev->num_rings = 0;
2018 adev->mman.buffer_funcs = NULL;
2019 adev->mman.buffer_funcs_ring = NULL;
2020 adev->vm_manager.vm_pte_funcs = NULL;
2021 adev->vm_manager.vm_pte_num_rings = 0;
2022 adev->gart.gart_funcs = NULL;
2023 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2025 adev->smc_rreg = &amdgpu_invalid_rreg;
2026 adev->smc_wreg = &amdgpu_invalid_wreg;
2027 adev->pcie_rreg = &amdgpu_invalid_rreg;
2028 adev->pcie_wreg = &amdgpu_invalid_wreg;
2029 adev->pciep_rreg = &amdgpu_invalid_rreg;
2030 adev->pciep_wreg = &amdgpu_invalid_wreg;
2031 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2032 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2033 adev->didt_rreg = &amdgpu_invalid_rreg;
2034 adev->didt_wreg = &amdgpu_invalid_wreg;
2035 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2036 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2037 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2038 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2041 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2042 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2043 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2045 /* mutex initialization are all done here so we
2046 * can recall function without having locking issues */
2047 atomic_set(&adev->irq.ih.lock, 0);
2048 mutex_init(&adev->firmware.mutex);
2049 mutex_init(&adev->pm.mutex);
2050 mutex_init(&adev->gfx.gpu_clock_mutex);
2051 mutex_init(&adev->srbm_mutex);
2052 mutex_init(&adev->grbm_idx_mutex);
2053 mutex_init(&adev->mn_lock);
2054 hash_init(adev->mn_hash);
2056 amdgpu_check_arguments(adev);
2058 /* Registers mapping */
2059 /* TODO: block userspace mapping of io register */
2060 spin_lock_init(&adev->mmio_idx_lock);
2061 spin_lock_init(&adev->smc_idx_lock);
2062 spin_lock_init(&adev->pcie_idx_lock);
2063 spin_lock_init(&adev->uvd_ctx_idx_lock);
2064 spin_lock_init(&adev->didt_idx_lock);
2065 spin_lock_init(&adev->gc_cac_idx_lock);
2066 spin_lock_init(&adev->audio_endpt_idx_lock);
2067 spin_lock_init(&adev->mm_stats.lock);
2069 INIT_LIST_HEAD(&adev->shadow_list);
2070 mutex_init(&adev->shadow_list_lock);
2072 INIT_LIST_HEAD(&adev->gtt_list);
2073 spin_lock_init(&adev->gtt_list_lock);
2075 INIT_LIST_HEAD(&adev->ring_lru_list);
2076 spin_lock_init(&adev->ring_lru_list_lock);
2078 INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler);
2080 if (adev->asic_type >= CHIP_BONAIRE) {
2081 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2082 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2084 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2085 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2088 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2089 if (adev->rmmio == NULL) {
2092 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2093 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2095 if (adev->asic_type >= CHIP_BONAIRE)
2096 /* doorbell bar mapping */
2097 amdgpu_doorbell_init(adev);
2099 /* io port mapping */
2100 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2101 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2102 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2103 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2107 if (adev->rio_mem == NULL)
2108 DRM_INFO("PCI I/O BAR is not found.\n");
2110 /* early init functions */
2111 r = amdgpu_early_init(adev);
2115 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2116 /* this will fail for cards that aren't VGA class devices, just
2118 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
2120 if (amdgpu_runtime_pm == 1)
2122 if (amdgpu_device_is_px(ddev))
2124 if (!pci_is_thunderbolt_attached(adev->pdev))
2125 vga_switcheroo_register_client(adev->pdev,
2126 &amdgpu_switcheroo_ops, runtime);
2128 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2131 if (!amdgpu_get_bios(adev)) {
2136 r = amdgpu_atombios_init(adev);
2138 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2142 /* detect if we are with an SRIOV vbios */
2143 amdgpu_device_detect_sriov_bios(adev);
2145 /* Post card if necessary */
2146 if (amdgpu_vpost_needed(adev)) {
2148 dev_err(adev->dev, "no vBIOS found\n");
2152 DRM_INFO("GPU posting now...\n");
2153 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2155 dev_err(adev->dev, "gpu post error!\n");
2159 DRM_INFO("GPU post is not needed\n");
2162 if (!adev->is_atom_fw) {
2163 /* Initialize clocks */
2164 r = amdgpu_atombios_get_clock_info(adev);
2166 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2169 /* init i2c buses */
2170 amdgpu_atombios_i2c_init(adev);
2174 r = amdgpu_fence_driver_init(adev);
2176 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2180 /* init the mode config */
2181 drm_mode_config_init(adev->ddev);
2183 r = amdgpu_init(adev);
2185 dev_err(adev->dev, "amdgpu_init failed\n");
2190 adev->accel_working = true;
2192 amdgpu_vm_check_compute_bug(adev);
2194 /* Initialize the buffer migration limit. */
2195 if (amdgpu_moverate >= 0)
2196 max_MBps = amdgpu_moverate;
2198 max_MBps = 8; /* Allow 8 MB/s. */
2199 /* Get a log2 for easy divisions. */
2200 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2202 r = amdgpu_ib_pool_init(adev);
2204 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2208 r = amdgpu_ib_ring_tests(adev);
2210 DRM_ERROR("ib ring test failed (%d).\n", r);
2212 amdgpu_fbdev_init(adev);
2214 r = amdgpu_gem_debugfs_init(adev);
2216 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2218 r = amdgpu_debugfs_regs_init(adev);
2220 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2222 r = amdgpu_debugfs_firmware_init(adev);
2224 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2226 if ((amdgpu_testing & 1)) {
2227 if (adev->accel_working)
2228 amdgpu_test_moves(adev);
2230 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2232 if (amdgpu_benchmarking) {
2233 if (adev->accel_working)
2234 amdgpu_benchmark(adev, amdgpu_benchmarking);
2236 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2239 /* enable clockgating, etc. after ib tests, etc. since some blocks require
2240 * explicit gating rather than handling it automatically.
2242 r = amdgpu_late_init(adev);
2244 dev_err(adev->dev, "amdgpu_late_init failed\n");
2252 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2257 * amdgpu_device_fini - tear down the driver
2259 * @adev: amdgpu_device pointer
2261 * Tear down the driver info (all asics).
2262 * Called at driver shutdown.
2264 void amdgpu_device_fini(struct amdgpu_device *adev)
2268 DRM_INFO("amdgpu: finishing device.\n");
2269 adev->shutdown = true;
2270 if (adev->mode_info.mode_config_initialized)
2271 drm_crtc_force_disable_all(adev->ddev);
2272 /* evict vram memory */
2273 amdgpu_bo_evict_vram(adev);
2274 amdgpu_ib_pool_fini(adev);
2275 amdgpu_fence_driver_fini(adev);
2276 amdgpu_fbdev_fini(adev);
2277 r = amdgpu_fini(adev);
2278 adev->accel_working = false;
2279 cancel_delayed_work_sync(&adev->late_init_work);
2280 /* free i2c buses */
2281 amdgpu_i2c_fini(adev);
2282 amdgpu_atombios_fini(adev);
2285 if (!pci_is_thunderbolt_attached(adev->pdev))
2286 vga_switcheroo_unregister_client(adev->pdev);
2287 if (adev->flags & AMD_IS_PX)
2288 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2289 vga_client_register(adev->pdev, NULL, NULL, NULL);
2291 pci_iounmap(adev->pdev, adev->rio_mem);
2292 adev->rio_mem = NULL;
2293 iounmap(adev->rmmio);
2295 if (adev->asic_type >= CHIP_BONAIRE)
2296 amdgpu_doorbell_fini(adev);
2297 amdgpu_debugfs_regs_cleanup(adev);
2305 * amdgpu_device_suspend - initiate device suspend
2307 * @pdev: drm dev pointer
2308 * @state: suspend state
2310 * Puts the hw in the suspend state (all asics).
2311 * Returns 0 for success or an error on failure.
2312 * Called at driver suspend.
2314 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2316 struct amdgpu_device *adev;
2317 struct drm_crtc *crtc;
2318 struct drm_connector *connector;
2321 if (dev == NULL || dev->dev_private == NULL) {
2325 adev = dev->dev_private;
2327 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2330 drm_kms_helper_poll_disable(dev);
2332 /* turn off display hw */
2333 drm_modeset_lock_all(dev);
2334 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2335 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2337 drm_modeset_unlock_all(dev);
2339 /* unpin the front buffers and cursors */
2340 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2341 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2342 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
2343 struct amdgpu_bo *robj;
2345 if (amdgpu_crtc->cursor_bo) {
2346 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2347 r = amdgpu_bo_reserve(aobj, true);
2349 amdgpu_bo_unpin(aobj);
2350 amdgpu_bo_unreserve(aobj);
2354 if (rfb == NULL || rfb->obj == NULL) {
2357 robj = gem_to_amdgpu_bo(rfb->obj);
2358 /* don't unpin kernel fb objects */
2359 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2360 r = amdgpu_bo_reserve(robj, true);
2362 amdgpu_bo_unpin(robj);
2363 amdgpu_bo_unreserve(robj);
2367 /* evict vram memory */
2368 amdgpu_bo_evict_vram(adev);
2370 amdgpu_fence_driver_suspend(adev);
2372 r = amdgpu_suspend(adev);
2374 /* evict remaining vram memory
2375 * This second call to evict vram is to evict the gart page table
2378 amdgpu_bo_evict_vram(adev);
2380 if (adev->is_atom_fw)
2381 amdgpu_atomfirmware_scratch_regs_save(adev);
2383 amdgpu_atombios_scratch_regs_save(adev);
2384 pci_save_state(dev->pdev);
2386 /* Shut down the device */
2387 pci_disable_device(dev->pdev);
2388 pci_set_power_state(dev->pdev, PCI_D3hot);
2390 r = amdgpu_asic_reset(adev);
2392 DRM_ERROR("amdgpu asic reset failed\n");
2397 amdgpu_fbdev_set_suspend(adev, 1);
2404 * amdgpu_device_resume - initiate device resume
2406 * @pdev: drm dev pointer
2408 * Bring the hw back to operating state (all asics).
2409 * Returns 0 for success or an error on failure.
2410 * Called at driver resume.
2412 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2414 struct drm_connector *connector;
2415 struct amdgpu_device *adev = dev->dev_private;
2416 struct drm_crtc *crtc;
2419 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2426 pci_set_power_state(dev->pdev, PCI_D0);
2427 pci_restore_state(dev->pdev);
2428 r = pci_enable_device(dev->pdev);
2432 if (adev->is_atom_fw)
2433 amdgpu_atomfirmware_scratch_regs_restore(adev);
2435 amdgpu_atombios_scratch_regs_restore(adev);
2438 if (amdgpu_need_post(adev)) {
2439 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2441 DRM_ERROR("amdgpu asic init failed\n");
2444 r = amdgpu_resume(adev);
2446 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2449 amdgpu_fence_driver_resume(adev);
2452 r = amdgpu_ib_ring_tests(adev);
2454 DRM_ERROR("ib ring test failed (%d).\n", r);
2457 r = amdgpu_late_init(adev);
2462 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2463 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2465 if (amdgpu_crtc->cursor_bo) {
2466 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2467 r = amdgpu_bo_reserve(aobj, true);
2469 r = amdgpu_bo_pin(aobj,
2470 AMDGPU_GEM_DOMAIN_VRAM,
2471 &amdgpu_crtc->cursor_addr);
2473 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2474 amdgpu_bo_unreserve(aobj);
2479 /* blat the mode back in */
2481 drm_helper_resume_force_mode(dev);
2482 /* turn on display hw */
2483 drm_modeset_lock_all(dev);
2484 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2485 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2487 drm_modeset_unlock_all(dev);
2490 drm_kms_helper_poll_enable(dev);
2493 * Most of the connector probing functions try to acquire runtime pm
2494 * refs to ensure that the GPU is powered on when connector polling is
2495 * performed. Since we're calling this from a runtime PM callback,
2496 * trying to acquire rpm refs will cause us to deadlock.
2498 * Since we're guaranteed to be holding the rpm lock, it's safe to
2499 * temporarily disable the rpm helpers so this doesn't deadlock us.
2502 dev->dev->power.disable_depth++;
2504 drm_helper_hpd_irq_event(dev);
2506 dev->dev->power.disable_depth--;
2510 amdgpu_fbdev_set_suspend(adev, 0);
2519 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2522 bool asic_hang = false;
2524 for (i = 0; i < adev->num_ip_blocks; i++) {
2525 if (!adev->ip_blocks[i].status.valid)
2527 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2528 adev->ip_blocks[i].status.hang =
2529 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2530 if (adev->ip_blocks[i].status.hang) {
2531 DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2538 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2542 for (i = 0; i < adev->num_ip_blocks; i++) {
2543 if (!adev->ip_blocks[i].status.valid)
2545 if (adev->ip_blocks[i].status.hang &&
2546 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2547 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2556 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2560 for (i = 0; i < adev->num_ip_blocks; i++) {
2561 if (!adev->ip_blocks[i].status.valid)
2563 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2564 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2565 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2566 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) {
2567 if (adev->ip_blocks[i].status.hang) {
2568 DRM_INFO("Some block need full reset!\n");
2576 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2580 for (i = 0; i < adev->num_ip_blocks; i++) {
2581 if (!adev->ip_blocks[i].status.valid)
2583 if (adev->ip_blocks[i].status.hang &&
2584 adev->ip_blocks[i].version->funcs->soft_reset) {
2585 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2594 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2598 for (i = 0; i < adev->num_ip_blocks; i++) {
2599 if (!adev->ip_blocks[i].status.valid)
2601 if (adev->ip_blocks[i].status.hang &&
2602 adev->ip_blocks[i].version->funcs->post_soft_reset)
2603 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2611 bool amdgpu_need_backup(struct amdgpu_device *adev)
2613 if (adev->flags & AMD_IS_APU)
2616 return amdgpu_lockup_timeout > 0 ? true : false;
2619 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2620 struct amdgpu_ring *ring,
2621 struct amdgpu_bo *bo,
2622 struct dma_fence **fence)
2630 r = amdgpu_bo_reserve(bo, true);
2633 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2634 /* if bo has been evicted, then no need to recover */
2635 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2636 r = amdgpu_bo_validate(bo->shadow);
2638 DRM_ERROR("bo validate failed!\n");
2642 r = amdgpu_ttm_bind(&bo->shadow->tbo, &bo->shadow->tbo.mem);
2644 DRM_ERROR("%p bind failed\n", bo->shadow);
2648 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2651 DRM_ERROR("recover page table failed!\n");
2656 amdgpu_bo_unreserve(bo);
2661 * amdgpu_sriov_gpu_reset - reset the asic
2663 * @adev: amdgpu device pointer
2664 * @job: which job trigger hang
2666 * Attempt the reset the GPU if it has hung (all asics).
2668 * Returns 0 for success or an error on failure.
2670 int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job)
2674 struct amdgpu_bo *bo, *tmp;
2675 struct amdgpu_ring *ring;
2676 struct dma_fence *fence = NULL, *next = NULL;
2678 mutex_lock(&adev->virt.lock_reset);
2679 atomic_inc(&adev->gpu_reset_counter);
2680 adev->gfx.in_reset = true;
2683 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2685 /* we start from the ring trigger GPU hang */
2686 j = job ? job->ring->idx : 0;
2688 /* block scheduler */
2689 for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) {
2690 ring = adev->rings[i % AMDGPU_MAX_RINGS];
2691 if (!ring || !ring->sched.thread)
2694 kthread_park(ring->sched.thread);
2699 /* here give the last chance to check if job removed from mirror-list
2700 * since we already pay some time on kthread_park */
2701 if (job && list_empty(&job->base.node)) {
2702 kthread_unpark(ring->sched.thread);
2706 if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit))
2707 amd_sched_job_kickout(&job->base);
2709 /* only do job_reset on the hang ring if @job not NULL */
2710 amd_sched_hw_job_reset(&ring->sched);
2712 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2713 amdgpu_fence_driver_force_completion_ring(ring);
2716 /* request to take full control of GPU before re-initialization */
2718 amdgpu_virt_reset_gpu(adev);
2720 amdgpu_virt_request_full_gpu(adev, true);
2723 /* Resume IP prior to SMC */
2724 amdgpu_sriov_reinit_early(adev);
2726 /* we need recover gart prior to run SMC/CP/SDMA resume */
2727 amdgpu_ttm_recover_gart(adev);
2729 /* now we are okay to resume SMC/CP/SDMA */
2730 amdgpu_sriov_reinit_late(adev);
2732 amdgpu_irq_gpu_reset_resume_helper(adev);
2734 if (amdgpu_ib_ring_tests(adev))
2735 dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);
2737 /* release full control of GPU after ib test */
2738 amdgpu_virt_release_full_gpu(adev, true);
2740 DRM_INFO("recover vram bo from shadow\n");
2742 ring = adev->mman.buffer_funcs_ring;
2743 mutex_lock(&adev->shadow_list_lock);
2744 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2746 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2748 r = dma_fence_wait(fence, false);
2750 WARN(r, "recovery from shadow isn't completed\n");
2755 dma_fence_put(fence);
2758 mutex_unlock(&adev->shadow_list_lock);
2761 r = dma_fence_wait(fence, false);
2763 WARN(r, "recovery from shadow isn't completed\n");
2765 dma_fence_put(fence);
2767 for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) {
2768 ring = adev->rings[i % AMDGPU_MAX_RINGS];
2769 if (!ring || !ring->sched.thread)
2772 if (job && j != i) {
2773 kthread_unpark(ring->sched.thread);
2777 amd_sched_job_recovery(&ring->sched);
2778 kthread_unpark(ring->sched.thread);
2781 drm_helper_resume_force_mode(adev->ddev);
2783 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2785 /* bad news, how to tell it to userspace ? */
2786 dev_info(adev->dev, "GPU reset failed\n");
2788 dev_info(adev->dev, "GPU reset successed!\n");
2791 adev->gfx.in_reset = false;
2792 mutex_unlock(&adev->virt.lock_reset);
2797 * amdgpu_gpu_reset - reset the asic
2799 * @adev: amdgpu device pointer
2801 * Attempt the reset the GPU if it has hung (all asics).
2802 * Returns 0 for success or an error on failure.
2804 int amdgpu_gpu_reset(struct amdgpu_device *adev)
2808 bool need_full_reset, vram_lost = false;
2810 if (!amdgpu_check_soft_reset(adev)) {
2811 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2815 atomic_inc(&adev->gpu_reset_counter);
2818 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2820 /* block scheduler */
2821 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2822 struct amdgpu_ring *ring = adev->rings[i];
2824 if (!ring || !ring->sched.thread)
2826 kthread_park(ring->sched.thread);
2827 amd_sched_hw_job_reset(&ring->sched);
2829 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2830 amdgpu_fence_driver_force_completion(adev);
2832 need_full_reset = amdgpu_need_full_reset(adev);
2834 if (!need_full_reset) {
2835 amdgpu_pre_soft_reset(adev);
2836 r = amdgpu_soft_reset(adev);
2837 amdgpu_post_soft_reset(adev);
2838 if (r || amdgpu_check_soft_reset(adev)) {
2839 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2840 need_full_reset = true;
2844 if (need_full_reset) {
2845 r = amdgpu_suspend(adev);
2848 /* Disable fb access */
2849 if (adev->mode_info.num_crtc) {
2850 struct amdgpu_mode_mc_save save;
2851 amdgpu_display_stop_mc_access(adev, &save);
2852 amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
2854 if (adev->is_atom_fw)
2855 amdgpu_atomfirmware_scratch_regs_save(adev);
2857 amdgpu_atombios_scratch_regs_save(adev);
2858 r = amdgpu_asic_reset(adev);
2859 if (adev->is_atom_fw)
2860 amdgpu_atomfirmware_scratch_regs_restore(adev);
2862 amdgpu_atombios_scratch_regs_restore(adev);
2864 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2867 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2868 r = amdgpu_resume_phase1(adev);
2871 vram_lost = amdgpu_check_vram_lost(adev);
2873 DRM_ERROR("VRAM is lost!\n");
2874 atomic_inc(&adev->vram_lost_counter);
2876 r = amdgpu_ttm_recover_gart(adev);
2879 r = amdgpu_resume_phase2(adev);
2883 amdgpu_fill_reset_magic(adev);
2888 amdgpu_irq_gpu_reset_resume_helper(adev);
2889 r = amdgpu_ib_ring_tests(adev);
2891 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2892 r = amdgpu_suspend(adev);
2893 need_full_reset = true;
2897 * recovery vm page tables, since we cannot depend on VRAM is
2898 * consistent after gpu full reset.
2900 if (need_full_reset && amdgpu_need_backup(adev)) {
2901 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2902 struct amdgpu_bo *bo, *tmp;
2903 struct dma_fence *fence = NULL, *next = NULL;
2905 DRM_INFO("recover vram bo from shadow\n");
2906 mutex_lock(&adev->shadow_list_lock);
2907 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2909 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2911 r = dma_fence_wait(fence, false);
2913 WARN(r, "recovery from shadow isn't completed\n");
2918 dma_fence_put(fence);
2921 mutex_unlock(&adev->shadow_list_lock);
2923 r = dma_fence_wait(fence, false);
2925 WARN(r, "recovery from shadow isn't completed\n");
2927 dma_fence_put(fence);
2929 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2930 struct amdgpu_ring *ring = adev->rings[i];
2932 if (!ring || !ring->sched.thread)
2935 amd_sched_job_recovery(&ring->sched);
2936 kthread_unpark(ring->sched.thread);
2939 dev_err(adev->dev, "asic resume failed (%d).\n", r);
2940 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2941 if (adev->rings[i] && adev->rings[i]->sched.thread) {
2942 kthread_unpark(adev->rings[i]->sched.thread);
2947 drm_helper_resume_force_mode(adev->ddev);
2949 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2951 /* bad news, how to tell it to userspace ? */
2952 dev_info(adev->dev, "GPU reset failed\n");
2954 dev_info(adev->dev, "GPU reset successed!\n");
2959 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2964 if (amdgpu_pcie_gen_cap)
2965 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2967 if (amdgpu_pcie_lane_cap)
2968 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2970 /* covers APUs as well */
2971 if (pci_is_root_bus(adev->pdev->bus)) {
2972 if (adev->pm.pcie_gen_mask == 0)
2973 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2974 if (adev->pm.pcie_mlw_mask == 0)
2975 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2979 if (adev->pm.pcie_gen_mask == 0) {
2980 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2982 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2983 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2984 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2986 if (mask & DRM_PCIE_SPEED_25)
2987 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2988 if (mask & DRM_PCIE_SPEED_50)
2989 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2990 if (mask & DRM_PCIE_SPEED_80)
2991 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2993 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2996 if (adev->pm.pcie_mlw_mask == 0) {
2997 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
3001 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3002 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3003 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3004 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3005 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3006 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3007 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3010 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3011 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3012 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3013 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3014 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3015 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3018 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3019 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3020 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3021 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3022 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3025 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3026 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3027 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3028 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3031 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3032 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3033 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3036 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3037 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3040 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
3046 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3054 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
3055 const struct drm_info_list *files,
3060 for (i = 0; i < adev->debugfs_count; i++) {
3061 if (adev->debugfs[i].files == files) {
3062 /* Already registered */
3067 i = adev->debugfs_count + 1;
3068 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
3069 DRM_ERROR("Reached maximum number of debugfs components.\n");
3070 DRM_ERROR("Report so we increase "
3071 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
3074 adev->debugfs[adev->debugfs_count].files = files;
3075 adev->debugfs[adev->debugfs_count].num_files = nfiles;
3076 adev->debugfs_count = i;
3077 #if defined(CONFIG_DEBUG_FS)
3078 drm_debugfs_create_files(files, nfiles,
3079 adev->ddev->primary->debugfs_root,
3080 adev->ddev->primary);
3085 #if defined(CONFIG_DEBUG_FS)
3087 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
3088 size_t size, loff_t *pos)
3090 struct amdgpu_device *adev = file_inode(f)->i_private;
3093 bool pm_pg_lock, use_bank;
3094 unsigned instance_bank, sh_bank, se_bank;
3096 if (size & 0x3 || *pos & 0x3)
3099 /* are we reading registers for which a PG lock is necessary? */
3100 pm_pg_lock = (*pos >> 23) & 1;
3102 if (*pos & (1ULL << 62)) {
3103 se_bank = (*pos >> 24) & 0x3FF;
3104 sh_bank = (*pos >> 34) & 0x3FF;
3105 instance_bank = (*pos >> 44) & 0x3FF;
3107 if (se_bank == 0x3FF)
3108 se_bank = 0xFFFFFFFF;
3109 if (sh_bank == 0x3FF)
3110 sh_bank = 0xFFFFFFFF;
3111 if (instance_bank == 0x3FF)
3112 instance_bank = 0xFFFFFFFF;
3118 *pos &= (1UL << 22) - 1;
3121 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
3122 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3124 mutex_lock(&adev->grbm_idx_mutex);
3125 amdgpu_gfx_select_se_sh(adev, se_bank,
3126 sh_bank, instance_bank);
3130 mutex_lock(&adev->pm.mutex);
3135 if (*pos > adev->rmmio_size)
3138 value = RREG32(*pos >> 2);
3139 r = put_user(value, (uint32_t *)buf);
3153 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3154 mutex_unlock(&adev->grbm_idx_mutex);
3158 mutex_unlock(&adev->pm.mutex);
3163 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
3164 size_t size, loff_t *pos)
3166 struct amdgpu_device *adev = file_inode(f)->i_private;
3169 bool pm_pg_lock, use_bank;
3170 unsigned instance_bank, sh_bank, se_bank;
3172 if (size & 0x3 || *pos & 0x3)
3175 /* are we reading registers for which a PG lock is necessary? */
3176 pm_pg_lock = (*pos >> 23) & 1;
3178 if (*pos & (1ULL << 62)) {
3179 se_bank = (*pos >> 24) & 0x3FF;
3180 sh_bank = (*pos >> 34) & 0x3FF;
3181 instance_bank = (*pos >> 44) & 0x3FF;
3183 if (se_bank == 0x3FF)
3184 se_bank = 0xFFFFFFFF;
3185 if (sh_bank == 0x3FF)
3186 sh_bank = 0xFFFFFFFF;
3187 if (instance_bank == 0x3FF)
3188 instance_bank = 0xFFFFFFFF;
3194 *pos &= (1UL << 22) - 1;
3197 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
3198 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3200 mutex_lock(&adev->grbm_idx_mutex);
3201 amdgpu_gfx_select_se_sh(adev, se_bank,
3202 sh_bank, instance_bank);
3206 mutex_lock(&adev->pm.mutex);
3211 if (*pos > adev->rmmio_size)
3214 r = get_user(value, (uint32_t *)buf);
3218 WREG32(*pos >> 2, value);
3227 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3228 mutex_unlock(&adev->grbm_idx_mutex);
3232 mutex_unlock(&adev->pm.mutex);
3237 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
3238 size_t size, loff_t *pos)
3240 struct amdgpu_device *adev = file_inode(f)->i_private;
3244 if (size & 0x3 || *pos & 0x3)
3250 value = RREG32_PCIE(*pos >> 2);
3251 r = put_user(value, (uint32_t *)buf);
3264 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
3265 size_t size, loff_t *pos)
3267 struct amdgpu_device *adev = file_inode(f)->i_private;
3271 if (size & 0x3 || *pos & 0x3)
3277 r = get_user(value, (uint32_t *)buf);
3281 WREG32_PCIE(*pos >> 2, value);
3292 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
3293 size_t size, loff_t *pos)
3295 struct amdgpu_device *adev = file_inode(f)->i_private;
3299 if (size & 0x3 || *pos & 0x3)
3305 value = RREG32_DIDT(*pos >> 2);
3306 r = put_user(value, (uint32_t *)buf);
3319 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
3320 size_t size, loff_t *pos)
3322 struct amdgpu_device *adev = file_inode(f)->i_private;
3326 if (size & 0x3 || *pos & 0x3)
3332 r = get_user(value, (uint32_t *)buf);
3336 WREG32_DIDT(*pos >> 2, value);
3347 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
3348 size_t size, loff_t *pos)
3350 struct amdgpu_device *adev = file_inode(f)->i_private;
3354 if (size & 0x3 || *pos & 0x3)
3360 value = RREG32_SMC(*pos);
3361 r = put_user(value, (uint32_t *)buf);
3374 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
3375 size_t size, loff_t *pos)
3377 struct amdgpu_device *adev = file_inode(f)->i_private;
3381 if (size & 0x3 || *pos & 0x3)
3387 r = get_user(value, (uint32_t *)buf);
3391 WREG32_SMC(*pos, value);
3402 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
3403 size_t size, loff_t *pos)
3405 struct amdgpu_device *adev = file_inode(f)->i_private;
3408 uint32_t *config, no_regs = 0;
3410 if (size & 0x3 || *pos & 0x3)
3413 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
3417 /* version, increment each time something is added */
3418 config[no_regs++] = 3;
3419 config[no_regs++] = adev->gfx.config.max_shader_engines;
3420 config[no_regs++] = adev->gfx.config.max_tile_pipes;
3421 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
3422 config[no_regs++] = adev->gfx.config.max_sh_per_se;
3423 config[no_regs++] = adev->gfx.config.max_backends_per_se;
3424 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
3425 config[no_regs++] = adev->gfx.config.max_gprs;
3426 config[no_regs++] = adev->gfx.config.max_gs_threads;
3427 config[no_regs++] = adev->gfx.config.max_hw_contexts;
3428 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
3429 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
3430 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
3431 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
3432 config[no_regs++] = adev->gfx.config.num_tile_pipes;
3433 config[no_regs++] = adev->gfx.config.backend_enable_mask;
3434 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
3435 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
3436 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
3437 config[no_regs++] = adev->gfx.config.num_gpus;
3438 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
3439 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
3440 config[no_regs++] = adev->gfx.config.gb_addr_config;
3441 config[no_regs++] = adev->gfx.config.num_rbs;
3444 config[no_regs++] = adev->rev_id;
3445 config[no_regs++] = adev->pg_flags;
3446 config[no_regs++] = adev->cg_flags;
3449 config[no_regs++] = adev->family;
3450 config[no_regs++] = adev->external_rev_id;
3453 config[no_regs++] = adev->pdev->device;
3454 config[no_regs++] = adev->pdev->revision;
3455 config[no_regs++] = adev->pdev->subsystem_device;
3456 config[no_regs++] = adev->pdev->subsystem_vendor;
3458 while (size && (*pos < no_regs * 4)) {
3461 value = config[*pos >> 2];
3462 r = put_user(value, (uint32_t *)buf);
3478 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
3479 size_t size, loff_t *pos)
3481 struct amdgpu_device *adev = file_inode(f)->i_private;
3482 int idx, x, outsize, r, valuesize;
3483 uint32_t values[16];
3485 if (size & 3 || *pos & 0x3)
3488 if (amdgpu_dpm == 0)
3491 /* convert offset to sensor number */
3494 valuesize = sizeof(values);
3495 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
3496 r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize);
3497 else if (adev->pm.funcs && adev->pm.funcs->read_sensor)
3498 r = adev->pm.funcs->read_sensor(adev, idx, &values[0],
3503 if (size > valuesize)
3510 r = put_user(values[x++], (int32_t *)buf);
3517 return !r ? outsize : r;
3520 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
3521 size_t size, loff_t *pos)
3523 struct amdgpu_device *adev = f->f_inode->i_private;
3526 uint32_t offset, se, sh, cu, wave, simd, data[32];
3528 if (size & 3 || *pos & 3)
3532 offset = (*pos & 0x7F);
3533 se = ((*pos >> 7) & 0xFF);
3534 sh = ((*pos >> 15) & 0xFF);
3535 cu = ((*pos >> 23) & 0xFF);
3536 wave = ((*pos >> 31) & 0xFF);
3537 simd = ((*pos >> 37) & 0xFF);
3539 /* switch to the specific se/sh/cu */
3540 mutex_lock(&adev->grbm_idx_mutex);
3541 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3544 if (adev->gfx.funcs->read_wave_data)
3545 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
3547 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3548 mutex_unlock(&adev->grbm_idx_mutex);
3553 while (size && (offset < x * 4)) {
3556 value = data[offset >> 2];
3557 r = put_user(value, (uint32_t *)buf);
3570 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
3571 size_t size, loff_t *pos)
3573 struct amdgpu_device *adev = f->f_inode->i_private;
3576 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
3578 if (size & 3 || *pos & 3)
3582 offset = (*pos & 0xFFF); /* in dwords */
3583 se = ((*pos >> 12) & 0xFF);
3584 sh = ((*pos >> 20) & 0xFF);
3585 cu = ((*pos >> 28) & 0xFF);
3586 wave = ((*pos >> 36) & 0xFF);
3587 simd = ((*pos >> 44) & 0xFF);
3588 thread = ((*pos >> 52) & 0xFF);
3589 bank = ((*pos >> 60) & 1);
3591 data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
3595 /* switch to the specific se/sh/cu */
3596 mutex_lock(&adev->grbm_idx_mutex);
3597 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3600 if (adev->gfx.funcs->read_wave_vgprs)
3601 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
3603 if (adev->gfx.funcs->read_wave_sgprs)
3604 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
3607 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3608 mutex_unlock(&adev->grbm_idx_mutex);
3613 value = data[offset++];
3614 r = put_user(value, (uint32_t *)buf);
3630 static const struct file_operations amdgpu_debugfs_regs_fops = {
3631 .owner = THIS_MODULE,
3632 .read = amdgpu_debugfs_regs_read,
3633 .write = amdgpu_debugfs_regs_write,
3634 .llseek = default_llseek
3636 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
3637 .owner = THIS_MODULE,
3638 .read = amdgpu_debugfs_regs_didt_read,
3639 .write = amdgpu_debugfs_regs_didt_write,
3640 .llseek = default_llseek
3642 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
3643 .owner = THIS_MODULE,
3644 .read = amdgpu_debugfs_regs_pcie_read,
3645 .write = amdgpu_debugfs_regs_pcie_write,
3646 .llseek = default_llseek
3648 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
3649 .owner = THIS_MODULE,
3650 .read = amdgpu_debugfs_regs_smc_read,
3651 .write = amdgpu_debugfs_regs_smc_write,
3652 .llseek = default_llseek
3655 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
3656 .owner = THIS_MODULE,
3657 .read = amdgpu_debugfs_gca_config_read,
3658 .llseek = default_llseek
3661 static const struct file_operations amdgpu_debugfs_sensors_fops = {
3662 .owner = THIS_MODULE,
3663 .read = amdgpu_debugfs_sensor_read,
3664 .llseek = default_llseek
3667 static const struct file_operations amdgpu_debugfs_wave_fops = {
3668 .owner = THIS_MODULE,
3669 .read = amdgpu_debugfs_wave_read,
3670 .llseek = default_llseek
3672 static const struct file_operations amdgpu_debugfs_gpr_fops = {
3673 .owner = THIS_MODULE,
3674 .read = amdgpu_debugfs_gpr_read,
3675 .llseek = default_llseek
3678 static const struct file_operations *debugfs_regs[] = {
3679 &amdgpu_debugfs_regs_fops,
3680 &amdgpu_debugfs_regs_didt_fops,
3681 &amdgpu_debugfs_regs_pcie_fops,
3682 &amdgpu_debugfs_regs_smc_fops,
3683 &amdgpu_debugfs_gca_config_fops,
3684 &amdgpu_debugfs_sensors_fops,
3685 &amdgpu_debugfs_wave_fops,
3686 &amdgpu_debugfs_gpr_fops,
3689 static const char *debugfs_regs_names[] = {
3694 "amdgpu_gca_config",
3700 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3702 struct drm_minor *minor = adev->ddev->primary;
3703 struct dentry *ent, *root = minor->debugfs_root;
3706 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3707 ent = debugfs_create_file(debugfs_regs_names[i],
3708 S_IFREG | S_IRUGO, root,
3709 adev, debugfs_regs[i]);
3711 for (j = 0; j < i; j++) {
3712 debugfs_remove(adev->debugfs_regs[i]);
3713 adev->debugfs_regs[i] = NULL;
3715 return PTR_ERR(ent);
3719 i_size_write(ent->d_inode, adev->rmmio_size);
3720 adev->debugfs_regs[i] = ent;
3726 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
3730 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3731 if (adev->debugfs_regs[i]) {
3732 debugfs_remove(adev->debugfs_regs[i]);
3733 adev->debugfs_regs[i] = NULL;
3738 int amdgpu_debugfs_init(struct drm_minor *minor)
3743 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3747 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }