2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
33 #include <linux/iommu.h>
34 #include <linux/pci.h>
35 #include <linux/devcoredump.h>
36 #include <generated/utsrelease.h>
37 #include <linux/pci-p2pdma.h>
38 #include <linux/apple-gmux.h>
40 #include <drm/drm_aperture.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_fb_helper.h>
44 #include <drm/drm_probe_helper.h>
45 #include <drm/amdgpu_drm.h>
46 #include <linux/vgaarb.h>
47 #include <linux/vga_switcheroo.h>
48 #include <linux/efi.h>
50 #include "amdgpu_trace.h"
51 #include "amdgpu_i2c.h"
53 #include "amdgpu_atombios.h"
54 #include "amdgpu_atomfirmware.h"
56 #ifdef CONFIG_DRM_AMDGPU_SI
59 #ifdef CONFIG_DRM_AMDGPU_CIK
65 #include "bif/bif_4_1_d.h"
66 #include <linux/firmware.h>
67 #include "amdgpu_vf_error.h"
69 #include "amdgpu_amdkfd.h"
70 #include "amdgpu_pm.h"
72 #include "amdgpu_xgmi.h"
73 #include "amdgpu_ras.h"
74 #include "amdgpu_pmu.h"
75 #include "amdgpu_fru_eeprom.h"
76 #include "amdgpu_reset.h"
78 #include <linux/suspend.h>
79 #include <drm/task_barrier.h>
80 #include <linux/pm_runtime.h>
82 #include <drm/drm_drv.h>
84 #if IS_ENABLED(CONFIG_X86)
85 #include <asm/intel-family.h>
88 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
89 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
90 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
91 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
92 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
93 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
94 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
96 #define AMDGPU_RESUME_MS 2000
97 #define AMDGPU_MAX_RETRY_LIMIT 2
98 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
100 static const struct drm_driver amdgpu_kms_driver;
102 const char *amdgpu_asic_name[] = {
144 * DOC: pcie_replay_count
146 * The amdgpu driver provides a sysfs API for reporting the total number
147 * of PCIe replays (NAKs)
148 * The file pcie_replay_count is used for this and returns the total
149 * number of replays as a sum of the NAKs generated and NAKs received
152 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
153 struct device_attribute *attr, char *buf)
155 struct drm_device *ddev = dev_get_drvdata(dev);
156 struct amdgpu_device *adev = drm_to_adev(ddev);
157 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
159 return sysfs_emit(buf, "%llu\n", cnt);
162 static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
163 amdgpu_device_get_pcie_replay_count, NULL);
165 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
170 * The amdgpu driver provides a sysfs API for reporting the product name
172 * The file product_name is used for this and returns the product name
173 * as returned from the FRU.
174 * NOTE: This is only available for certain server cards
177 static ssize_t amdgpu_device_get_product_name(struct device *dev,
178 struct device_attribute *attr, char *buf)
180 struct drm_device *ddev = dev_get_drvdata(dev);
181 struct amdgpu_device *adev = drm_to_adev(ddev);
183 return sysfs_emit(buf, "%s\n", adev->product_name);
186 static DEVICE_ATTR(product_name, S_IRUGO,
187 amdgpu_device_get_product_name, NULL);
190 * DOC: product_number
192 * The amdgpu driver provides a sysfs API for reporting the part number
194 * The file product_number is used for this and returns the part number
195 * as returned from the FRU.
196 * NOTE: This is only available for certain server cards
199 static ssize_t amdgpu_device_get_product_number(struct device *dev,
200 struct device_attribute *attr, char *buf)
202 struct drm_device *ddev = dev_get_drvdata(dev);
203 struct amdgpu_device *adev = drm_to_adev(ddev);
205 return sysfs_emit(buf, "%s\n", adev->product_number);
208 static DEVICE_ATTR(product_number, S_IRUGO,
209 amdgpu_device_get_product_number, NULL);
214 * The amdgpu driver provides a sysfs API for reporting the serial number
216 * The file serial_number is used for this and returns the serial number
217 * as returned from the FRU.
218 * NOTE: This is only available for certain server cards
221 static ssize_t amdgpu_device_get_serial_number(struct device *dev,
222 struct device_attribute *attr, char *buf)
224 struct drm_device *ddev = dev_get_drvdata(dev);
225 struct amdgpu_device *adev = drm_to_adev(ddev);
227 return sysfs_emit(buf, "%s\n", adev->serial);
230 static DEVICE_ATTR(serial_number, S_IRUGO,
231 amdgpu_device_get_serial_number, NULL);
234 * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control
236 * @dev: drm_device pointer
238 * Returns true if the device is a dGPU with ATPX power control,
239 * otherwise return false.
241 bool amdgpu_device_supports_px(struct drm_device *dev)
243 struct amdgpu_device *adev = drm_to_adev(dev);
245 if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())
251 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
253 * @dev: drm_device pointer
255 * Returns true if the device is a dGPU with ACPI power control,
256 * otherwise return false.
258 bool amdgpu_device_supports_boco(struct drm_device *dev)
260 struct amdgpu_device *adev = drm_to_adev(dev);
263 ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))
269 * amdgpu_device_supports_baco - Does the device support BACO
271 * @dev: drm_device pointer
273 * Returns true if the device supporte BACO,
274 * otherwise return false.
276 bool amdgpu_device_supports_baco(struct drm_device *dev)
278 struct amdgpu_device *adev = drm_to_adev(dev);
280 return amdgpu_asic_supports_baco(adev);
284 * amdgpu_device_supports_smart_shift - Is the device dGPU with
285 * smart shift support
287 * @dev: drm_device pointer
289 * Returns true if the device is a dGPU with Smart Shift support,
290 * otherwise returns false.
292 bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
294 return (amdgpu_device_supports_boco(dev) &&
295 amdgpu_acpi_is_power_shift_control_supported());
299 * VRAM access helper functions
303 * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
305 * @adev: amdgpu_device pointer
306 * @pos: offset of the buffer in vram
307 * @buf: virtual address of the buffer in system memory
308 * @size: read/write size, sizeof(@buf) must > @size
309 * @write: true - write to vram, otherwise - read from vram
311 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
312 void *buf, size_t size, bool write)
315 uint32_t hi = ~0, tmp = 0;
316 uint32_t *data = buf;
320 if (!drm_dev_enter(adev_to_drm(adev), &idx))
323 BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
325 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
326 for (last = pos + size; pos < last; pos += 4) {
329 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
331 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
335 WREG32_NO_KIQ(mmMM_DATA, *data++);
337 *data++ = RREG32_NO_KIQ(mmMM_DATA);
340 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
345 * amdgpu_device_aper_access - access vram by vram aperature
347 * @adev: amdgpu_device pointer
348 * @pos: offset of the buffer in vram
349 * @buf: virtual address of the buffer in system memory
350 * @size: read/write size, sizeof(@buf) must > @size
351 * @write: true - write to vram, otherwise - read from vram
353 * The return value means how many bytes have been transferred.
355 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
356 void *buf, size_t size, bool write)
363 if (!adev->mman.aper_base_kaddr)
366 last = min(pos + size, adev->gmc.visible_vram_size);
368 addr = adev->mman.aper_base_kaddr + pos;
372 memcpy_toio(addr, buf, count);
374 amdgpu_device_flush_hdp(adev, NULL);
376 amdgpu_device_invalidate_hdp(adev, NULL);
378 memcpy_fromio(buf, addr, count);
390 * amdgpu_device_vram_access - read/write a buffer in vram
392 * @adev: amdgpu_device pointer
393 * @pos: offset of the buffer in vram
394 * @buf: virtual address of the buffer in system memory
395 * @size: read/write size, sizeof(@buf) must > @size
396 * @write: true - write to vram, otherwise - read from vram
398 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
399 void *buf, size_t size, bool write)
403 /* try to using vram apreature to access vram first */
404 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
407 /* using MM to access rest vram */
410 amdgpu_device_mm_access(adev, pos, buf, size, write);
415 * register access helper functions.
418 /* Check if hw access should be skipped because of hotplug or device error */
419 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
421 if (adev->no_hw_access)
424 #ifdef CONFIG_LOCKDEP
426 * This is a bit complicated to understand, so worth a comment. What we assert
427 * here is that the GPU reset is not running on another thread in parallel.
429 * For this we trylock the read side of the reset semaphore, if that succeeds
430 * we know that the reset is not running in paralell.
432 * If the trylock fails we assert that we are either already holding the read
433 * side of the lock or are the reset thread itself and hold the write side of
437 if (down_read_trylock(&adev->reset_domain->sem))
438 up_read(&adev->reset_domain->sem);
440 lockdep_assert_held(&adev->reset_domain->sem);
447 * amdgpu_device_rreg - read a memory mapped IO or indirect register
449 * @adev: amdgpu_device pointer
450 * @reg: dword aligned register offset
451 * @acc_flags: access flags which require special behavior
453 * Returns the 32 bit value from the offset specified.
455 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
456 uint32_t reg, uint32_t acc_flags)
460 if (amdgpu_device_skip_hw_access(adev))
463 if ((reg * 4) < adev->rmmio_size) {
464 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
465 amdgpu_sriov_runtime(adev) &&
466 down_read_trylock(&adev->reset_domain->sem)) {
467 ret = amdgpu_kiq_rreg(adev, reg);
468 up_read(&adev->reset_domain->sem);
470 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
473 ret = adev->pcie_rreg(adev, reg * 4);
476 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
482 * MMIO register read with bytes helper functions
483 * @offset:bytes offset from MMIO start
488 * amdgpu_mm_rreg8 - read a memory mapped IO register
490 * @adev: amdgpu_device pointer
491 * @offset: byte aligned register offset
493 * Returns the 8 bit value from the offset specified.
495 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
497 if (amdgpu_device_skip_hw_access(adev))
500 if (offset < adev->rmmio_size)
501 return (readb(adev->rmmio + offset));
506 * MMIO register write with bytes helper functions
507 * @offset:bytes offset from MMIO start
508 * @value: the value want to be written to the register
512 * amdgpu_mm_wreg8 - read a memory mapped IO register
514 * @adev: amdgpu_device pointer
515 * @offset: byte aligned register offset
516 * @value: 8 bit value to write
518 * Writes the value specified to the offset specified.
520 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
522 if (amdgpu_device_skip_hw_access(adev))
525 if (offset < adev->rmmio_size)
526 writeb(value, adev->rmmio + offset);
532 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
534 * @adev: amdgpu_device pointer
535 * @reg: dword aligned register offset
536 * @v: 32 bit value to write to the register
537 * @acc_flags: access flags which require special behavior
539 * Writes the value specified to the offset specified.
541 void amdgpu_device_wreg(struct amdgpu_device *adev,
542 uint32_t reg, uint32_t v,
545 if (amdgpu_device_skip_hw_access(adev))
548 if ((reg * 4) < adev->rmmio_size) {
549 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
550 amdgpu_sriov_runtime(adev) &&
551 down_read_trylock(&adev->reset_domain->sem)) {
552 amdgpu_kiq_wreg(adev, reg, v);
553 up_read(&adev->reset_domain->sem);
555 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
558 adev->pcie_wreg(adev, reg * 4, v);
561 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
565 * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range
567 * @adev: amdgpu_device pointer
568 * @reg: mmio/rlc register
571 * this function is invoked only for the debugfs register access
573 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
574 uint32_t reg, uint32_t v)
576 if (amdgpu_device_skip_hw_access(adev))
579 if (amdgpu_sriov_fullaccess(adev) &&
580 adev->gfx.rlc.funcs &&
581 adev->gfx.rlc.funcs->is_rlcg_access_range) {
582 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
583 return amdgpu_sriov_wreg(adev, reg, v, 0, 0);
584 } else if ((reg * 4) >= adev->rmmio_size) {
585 adev->pcie_wreg(adev, reg * 4, v);
587 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
592 * amdgpu_mm_rdoorbell - read a doorbell dword
594 * @adev: amdgpu_device pointer
595 * @index: doorbell index
597 * Returns the value in the doorbell aperture at the
598 * requested doorbell index (CIK).
600 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
602 if (amdgpu_device_skip_hw_access(adev))
605 if (index < adev->doorbell.num_kernel_doorbells) {
606 return readl(adev->doorbell.ptr + index);
608 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
614 * amdgpu_mm_wdoorbell - write a doorbell dword
616 * @adev: amdgpu_device pointer
617 * @index: doorbell index
620 * Writes @v to the doorbell aperture at the
621 * requested doorbell index (CIK).
623 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
625 if (amdgpu_device_skip_hw_access(adev))
628 if (index < adev->doorbell.num_kernel_doorbells) {
629 writel(v, adev->doorbell.ptr + index);
631 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
636 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
638 * @adev: amdgpu_device pointer
639 * @index: doorbell index
641 * Returns the value in the doorbell aperture at the
642 * requested doorbell index (VEGA10+).
644 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
646 if (amdgpu_device_skip_hw_access(adev))
649 if (index < adev->doorbell.num_kernel_doorbells) {
650 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
652 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
658 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
660 * @adev: amdgpu_device pointer
661 * @index: doorbell index
664 * Writes @v to the doorbell aperture at the
665 * requested doorbell index (VEGA10+).
667 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
669 if (amdgpu_device_skip_hw_access(adev))
672 if (index < adev->doorbell.num_kernel_doorbells) {
673 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
675 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
680 * amdgpu_device_indirect_rreg - read an indirect register
682 * @adev: amdgpu_device pointer
683 * @reg_addr: indirect register address to read from
685 * Returns the value of indirect register @reg_addr
687 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
690 unsigned long flags, pcie_index, pcie_data;
691 void __iomem *pcie_index_offset;
692 void __iomem *pcie_data_offset;
695 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
696 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
698 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
699 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
700 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
702 writel(reg_addr, pcie_index_offset);
703 readl(pcie_index_offset);
704 r = readl(pcie_data_offset);
705 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
711 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
713 * @adev: amdgpu_device pointer
714 * @reg_addr: indirect register address to read from
716 * Returns the value of indirect register @reg_addr
718 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
721 unsigned long flags, pcie_index, pcie_data;
722 void __iomem *pcie_index_offset;
723 void __iomem *pcie_data_offset;
726 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
727 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
729 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
730 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
731 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
733 /* read low 32 bits */
734 writel(reg_addr, pcie_index_offset);
735 readl(pcie_index_offset);
736 r = readl(pcie_data_offset);
737 /* read high 32 bits */
738 writel(reg_addr + 4, pcie_index_offset);
739 readl(pcie_index_offset);
740 r |= ((u64)readl(pcie_data_offset) << 32);
741 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
747 * amdgpu_device_indirect_wreg - write an indirect register address
749 * @adev: amdgpu_device pointer
750 * @pcie_index: mmio register offset
751 * @pcie_data: mmio register offset
752 * @reg_addr: indirect register offset
753 * @reg_data: indirect register data
756 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
757 u32 reg_addr, u32 reg_data)
759 unsigned long flags, pcie_index, pcie_data;
760 void __iomem *pcie_index_offset;
761 void __iomem *pcie_data_offset;
763 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
764 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
766 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
767 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
768 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
770 writel(reg_addr, pcie_index_offset);
771 readl(pcie_index_offset);
772 writel(reg_data, pcie_data_offset);
773 readl(pcie_data_offset);
774 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
778 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
780 * @adev: amdgpu_device pointer
781 * @pcie_index: mmio register offset
782 * @pcie_data: mmio register offset
783 * @reg_addr: indirect register offset
784 * @reg_data: indirect register data
787 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
788 u32 reg_addr, u64 reg_data)
790 unsigned long flags, pcie_index, pcie_data;
791 void __iomem *pcie_index_offset;
792 void __iomem *pcie_data_offset;
794 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
795 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
797 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
798 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
799 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
801 /* write low 32 bits */
802 writel(reg_addr, pcie_index_offset);
803 readl(pcie_index_offset);
804 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
805 readl(pcie_data_offset);
806 /* write high 32 bits */
807 writel(reg_addr + 4, pcie_index_offset);
808 readl(pcie_index_offset);
809 writel((u32)(reg_data >> 32), pcie_data_offset);
810 readl(pcie_data_offset);
811 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
815 * amdgpu_device_get_rev_id - query device rev_id
817 * @adev: amdgpu_device pointer
819 * Return device rev_id
821 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev)
823 return adev->nbio.funcs->get_rev_id(adev);
827 * amdgpu_invalid_rreg - dummy reg read function
829 * @adev: amdgpu_device pointer
830 * @reg: offset of register
832 * Dummy register read function. Used for register blocks
833 * that certain asics don't have (all asics).
834 * Returns the value in the register.
836 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
838 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
844 * amdgpu_invalid_wreg - dummy reg write function
846 * @adev: amdgpu_device pointer
847 * @reg: offset of register
848 * @v: value to write to the register
850 * Dummy register read function. Used for register blocks
851 * that certain asics don't have (all asics).
853 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
855 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
861 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
863 * @adev: amdgpu_device pointer
864 * @reg: offset of register
866 * Dummy register read function. Used for register blocks
867 * that certain asics don't have (all asics).
868 * Returns the value in the register.
870 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
872 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
878 * amdgpu_invalid_wreg64 - dummy reg write function
880 * @adev: amdgpu_device pointer
881 * @reg: offset of register
882 * @v: value to write to the register
884 * Dummy register read function. Used for register blocks
885 * that certain asics don't have (all asics).
887 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
889 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
895 * amdgpu_block_invalid_rreg - dummy reg read function
897 * @adev: amdgpu_device pointer
898 * @block: offset of instance
899 * @reg: offset of register
901 * Dummy register read function. Used for register blocks
902 * that certain asics don't have (all asics).
903 * Returns the value in the register.
905 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
906 uint32_t block, uint32_t reg)
908 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
915 * amdgpu_block_invalid_wreg - dummy reg write function
917 * @adev: amdgpu_device pointer
918 * @block: offset of instance
919 * @reg: offset of register
920 * @v: value to write to the register
922 * Dummy register read function. Used for register blocks
923 * that certain asics don't have (all asics).
925 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
927 uint32_t reg, uint32_t v)
929 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
935 * amdgpu_device_asic_init - Wrapper for atom asic_init
937 * @adev: amdgpu_device pointer
939 * Does any asic specific work and then calls atom asic init.
941 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
943 amdgpu_asic_pre_asic_init(adev);
945 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
946 return amdgpu_atomfirmware_asic_init(adev, true);
948 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
952 * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page
954 * @adev: amdgpu_device pointer
956 * Allocates a scratch page of VRAM for use by various things in the
959 static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev)
961 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
962 AMDGPU_GEM_DOMAIN_VRAM |
963 AMDGPU_GEM_DOMAIN_GTT,
964 &adev->mem_scratch.robj,
965 &adev->mem_scratch.gpu_addr,
966 (void **)&adev->mem_scratch.ptr);
970 * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page
972 * @adev: amdgpu_device pointer
974 * Frees the VRAM scratch page.
976 static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev)
978 amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL);
982 * amdgpu_device_program_register_sequence - program an array of registers.
984 * @adev: amdgpu_device pointer
985 * @registers: pointer to the register array
986 * @array_size: size of the register array
988 * Programs an array or registers with and and or masks.
989 * This is a helper for setting golden registers.
991 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
992 const u32 *registers,
993 const u32 array_size)
995 u32 tmp, reg, and_mask, or_mask;
1001 for (i = 0; i < array_size; i += 3) {
1002 reg = registers[i + 0];
1003 and_mask = registers[i + 1];
1004 or_mask = registers[i + 2];
1006 if (and_mask == 0xffffffff) {
1011 if (adev->family >= AMDGPU_FAMILY_AI)
1012 tmp |= (or_mask & and_mask);
1021 * amdgpu_device_pci_config_reset - reset the GPU
1023 * @adev: amdgpu_device pointer
1025 * Resets the GPU using the pci config reset sequence.
1026 * Only applicable to asics prior to vega10.
1028 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
1030 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
1034 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
1036 * @adev: amdgpu_device pointer
1038 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
1040 int amdgpu_device_pci_reset(struct amdgpu_device *adev)
1042 return pci_reset_function(adev->pdev);
1046 * GPU doorbell aperture helpers function.
1049 * amdgpu_device_doorbell_init - Init doorbell driver information.
1051 * @adev: amdgpu_device pointer
1053 * Init doorbell driver information (CIK)
1054 * Returns 0 on success, error on failure.
1056 static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
1059 /* No doorbell on SI hardware generation */
1060 if (adev->asic_type < CHIP_BONAIRE) {
1061 adev->doorbell.base = 0;
1062 adev->doorbell.size = 0;
1063 adev->doorbell.num_kernel_doorbells = 0;
1064 adev->doorbell.ptr = NULL;
1068 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
1071 amdgpu_asic_init_doorbell_index(adev);
1073 /* doorbell bar mapping */
1074 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
1075 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
1077 if (adev->enable_mes) {
1078 adev->doorbell.num_kernel_doorbells =
1079 adev->doorbell.size / sizeof(u32);
1081 adev->doorbell.num_kernel_doorbells =
1082 min_t(u32, adev->doorbell.size / sizeof(u32),
1083 adev->doorbell_index.max_assignment+1);
1084 if (adev->doorbell.num_kernel_doorbells == 0)
1087 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
1088 * paging queue doorbell use the second page. The
1089 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
1090 * doorbells are in the first page. So with paging queue enabled,
1091 * the max num_kernel_doorbells should + 1 page (0x400 in dword)
1093 if (adev->asic_type >= CHIP_VEGA10)
1094 adev->doorbell.num_kernel_doorbells += 0x400;
1097 adev->doorbell.ptr = ioremap(adev->doorbell.base,
1098 adev->doorbell.num_kernel_doorbells *
1100 if (adev->doorbell.ptr == NULL)
1107 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
1109 * @adev: amdgpu_device pointer
1111 * Tear down doorbell driver information (CIK)
1113 static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
1115 iounmap(adev->doorbell.ptr);
1116 adev->doorbell.ptr = NULL;
1122 * amdgpu_device_wb_*()
1123 * Writeback is the method by which the GPU updates special pages in memory
1124 * with the status of certain GPU events (fences, ring pointers,etc.).
1128 * amdgpu_device_wb_fini - Disable Writeback and free memory
1130 * @adev: amdgpu_device pointer
1132 * Disables Writeback and frees the Writeback memory (all asics).
1133 * Used at driver shutdown.
1135 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1137 if (adev->wb.wb_obj) {
1138 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1140 (void **)&adev->wb.wb);
1141 adev->wb.wb_obj = NULL;
1146 * amdgpu_device_wb_init - Init Writeback driver info and allocate memory
1148 * @adev: amdgpu_device pointer
1150 * Initializes writeback and allocates writeback memory (all asics).
1151 * Used at driver startup.
1152 * Returns 0 on success or an -error on failure.
1154 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1158 if (adev->wb.wb_obj == NULL) {
1159 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1160 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1161 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1162 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1163 (void **)&adev->wb.wb);
1165 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1169 adev->wb.num_wb = AMDGPU_MAX_WB;
1170 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1172 /* clear wb memory */
1173 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1180 * amdgpu_device_wb_get - Allocate a wb entry
1182 * @adev: amdgpu_device pointer
1185 * Allocate a wb slot for use by the driver (all asics).
1186 * Returns 0 on success or -EINVAL on failure.
1188 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1190 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1192 if (offset < adev->wb.num_wb) {
1193 __set_bit(offset, adev->wb.used);
1194 *wb = offset << 3; /* convert to dw offset */
1202 * amdgpu_device_wb_free - Free a wb entry
1204 * @adev: amdgpu_device pointer
1207 * Free a wb slot allocated for use by the driver (all asics)
1209 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1212 if (wb < adev->wb.num_wb)
1213 __clear_bit(wb, adev->wb.used);
1217 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1219 * @adev: amdgpu_device pointer
1221 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1222 * to fail, but if any of the BARs is not accessible after the size we abort
1223 * driver loading by returning -ENODEV.
1225 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1227 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1228 struct pci_bus *root;
1229 struct resource *res;
1235 if (amdgpu_sriov_vf(adev))
1238 /* skip if the bios has already enabled large BAR */
1239 if (adev->gmc.real_vram_size &&
1240 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1243 /* Check if the root BUS has 64bit memory resources */
1244 root = adev->pdev->bus;
1245 while (root->parent)
1246 root = root->parent;
1248 pci_bus_for_each_resource(root, res, i) {
1249 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1250 res->start > 0x100000000ull)
1254 /* Trying to resize is pointless without a root hub window above 4GB */
1258 /* Limit the BAR size to what is available */
1259 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1262 /* Disable memory decoding while we change the BAR addresses and size */
1263 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1264 pci_write_config_word(adev->pdev, PCI_COMMAND,
1265 cmd & ~PCI_COMMAND_MEMORY);
1267 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1268 amdgpu_device_doorbell_fini(adev);
1269 if (adev->asic_type >= CHIP_BONAIRE)
1270 pci_release_resource(adev->pdev, 2);
1272 pci_release_resource(adev->pdev, 0);
1274 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1276 DRM_INFO("Not enough PCI address space for a large BAR.");
1277 else if (r && r != -ENOTSUPP)
1278 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1280 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1282 /* When the doorbell or fb BAR isn't available we have no chance of
1285 r = amdgpu_device_doorbell_init(adev);
1286 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1289 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1295 * GPU helpers function.
1298 * amdgpu_device_need_post - check if the hw need post or not
1300 * @adev: amdgpu_device pointer
1302 * Check if the asic has been initialized (all asics) at driver startup
1303 * or post is needed if hw reset is performed.
1304 * Returns true if need or false if not.
1306 bool amdgpu_device_need_post(struct amdgpu_device *adev)
1310 if (amdgpu_sriov_vf(adev))
1313 if (amdgpu_passthrough(adev)) {
1314 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1315 * some old smc fw still need driver do vPost otherwise gpu hang, while
1316 * those smc fw version above 22.15 doesn't have this flaw, so we force
1317 * vpost executed for smc version below 22.15
1319 if (adev->asic_type == CHIP_FIJI) {
1322 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1323 /* force vPost if error occured */
1327 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1328 if (fw_ver < 0x00160e00)
1333 /* Don't post if we need to reset whole hive on init */
1334 if (adev->gmc.xgmi.pending_reset)
1337 if (adev->has_hw_reset) {
1338 adev->has_hw_reset = false;
1342 /* bios scratch used on CIK+ */
1343 if (adev->asic_type >= CHIP_BONAIRE)
1344 return amdgpu_atombios_scratch_need_asic_init(adev);
1346 /* check MEM_SIZE for older asics */
1347 reg = amdgpu_asic_get_config_memsize(adev);
1349 if ((reg != 0) && (reg != 0xffffffff))
1356 * amdgpu_device_should_use_aspm - check if the device should program ASPM
1358 * @adev: amdgpu_device pointer
1360 * Confirm whether the module parameter and pcie bridge agree that ASPM should
1361 * be set for this device.
1363 * Returns true if it should be used or false if not.
1365 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
1367 switch (amdgpu_aspm) {
1377 return pcie_aspm_enabled(adev->pdev);
1380 bool amdgpu_device_aspm_support_quirk(void)
1382 #if IS_ENABLED(CONFIG_X86)
1383 struct cpuinfo_x86 *c = &cpu_data(0);
1385 return !(c->x86 == 6 && c->x86_model == INTEL_FAM6_ALDERLAKE);
1391 /* if we get transitioned to only one device, take VGA back */
1393 * amdgpu_device_vga_set_decode - enable/disable vga decode
1395 * @pdev: PCI device pointer
1396 * @state: enable/disable vga decode
1398 * Enable/disable vga decode (all asics).
1399 * Returns VGA resource flags.
1401 static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev,
1404 struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev));
1405 amdgpu_asic_set_vga_state(adev, state);
1407 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1408 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1410 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1414 * amdgpu_device_check_block_size - validate the vm block size
1416 * @adev: amdgpu_device pointer
1418 * Validates the vm block size specified via module parameter.
1419 * The vm block size defines number of bits in page table versus page directory,
1420 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1421 * page table and the remaining bits are in the page directory.
1423 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1425 /* defines number of bits in page table versus page directory,
1426 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1427 * page table and the remaining bits are in the page directory */
1428 if (amdgpu_vm_block_size == -1)
1431 if (amdgpu_vm_block_size < 9) {
1432 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1433 amdgpu_vm_block_size);
1434 amdgpu_vm_block_size = -1;
1439 * amdgpu_device_check_vm_size - validate the vm size
1441 * @adev: amdgpu_device pointer
1443 * Validates the vm size in GB specified via module parameter.
1444 * The VM size is the size of the GPU virtual memory space in GB.
1446 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1448 /* no need to check the default value */
1449 if (amdgpu_vm_size == -1)
1452 if (amdgpu_vm_size < 1) {
1453 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1455 amdgpu_vm_size = -1;
1459 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1462 bool is_os_64 = (sizeof(void *) == 8);
1463 uint64_t total_memory;
1464 uint64_t dram_size_seven_GB = 0x1B8000000;
1465 uint64_t dram_size_three_GB = 0xB8000000;
1467 if (amdgpu_smu_memory_pool_size == 0)
1471 DRM_WARN("Not 64-bit OS, feature not supported\n");
1475 total_memory = (uint64_t)si.totalram * si.mem_unit;
1477 if ((amdgpu_smu_memory_pool_size == 1) ||
1478 (amdgpu_smu_memory_pool_size == 2)) {
1479 if (total_memory < dram_size_three_GB)
1481 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1482 (amdgpu_smu_memory_pool_size == 8)) {
1483 if (total_memory < dram_size_seven_GB)
1486 DRM_WARN("Smu memory pool size not supported\n");
1489 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1494 DRM_WARN("No enough system memory\n");
1496 adev->pm.smu_prv_buffer_size = 0;
1499 static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)
1501 if (!(adev->flags & AMD_IS_APU) ||
1502 adev->asic_type < CHIP_RAVEN)
1505 switch (adev->asic_type) {
1507 if (adev->pdev->device == 0x15dd)
1508 adev->apu_flags |= AMD_APU_IS_RAVEN;
1509 if (adev->pdev->device == 0x15d8)
1510 adev->apu_flags |= AMD_APU_IS_PICASSO;
1513 if ((adev->pdev->device == 0x1636) ||
1514 (adev->pdev->device == 0x164c))
1515 adev->apu_flags |= AMD_APU_IS_RENOIR;
1517 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1520 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1522 case CHIP_YELLOW_CARP:
1524 case CHIP_CYAN_SKILLFISH:
1525 if ((adev->pdev->device == 0x13FE) ||
1526 (adev->pdev->device == 0x143F))
1527 adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2;
1537 * amdgpu_device_check_arguments - validate module params
1539 * @adev: amdgpu_device pointer
1541 * Validates certain module parameters and updates
1542 * the associated values used by the driver (all asics).
1544 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1546 if (amdgpu_sched_jobs < 4) {
1547 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1549 amdgpu_sched_jobs = 4;
1550 } else if (!is_power_of_2(amdgpu_sched_jobs)) {
1551 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1553 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1556 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1557 /* gart size must be greater or equal to 32M */
1558 dev_warn(adev->dev, "gart size (%d) too small\n",
1560 amdgpu_gart_size = -1;
1563 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1564 /* gtt size must be greater or equal to 32M */
1565 dev_warn(adev->dev, "gtt size (%d) too small\n",
1567 amdgpu_gtt_size = -1;
1570 /* valid range is between 4 and 9 inclusive */
1571 if (amdgpu_vm_fragment_size != -1 &&
1572 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1573 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1574 amdgpu_vm_fragment_size = -1;
1577 if (amdgpu_sched_hw_submission < 2) {
1578 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1579 amdgpu_sched_hw_submission);
1580 amdgpu_sched_hw_submission = 2;
1581 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1582 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1583 amdgpu_sched_hw_submission);
1584 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1587 if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) {
1588 dev_warn(adev->dev, "invalid option for reset method, reverting to default\n");
1589 amdgpu_reset_method = -1;
1592 amdgpu_device_check_smu_prv_buffer_size(adev);
1594 amdgpu_device_check_vm_size(adev);
1596 amdgpu_device_check_block_size(adev);
1598 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1604 * amdgpu_switcheroo_set_state - set switcheroo state
1606 * @pdev: pci dev pointer
1607 * @state: vga_switcheroo state
1609 * Callback for the switcheroo driver. Suspends or resumes
1610 * the asics before or after it is powered up using ACPI methods.
1612 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1613 enum vga_switcheroo_state state)
1615 struct drm_device *dev = pci_get_drvdata(pdev);
1618 if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF)
1621 if (state == VGA_SWITCHEROO_ON) {
1622 pr_info("switched on\n");
1623 /* don't suspend or resume card normally */
1624 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1626 pci_set_power_state(pdev, PCI_D0);
1627 amdgpu_device_load_pci_state(pdev);
1628 r = pci_enable_device(pdev);
1630 DRM_WARN("pci_enable_device failed (%d)\n", r);
1631 amdgpu_device_resume(dev, true);
1633 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1635 pr_info("switched off\n");
1636 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1637 amdgpu_device_suspend(dev, true);
1638 amdgpu_device_cache_pci_state(pdev);
1639 /* Shut down the device */
1640 pci_disable_device(pdev);
1641 pci_set_power_state(pdev, PCI_D3cold);
1642 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1647 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1649 * @pdev: pci dev pointer
1651 * Callback for the switcheroo driver. Check of the switcheroo
1652 * state can be changed.
1653 * Returns true if the state can be changed, false if not.
1655 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1657 struct drm_device *dev = pci_get_drvdata(pdev);
1660 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1661 * locking inversion with the driver load path. And the access here is
1662 * completely racy anyway. So don't bother with locking for now.
1664 return atomic_read(&dev->open_count) == 0;
1667 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1668 .set_gpu_state = amdgpu_switcheroo_set_state,
1670 .can_switch = amdgpu_switcheroo_can_switch,
1674 * amdgpu_device_ip_set_clockgating_state - set the CG state
1676 * @dev: amdgpu_device pointer
1677 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1678 * @state: clockgating state (gate or ungate)
1680 * Sets the requested clockgating state for all instances of
1681 * the hardware IP specified.
1682 * Returns the error code from the last instance.
1684 int amdgpu_device_ip_set_clockgating_state(void *dev,
1685 enum amd_ip_block_type block_type,
1686 enum amd_clockgating_state state)
1688 struct amdgpu_device *adev = dev;
1691 for (i = 0; i < adev->num_ip_blocks; i++) {
1692 if (!adev->ip_blocks[i].status.valid)
1694 if (adev->ip_blocks[i].version->type != block_type)
1696 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1698 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1699 (void *)adev, state);
1701 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1702 adev->ip_blocks[i].version->funcs->name, r);
1708 * amdgpu_device_ip_set_powergating_state - set the PG state
1710 * @dev: amdgpu_device pointer
1711 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1712 * @state: powergating state (gate or ungate)
1714 * Sets the requested powergating state for all instances of
1715 * the hardware IP specified.
1716 * Returns the error code from the last instance.
1718 int amdgpu_device_ip_set_powergating_state(void *dev,
1719 enum amd_ip_block_type block_type,
1720 enum amd_powergating_state state)
1722 struct amdgpu_device *adev = dev;
1725 for (i = 0; i < adev->num_ip_blocks; i++) {
1726 if (!adev->ip_blocks[i].status.valid)
1728 if (adev->ip_blocks[i].version->type != block_type)
1730 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1732 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1733 (void *)adev, state);
1735 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1736 adev->ip_blocks[i].version->funcs->name, r);
1742 * amdgpu_device_ip_get_clockgating_state - get the CG state
1744 * @adev: amdgpu_device pointer
1745 * @flags: clockgating feature flags
1747 * Walks the list of IPs on the device and updates the clockgating
1748 * flags for each IP.
1749 * Updates @flags with the feature flags for each hardware IP where
1750 * clockgating is enabled.
1752 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1757 for (i = 0; i < adev->num_ip_blocks; i++) {
1758 if (!adev->ip_blocks[i].status.valid)
1760 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1761 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1766 * amdgpu_device_ip_wait_for_idle - wait for idle
1768 * @adev: amdgpu_device pointer
1769 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1771 * Waits for the request hardware IP to be idle.
1772 * Returns 0 for success or a negative error code on failure.
1774 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1775 enum amd_ip_block_type block_type)
1779 for (i = 0; i < adev->num_ip_blocks; i++) {
1780 if (!adev->ip_blocks[i].status.valid)
1782 if (adev->ip_blocks[i].version->type == block_type) {
1783 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1794 * amdgpu_device_ip_is_idle - is the hardware IP idle
1796 * @adev: amdgpu_device pointer
1797 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1799 * Check if the hardware IP is idle or not.
1800 * Returns true if it the IP is idle, false if not.
1802 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1803 enum amd_ip_block_type block_type)
1807 for (i = 0; i < adev->num_ip_blocks; i++) {
1808 if (!adev->ip_blocks[i].status.valid)
1810 if (adev->ip_blocks[i].version->type == block_type)
1811 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1818 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1820 * @adev: amdgpu_device pointer
1821 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1823 * Returns a pointer to the hardware IP block structure
1824 * if it exists for the asic, otherwise NULL.
1826 struct amdgpu_ip_block *
1827 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1828 enum amd_ip_block_type type)
1832 for (i = 0; i < adev->num_ip_blocks; i++)
1833 if (adev->ip_blocks[i].version->type == type)
1834 return &adev->ip_blocks[i];
1840 * amdgpu_device_ip_block_version_cmp
1842 * @adev: amdgpu_device pointer
1843 * @type: enum amd_ip_block_type
1844 * @major: major version
1845 * @minor: minor version
1847 * return 0 if equal or greater
1848 * return 1 if smaller or the ip_block doesn't exist
1850 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1851 enum amd_ip_block_type type,
1852 u32 major, u32 minor)
1854 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1856 if (ip_block && ((ip_block->version->major > major) ||
1857 ((ip_block->version->major == major) &&
1858 (ip_block->version->minor >= minor))))
1865 * amdgpu_device_ip_block_add
1867 * @adev: amdgpu_device pointer
1868 * @ip_block_version: pointer to the IP to add
1870 * Adds the IP block driver information to the collection of IPs
1873 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1874 const struct amdgpu_ip_block_version *ip_block_version)
1876 if (!ip_block_version)
1879 switch (ip_block_version->type) {
1880 case AMD_IP_BLOCK_TYPE_VCN:
1881 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1884 case AMD_IP_BLOCK_TYPE_JPEG:
1885 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
1892 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1893 ip_block_version->funcs->name);
1895 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1901 * amdgpu_device_enable_virtual_display - enable virtual display feature
1903 * @adev: amdgpu_device pointer
1905 * Enabled the virtual display feature if the user has enabled it via
1906 * the module parameter virtual_display. This feature provides a virtual
1907 * display hardware on headless boards or in virtualized environments.
1908 * This function parses and validates the configuration string specified by
1909 * the user and configues the virtual display configuration (number of
1910 * virtual connectors, crtcs, etc.) specified.
1912 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1914 adev->enable_virtual_display = false;
1916 if (amdgpu_virtual_display) {
1917 const char *pci_address_name = pci_name(adev->pdev);
1918 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1920 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1921 pciaddstr_tmp = pciaddstr;
1922 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1923 pciaddname = strsep(&pciaddname_tmp, ",");
1924 if (!strcmp("all", pciaddname)
1925 || !strcmp(pci_address_name, pciaddname)) {
1929 adev->enable_virtual_display = true;
1932 res = kstrtol(pciaddname_tmp, 10,
1940 adev->mode_info.num_crtc = num_crtc;
1942 adev->mode_info.num_crtc = 1;
1948 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1949 amdgpu_virtual_display, pci_address_name,
1950 adev->enable_virtual_display, adev->mode_info.num_crtc);
1956 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)
1958 if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {
1959 adev->mode_info.num_crtc = 1;
1960 adev->enable_virtual_display = true;
1961 DRM_INFO("virtual_display:%d, num_crtc:%d\n",
1962 adev->enable_virtual_display, adev->mode_info.num_crtc);
1967 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1969 * @adev: amdgpu_device pointer
1971 * Parses the asic configuration parameters specified in the gpu info
1972 * firmware and makes them availale to the driver for use in configuring
1974 * Returns 0 on success, -EINVAL on failure.
1976 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1978 const char *chip_name;
1981 const struct gpu_info_firmware_header_v1_0 *hdr;
1983 adev->firmware.gpu_info_fw = NULL;
1985 if (adev->mman.discovery_bin) {
1987 * FIXME: The bounding box is still needed by Navi12, so
1988 * temporarily read it from gpu_info firmware. Should be dropped
1989 * when DAL no longer needs it.
1991 if (adev->asic_type != CHIP_NAVI12)
1995 switch (adev->asic_type) {
1999 chip_name = "vega10";
2002 chip_name = "vega12";
2005 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
2006 chip_name = "raven2";
2007 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
2008 chip_name = "picasso";
2010 chip_name = "raven";
2013 chip_name = "arcturus";
2016 chip_name = "navi12";
2020 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
2021 err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw, fw_name);
2024 "Failed to get gpu_info firmware \"%s\"\n",
2029 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
2030 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
2032 switch (hdr->version_major) {
2035 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
2036 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
2037 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2040 * Should be droped when DAL no longer needs it.
2042 if (adev->asic_type == CHIP_NAVI12)
2043 goto parse_soc_bounding_box;
2045 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
2046 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
2047 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
2048 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
2049 adev->gfx.config.max_texture_channel_caches =
2050 le32_to_cpu(gpu_info_fw->gc_num_tccs);
2051 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
2052 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
2053 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
2054 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
2055 adev->gfx.config.double_offchip_lds_buf =
2056 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
2057 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
2058 adev->gfx.cu_info.max_waves_per_simd =
2059 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
2060 adev->gfx.cu_info.max_scratch_slots_per_cu =
2061 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
2062 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
2063 if (hdr->version_minor >= 1) {
2064 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
2065 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
2066 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2067 adev->gfx.config.num_sc_per_sh =
2068 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
2069 adev->gfx.config.num_packer_per_sc =
2070 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
2073 parse_soc_bounding_box:
2075 * soc bounding box info is not integrated in disocovery table,
2076 * we always need to parse it from gpu info firmware if needed.
2078 if (hdr->version_minor == 2) {
2079 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
2080 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
2081 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2082 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
2088 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
2097 * amdgpu_device_ip_early_init - run early init for hardware IPs
2099 * @adev: amdgpu_device pointer
2101 * Early initialization pass for hardware IPs. The hardware IPs that make
2102 * up each asic are discovered each IP's early_init callback is run. This
2103 * is the first stage in initializing the asic.
2104 * Returns 0 on success, negative error code on failure.
2106 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
2108 struct drm_device *dev = adev_to_drm(adev);
2109 struct pci_dev *parent;
2113 amdgpu_device_enable_virtual_display(adev);
2115 if (amdgpu_sriov_vf(adev)) {
2116 r = amdgpu_virt_request_full_gpu(adev, true);
2121 switch (adev->asic_type) {
2122 #ifdef CONFIG_DRM_AMDGPU_SI
2128 adev->family = AMDGPU_FAMILY_SI;
2129 r = si_set_ip_blocks(adev);
2134 #ifdef CONFIG_DRM_AMDGPU_CIK
2140 if (adev->flags & AMD_IS_APU)
2141 adev->family = AMDGPU_FAMILY_KV;
2143 adev->family = AMDGPU_FAMILY_CI;
2145 r = cik_set_ip_blocks(adev);
2153 case CHIP_POLARIS10:
2154 case CHIP_POLARIS11:
2155 case CHIP_POLARIS12:
2159 if (adev->flags & AMD_IS_APU)
2160 adev->family = AMDGPU_FAMILY_CZ;
2162 adev->family = AMDGPU_FAMILY_VI;
2164 r = vi_set_ip_blocks(adev);
2169 r = amdgpu_discovery_set_ip_blocks(adev);
2175 if (amdgpu_has_atpx() &&
2176 (amdgpu_is_atpx_hybrid() ||
2177 amdgpu_has_atpx_dgpu_power_cntl()) &&
2178 ((adev->flags & AMD_IS_APU) == 0) &&
2179 !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
2180 adev->flags |= AMD_IS_PX;
2182 if (!(adev->flags & AMD_IS_APU)) {
2183 parent = pci_upstream_bridge(adev->pdev);
2184 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2188 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2189 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2190 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2191 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2192 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2195 for (i = 0; i < adev->num_ip_blocks; i++) {
2196 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2197 DRM_ERROR("disabled ip block: %d <%s>\n",
2198 i, adev->ip_blocks[i].version->funcs->name);
2199 adev->ip_blocks[i].status.valid = false;
2201 if (adev->ip_blocks[i].version->funcs->early_init) {
2202 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2204 adev->ip_blocks[i].status.valid = false;
2206 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2207 adev->ip_blocks[i].version->funcs->name, r);
2210 adev->ip_blocks[i].status.valid = true;
2213 adev->ip_blocks[i].status.valid = true;
2216 /* get the vbios after the asic_funcs are set up */
2217 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2218 r = amdgpu_device_parse_gpu_info_fw(adev);
2223 if (!amdgpu_get_bios(adev))
2226 r = amdgpu_atombios_init(adev);
2228 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2229 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2233 /*get pf2vf msg info at it's earliest time*/
2234 if (amdgpu_sriov_vf(adev))
2235 amdgpu_virt_init_data_exchange(adev);
2242 amdgpu_amdkfd_device_probe(adev);
2243 adev->cg_flags &= amdgpu_cg_mask;
2244 adev->pg_flags &= amdgpu_pg_mask;
2249 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2253 for (i = 0; i < adev->num_ip_blocks; i++) {
2254 if (!adev->ip_blocks[i].status.sw)
2256 if (adev->ip_blocks[i].status.hw)
2258 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2259 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2260 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2261 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2263 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2264 adev->ip_blocks[i].version->funcs->name, r);
2267 adev->ip_blocks[i].status.hw = true;
2274 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2278 for (i = 0; i < adev->num_ip_blocks; i++) {
2279 if (!adev->ip_blocks[i].status.sw)
2281 if (adev->ip_blocks[i].status.hw)
2283 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2285 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2286 adev->ip_blocks[i].version->funcs->name, r);
2289 adev->ip_blocks[i].status.hw = true;
2295 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2299 uint32_t smu_version;
2301 if (adev->asic_type >= CHIP_VEGA10) {
2302 for (i = 0; i < adev->num_ip_blocks; i++) {
2303 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2306 if (!adev->ip_blocks[i].status.sw)
2309 /* no need to do the fw loading again if already done*/
2310 if (adev->ip_blocks[i].status.hw == true)
2313 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2314 r = adev->ip_blocks[i].version->funcs->resume(adev);
2316 DRM_ERROR("resume of IP block <%s> failed %d\n",
2317 adev->ip_blocks[i].version->funcs->name, r);
2321 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2323 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2324 adev->ip_blocks[i].version->funcs->name, r);
2329 adev->ip_blocks[i].status.hw = true;
2334 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2335 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2340 static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
2345 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2346 struct amdgpu_ring *ring = adev->rings[i];
2348 /* No need to setup the GPU scheduler for rings that don't need it */
2349 if (!ring || ring->no_scheduler)
2352 switch (ring->funcs->type) {
2353 case AMDGPU_RING_TYPE_GFX:
2354 timeout = adev->gfx_timeout;
2356 case AMDGPU_RING_TYPE_COMPUTE:
2357 timeout = adev->compute_timeout;
2359 case AMDGPU_RING_TYPE_SDMA:
2360 timeout = adev->sdma_timeout;
2363 timeout = adev->video_timeout;
2367 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
2368 ring->num_hw_submission, 0,
2369 timeout, adev->reset_domain->wq,
2370 ring->sched_score, ring->name,
2373 DRM_ERROR("Failed to create scheduler on ring %s.\n",
2384 * amdgpu_device_ip_init - run init for hardware IPs
2386 * @adev: amdgpu_device pointer
2388 * Main initialization pass for hardware IPs. The list of all the hardware
2389 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2390 * are run. sw_init initializes the software state associated with each IP
2391 * and hw_init initializes the hardware associated with each IP.
2392 * Returns 0 on success, negative error code on failure.
2394 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2398 r = amdgpu_ras_init(adev);
2402 for (i = 0; i < adev->num_ip_blocks; i++) {
2403 if (!adev->ip_blocks[i].status.valid)
2405 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2407 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2408 adev->ip_blocks[i].version->funcs->name, r);
2411 adev->ip_blocks[i].status.sw = true;
2413 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2414 /* need to do common hw init early so everything is set up for gmc */
2415 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2417 DRM_ERROR("hw_init %d failed %d\n", i, r);
2420 adev->ip_blocks[i].status.hw = true;
2421 } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2422 /* need to do gmc hw init early so we can allocate gpu mem */
2423 /* Try to reserve bad pages early */
2424 if (amdgpu_sriov_vf(adev))
2425 amdgpu_virt_exchange_data(adev);
2427 r = amdgpu_device_mem_scratch_init(adev);
2429 DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);
2432 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2434 DRM_ERROR("hw_init %d failed %d\n", i, r);
2437 r = amdgpu_device_wb_init(adev);
2439 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2442 adev->ip_blocks[i].status.hw = true;
2444 /* right after GMC hw init, we create CSA */
2446 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2447 AMDGPU_GEM_DOMAIN_VRAM |
2448 AMDGPU_GEM_DOMAIN_GTT,
2451 DRM_ERROR("allocate CSA failed %d\n", r);
2458 if (amdgpu_sriov_vf(adev))
2459 amdgpu_virt_init_data_exchange(adev);
2461 r = amdgpu_ib_pool_init(adev);
2463 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2464 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2468 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2472 r = amdgpu_device_ip_hw_init_phase1(adev);
2476 r = amdgpu_device_fw_loading(adev);
2480 r = amdgpu_device_ip_hw_init_phase2(adev);
2485 * retired pages will be loaded from eeprom and reserved here,
2486 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2487 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2488 * for I2C communication which only true at this point.
2490 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2491 * failure from bad gpu situation and stop amdgpu init process
2492 * accordingly. For other failed cases, it will still release all
2493 * the resource and print error message, rather than returning one
2494 * negative value to upper level.
2496 * Note: theoretically, this should be called before all vram allocations
2497 * to protect retired page from abusing
2499 r = amdgpu_ras_recovery_init(adev);
2504 * In case of XGMI grab extra reference for reset domain for this device
2506 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2507 if (amdgpu_xgmi_add_device(adev) == 0) {
2508 if (!amdgpu_sriov_vf(adev)) {
2509 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2511 if (WARN_ON(!hive)) {
2516 if (!hive->reset_domain ||
2517 !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
2519 amdgpu_put_xgmi_hive(hive);
2523 /* Drop the early temporary reset domain we created for device */
2524 amdgpu_reset_put_reset_domain(adev->reset_domain);
2525 adev->reset_domain = hive->reset_domain;
2526 amdgpu_put_xgmi_hive(hive);
2531 r = amdgpu_device_init_schedulers(adev);
2535 /* Don't init kfd if whole hive need to be reset during init */
2536 if (!adev->gmc.xgmi.pending_reset)
2537 amdgpu_amdkfd_device_init(adev);
2539 amdgpu_fru_get_product_info(adev);
2547 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2549 * @adev: amdgpu_device pointer
2551 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2552 * this function before a GPU reset. If the value is retained after a
2553 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2555 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2557 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2561 * amdgpu_device_check_vram_lost - check if vram is valid
2563 * @adev: amdgpu_device pointer
2565 * Checks the reset magic value written to the gart pointer in VRAM.
2566 * The driver calls this after a GPU reset to see if the contents of
2567 * VRAM is lost or now.
2568 * returns true if vram is lost, false if not.
2570 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2572 if (memcmp(adev->gart.ptr, adev->reset_magic,
2573 AMDGPU_RESET_MAGIC_NUM))
2576 if (!amdgpu_in_reset(adev))
2580 * For all ASICs with baco/mode1 reset, the VRAM is
2581 * always assumed to be lost.
2583 switch (amdgpu_asic_reset_method(adev)) {
2584 case AMD_RESET_METHOD_BACO:
2585 case AMD_RESET_METHOD_MODE1:
2593 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2595 * @adev: amdgpu_device pointer
2596 * @state: clockgating state (gate or ungate)
2598 * The list of all the hardware IPs that make up the asic is walked and the
2599 * set_clockgating_state callbacks are run.
2600 * Late initialization pass enabling clockgating for hardware IPs.
2601 * Fini or suspend, pass disabling clockgating for hardware IPs.
2602 * Returns 0 on success, negative error code on failure.
2605 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2606 enum amd_clockgating_state state)
2610 if (amdgpu_emu_mode == 1)
2613 for (j = 0; j < adev->num_ip_blocks; j++) {
2614 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2615 if (!adev->ip_blocks[i].status.late_initialized)
2617 /* skip CG for GFX, SDMA on S0ix */
2618 if (adev->in_s0ix &&
2619 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2620 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2622 /* skip CG for VCE/UVD, it's handled specially */
2623 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2624 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2625 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2626 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2627 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2628 /* enable clockgating to save power */
2629 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2632 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2633 adev->ip_blocks[i].version->funcs->name, r);
2642 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
2643 enum amd_powergating_state state)
2647 if (amdgpu_emu_mode == 1)
2650 for (j = 0; j < adev->num_ip_blocks; j++) {
2651 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2652 if (!adev->ip_blocks[i].status.late_initialized)
2654 /* skip PG for GFX, SDMA on S0ix */
2655 if (adev->in_s0ix &&
2656 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2657 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2659 /* skip CG for VCE/UVD, it's handled specially */
2660 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2661 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2662 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2663 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2664 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2665 /* enable powergating to save power */
2666 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2669 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2670 adev->ip_blocks[i].version->funcs->name, r);
2678 static int amdgpu_device_enable_mgpu_fan_boost(void)
2680 struct amdgpu_gpu_instance *gpu_ins;
2681 struct amdgpu_device *adev;
2684 mutex_lock(&mgpu_info.mutex);
2687 * MGPU fan boost feature should be enabled
2688 * only when there are two or more dGPUs in
2691 if (mgpu_info.num_dgpu < 2)
2694 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2695 gpu_ins = &(mgpu_info.gpu_ins[i]);
2696 adev = gpu_ins->adev;
2697 if (!(adev->flags & AMD_IS_APU) &&
2698 !gpu_ins->mgpu_fan_enabled) {
2699 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2703 gpu_ins->mgpu_fan_enabled = 1;
2708 mutex_unlock(&mgpu_info.mutex);
2714 * amdgpu_device_ip_late_init - run late init for hardware IPs
2716 * @adev: amdgpu_device pointer
2718 * Late initialization pass for hardware IPs. The list of all the hardware
2719 * IPs that make up the asic is walked and the late_init callbacks are run.
2720 * late_init covers any special initialization that an IP requires
2721 * after all of the have been initialized or something that needs to happen
2722 * late in the init process.
2723 * Returns 0 on success, negative error code on failure.
2725 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2727 struct amdgpu_gpu_instance *gpu_instance;
2730 for (i = 0; i < adev->num_ip_blocks; i++) {
2731 if (!adev->ip_blocks[i].status.hw)
2733 if (adev->ip_blocks[i].version->funcs->late_init) {
2734 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2736 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2737 adev->ip_blocks[i].version->funcs->name, r);
2741 adev->ip_blocks[i].status.late_initialized = true;
2744 r = amdgpu_ras_late_init(adev);
2746 DRM_ERROR("amdgpu_ras_late_init failed %d", r);
2750 amdgpu_ras_set_error_query_ready(adev, true);
2752 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2753 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2755 amdgpu_device_fill_reset_magic(adev);
2757 r = amdgpu_device_enable_mgpu_fan_boost();
2759 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2761 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
2762 if (amdgpu_passthrough(adev) &&
2763 ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1) ||
2764 adev->asic_type == CHIP_ALDEBARAN))
2765 amdgpu_dpm_handle_passthrough_sbr(adev, true);
2767 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2768 mutex_lock(&mgpu_info.mutex);
2771 * Reset device p-state to low as this was booted with high.
2773 * This should be performed only after all devices from the same
2774 * hive get initialized.
2776 * However, it's unknown how many device in the hive in advance.
2777 * As this is counted one by one during devices initializations.
2779 * So, we wait for all XGMI interlinked devices initialized.
2780 * This may bring some delays as those devices may come from
2781 * different hives. But that should be OK.
2783 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2784 for (i = 0; i < mgpu_info.num_gpu; i++) {
2785 gpu_instance = &(mgpu_info.gpu_ins[i]);
2786 if (gpu_instance->adev->flags & AMD_IS_APU)
2789 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
2790 AMDGPU_XGMI_PSTATE_MIN);
2792 DRM_ERROR("pstate setting failed (%d).\n", r);
2798 mutex_unlock(&mgpu_info.mutex);
2805 * amdgpu_device_smu_fini_early - smu hw_fini wrapper
2807 * @adev: amdgpu_device pointer
2809 * For ASICs need to disable SMC first
2811 static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)
2815 if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
2818 for (i = 0; i < adev->num_ip_blocks; i++) {
2819 if (!adev->ip_blocks[i].status.hw)
2821 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2822 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2823 /* XXX handle errors */
2825 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2826 adev->ip_blocks[i].version->funcs->name, r);
2828 adev->ip_blocks[i].status.hw = false;
2834 static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
2838 for (i = 0; i < adev->num_ip_blocks; i++) {
2839 if (!adev->ip_blocks[i].version->funcs->early_fini)
2842 r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev);
2844 DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
2845 adev->ip_blocks[i].version->funcs->name, r);
2849 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2850 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2852 amdgpu_amdkfd_suspend(adev, false);
2854 /* Workaroud for ASICs need to disable SMC first */
2855 amdgpu_device_smu_fini_early(adev);
2857 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2858 if (!adev->ip_blocks[i].status.hw)
2861 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2862 /* XXX handle errors */
2864 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2865 adev->ip_blocks[i].version->funcs->name, r);
2868 adev->ip_blocks[i].status.hw = false;
2871 if (amdgpu_sriov_vf(adev)) {
2872 if (amdgpu_virt_release_full_gpu(adev, false))
2873 DRM_ERROR("failed to release exclusive mode on fini\n");
2880 * amdgpu_device_ip_fini - run fini for hardware IPs
2882 * @adev: amdgpu_device pointer
2884 * Main teardown pass for hardware IPs. The list of all the hardware
2885 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2886 * are run. hw_fini tears down the hardware associated with each IP
2887 * and sw_fini tears down any software state associated with each IP.
2888 * Returns 0 on success, negative error code on failure.
2890 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2894 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
2895 amdgpu_virt_release_ras_err_handler_data(adev);
2897 if (adev->gmc.xgmi.num_physical_nodes > 1)
2898 amdgpu_xgmi_remove_device(adev);
2900 amdgpu_amdkfd_device_fini_sw(adev);
2902 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2903 if (!adev->ip_blocks[i].status.sw)
2906 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2907 amdgpu_ucode_free_bo(adev);
2908 amdgpu_free_static_csa(&adev->virt.csa_obj);
2909 amdgpu_device_wb_fini(adev);
2910 amdgpu_device_mem_scratch_fini(adev);
2911 amdgpu_ib_pool_fini(adev);
2914 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2915 /* XXX handle errors */
2917 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2918 adev->ip_blocks[i].version->funcs->name, r);
2920 adev->ip_blocks[i].status.sw = false;
2921 adev->ip_blocks[i].status.valid = false;
2924 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2925 if (!adev->ip_blocks[i].status.late_initialized)
2927 if (adev->ip_blocks[i].version->funcs->late_fini)
2928 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2929 adev->ip_blocks[i].status.late_initialized = false;
2932 amdgpu_ras_fini(adev);
2938 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2940 * @work: work_struct.
2942 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2944 struct amdgpu_device *adev =
2945 container_of(work, struct amdgpu_device, delayed_init_work.work);
2948 r = amdgpu_ib_ring_tests(adev);
2950 DRM_ERROR("ib ring test failed (%d).\n", r);
2953 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2955 struct amdgpu_device *adev =
2956 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2958 WARN_ON_ONCE(adev->gfx.gfx_off_state);
2959 WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
2961 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2962 adev->gfx.gfx_off_state = true;
2966 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2968 * @adev: amdgpu_device pointer
2970 * Main suspend function for hardware IPs. The list of all the hardware
2971 * IPs that make up the asic is walked, clockgating is disabled and the
2972 * suspend callbacks are run. suspend puts the hardware and software state
2973 * in each IP into a state suitable for suspend.
2974 * Returns 0 on success, negative error code on failure.
2976 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2980 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2981 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2984 * Per PMFW team's suggestion, driver needs to handle gfxoff
2985 * and df cstate features disablement for gpu reset(e.g. Mode1Reset)
2986 * scenario. Add the missing df cstate disablement here.
2988 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
2989 dev_warn(adev->dev, "Failed to disallow df cstate");
2991 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2992 if (!adev->ip_blocks[i].status.valid)
2995 /* displays are handled separately */
2996 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
2999 /* XXX handle errors */
3000 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3001 /* XXX handle errors */
3003 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3004 adev->ip_blocks[i].version->funcs->name, r);
3008 adev->ip_blocks[i].status.hw = false;
3015 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
3017 * @adev: amdgpu_device pointer
3019 * Main suspend function for hardware IPs. The list of all the hardware
3020 * IPs that make up the asic is walked, clockgating is disabled and the
3021 * suspend callbacks are run. suspend puts the hardware and software state
3022 * in each IP into a state suitable for suspend.
3023 * Returns 0 on success, negative error code on failure.
3025 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
3030 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);
3032 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3033 if (!adev->ip_blocks[i].status.valid)
3035 /* displays are handled in phase1 */
3036 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
3038 /* PSP lost connection when err_event_athub occurs */
3039 if (amdgpu_ras_intr_triggered() &&
3040 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3041 adev->ip_blocks[i].status.hw = false;
3045 /* skip unnecessary suspend if we do not initialize them yet */
3046 if (adev->gmc.xgmi.pending_reset &&
3047 !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3048 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC ||
3049 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3050 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) {
3051 adev->ip_blocks[i].status.hw = false;
3055 /* skip suspend of gfx/mes and psp for S0ix
3056 * gfx is in gfxoff state, so on resume it will exit gfxoff just
3057 * like at runtime. PSP is also part of the always on hardware
3058 * so no need to suspend it.
3060 if (adev->in_s0ix &&
3061 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
3062 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3063 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
3066 /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
3067 if (adev->in_s0ix &&
3068 (adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 0, 0)) &&
3069 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
3072 /* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot.
3073 * These are in TMR, hence are expected to be reused by PSP-TOS to reload
3074 * from this location and RLC Autoload automatically also gets loaded
3075 * from here based on PMFW -> PSP message during re-init sequence.
3076 * Therefore, the psp suspend & resume should be skipped to avoid destroy
3077 * the TMR and reload FWs again for IMU enabled APU ASICs.
3079 if (amdgpu_in_reset(adev) &&
3080 (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs &&
3081 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3084 /* XXX handle errors */
3085 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3086 /* XXX handle errors */
3088 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3089 adev->ip_blocks[i].version->funcs->name, r);
3091 adev->ip_blocks[i].status.hw = false;
3092 /* handle putting the SMC in the appropriate state */
3093 if (!amdgpu_sriov_vf(adev)) {
3094 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3095 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
3097 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
3098 adev->mp1_state, r);
3109 * amdgpu_device_ip_suspend - run suspend for hardware IPs
3111 * @adev: amdgpu_device pointer
3113 * Main suspend function for hardware IPs. The list of all the hardware
3114 * IPs that make up the asic is walked, clockgating is disabled and the
3115 * suspend callbacks are run. suspend puts the hardware and software state
3116 * in each IP into a state suitable for suspend.
3117 * Returns 0 on success, negative error code on failure.
3119 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
3123 if (amdgpu_sriov_vf(adev)) {
3124 amdgpu_virt_fini_data_exchange(adev);
3125 amdgpu_virt_request_full_gpu(adev, false);
3128 r = amdgpu_device_ip_suspend_phase1(adev);
3131 r = amdgpu_device_ip_suspend_phase2(adev);
3133 if (amdgpu_sriov_vf(adev))
3134 amdgpu_virt_release_full_gpu(adev, false);
3139 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
3143 static enum amd_ip_block_type ip_order[] = {
3144 AMD_IP_BLOCK_TYPE_COMMON,
3145 AMD_IP_BLOCK_TYPE_GMC,
3146 AMD_IP_BLOCK_TYPE_PSP,
3147 AMD_IP_BLOCK_TYPE_IH,
3150 for (i = 0; i < adev->num_ip_blocks; i++) {
3152 struct amdgpu_ip_block *block;
3154 block = &adev->ip_blocks[i];
3155 block->status.hw = false;
3157 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
3159 if (block->version->type != ip_order[j] ||
3160 !block->status.valid)
3163 r = block->version->funcs->hw_init(adev);
3164 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3167 block->status.hw = true;
3174 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
3178 static enum amd_ip_block_type ip_order[] = {
3179 AMD_IP_BLOCK_TYPE_SMC,
3180 AMD_IP_BLOCK_TYPE_DCE,
3181 AMD_IP_BLOCK_TYPE_GFX,
3182 AMD_IP_BLOCK_TYPE_SDMA,
3183 AMD_IP_BLOCK_TYPE_MES,
3184 AMD_IP_BLOCK_TYPE_UVD,
3185 AMD_IP_BLOCK_TYPE_VCE,
3186 AMD_IP_BLOCK_TYPE_VCN,
3187 AMD_IP_BLOCK_TYPE_JPEG
3190 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
3192 struct amdgpu_ip_block *block;
3194 for (j = 0; j < adev->num_ip_blocks; j++) {
3195 block = &adev->ip_blocks[j];
3197 if (block->version->type != ip_order[i] ||
3198 !block->status.valid ||
3202 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
3203 r = block->version->funcs->resume(adev);
3205 r = block->version->funcs->hw_init(adev);
3207 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3210 block->status.hw = true;
3218 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
3220 * @adev: amdgpu_device pointer
3222 * First resume function for hardware IPs. The list of all the hardware
3223 * IPs that make up the asic is walked and the resume callbacks are run for
3224 * COMMON, GMC, and IH. resume puts the hardware into a functional state
3225 * after a suspend and updates the software state as necessary. This
3226 * function is also used for restoring the GPU after a GPU reset.
3227 * Returns 0 on success, negative error code on failure.
3229 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
3233 for (i = 0; i < adev->num_ip_blocks; i++) {
3234 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3236 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3237 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3238 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3239 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {
3241 r = adev->ip_blocks[i].version->funcs->resume(adev);
3243 DRM_ERROR("resume of IP block <%s> failed %d\n",
3244 adev->ip_blocks[i].version->funcs->name, r);
3247 adev->ip_blocks[i].status.hw = true;
3255 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
3257 * @adev: amdgpu_device pointer
3259 * First resume function for hardware IPs. The list of all the hardware
3260 * IPs that make up the asic is walked and the resume callbacks are run for
3261 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
3262 * functional state after a suspend and updates the software state as
3263 * necessary. This function is also used for restoring the GPU after a GPU
3265 * Returns 0 on success, negative error code on failure.
3267 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
3271 for (i = 0; i < adev->num_ip_blocks; i++) {
3272 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3274 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3275 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3276 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3277 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3279 r = adev->ip_blocks[i].version->funcs->resume(adev);
3281 DRM_ERROR("resume of IP block <%s> failed %d\n",
3282 adev->ip_blocks[i].version->funcs->name, r);
3285 adev->ip_blocks[i].status.hw = true;
3292 * amdgpu_device_ip_resume - run resume for hardware IPs
3294 * @adev: amdgpu_device pointer
3296 * Main resume function for hardware IPs. The hardware IPs
3297 * are split into two resume functions because they are
3298 * are also used in in recovering from a GPU reset and some additional
3299 * steps need to be take between them. In this case (S3/S4) they are
3301 * Returns 0 on success, negative error code on failure.
3303 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
3307 if (!adev->in_s0ix) {
3308 r = amdgpu_amdkfd_resume_iommu(adev);
3313 r = amdgpu_device_ip_resume_phase1(adev);
3317 r = amdgpu_device_fw_loading(adev);
3321 r = amdgpu_device_ip_resume_phase2(adev);
3327 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
3329 * @adev: amdgpu_device pointer
3331 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3333 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3335 if (amdgpu_sriov_vf(adev)) {
3336 if (adev->is_atom_fw) {
3337 if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
3338 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3340 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3341 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3344 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3345 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3350 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3352 * @asic_type: AMD asic type
3354 * Check if there is DC (new modesetting infrastructre) support for an asic.
3355 * returns true if DC has support, false if not.
3357 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3359 switch (asic_type) {
3360 #ifdef CONFIG_DRM_AMDGPU_SI
3364 /* chips with no display hardware */
3366 #if defined(CONFIG_DRM_AMD_DC)
3372 * We have systems in the wild with these ASICs that require
3373 * LVDS and VGA support which is not supported with DC.
3375 * Fallback to the non-DC driver here by default so as not to
3376 * cause regressions.
3378 #if defined(CONFIG_DRM_AMD_DC_SI)
3379 return amdgpu_dc > 0;
3388 * We have systems in the wild with these ASICs that require
3389 * VGA support which is not supported with DC.
3391 * Fallback to the non-DC driver here by default so as not to
3392 * cause regressions.
3394 return amdgpu_dc > 0;
3396 return amdgpu_dc != 0;
3400 DRM_INFO_ONCE("Display Core has been requested via kernel parameter "
3401 "but isn't supported by ASIC, ignoring\n");
3408 * amdgpu_device_has_dc_support - check if dc is supported
3410 * @adev: amdgpu_device pointer
3412 * Returns true for supported, false for not supported
3414 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3416 if (adev->enable_virtual_display ||
3417 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3420 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3423 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3425 struct amdgpu_device *adev =
3426 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3427 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3429 /* It's a bug to not have a hive within this function */
3434 * Use task barrier to synchronize all xgmi reset works across the
3435 * hive. task_barrier_enter and task_barrier_exit will block
3436 * until all the threads running the xgmi reset works reach
3437 * those points. task_barrier_full will do both blocks.
3439 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3441 task_barrier_enter(&hive->tb);
3442 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3444 if (adev->asic_reset_res)
3447 task_barrier_exit(&hive->tb);
3448 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3450 if (adev->asic_reset_res)
3453 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops &&
3454 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
3455 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev);
3458 task_barrier_full(&hive->tb);
3459 adev->asic_reset_res = amdgpu_asic_reset(adev);
3463 if (adev->asic_reset_res)
3464 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3465 adev->asic_reset_res, adev_to_drm(adev)->unique);
3466 amdgpu_put_xgmi_hive(hive);
3469 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3471 char *input = amdgpu_lockup_timeout;
3472 char *timeout_setting = NULL;
3478 * By default timeout for non compute jobs is 10000
3479 * and 60000 for compute jobs.
3480 * In SR-IOV or passthrough mode, timeout for compute
3481 * jobs are 60000 by default.
3483 adev->gfx_timeout = msecs_to_jiffies(10000);
3484 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3485 if (amdgpu_sriov_vf(adev))
3486 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3487 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3489 adev->compute_timeout = msecs_to_jiffies(60000);
3491 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3492 while ((timeout_setting = strsep(&input, ",")) &&
3493 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3494 ret = kstrtol(timeout_setting, 0, &timeout);
3501 } else if (timeout < 0) {
3502 timeout = MAX_SCHEDULE_TIMEOUT;
3503 dev_warn(adev->dev, "lockup timeout disabled");
3504 add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
3506 timeout = msecs_to_jiffies(timeout);
3511 adev->gfx_timeout = timeout;
3514 adev->compute_timeout = timeout;
3517 adev->sdma_timeout = timeout;
3520 adev->video_timeout = timeout;
3527 * There is only one value specified and
3528 * it should apply to all non-compute jobs.
3531 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3532 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3533 adev->compute_timeout = adev->gfx_timeout;
3541 * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU
3543 * @adev: amdgpu_device pointer
3545 * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode
3547 static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)
3549 struct iommu_domain *domain;
3551 domain = iommu_get_domain_for_dev(adev->dev);
3552 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
3553 adev->ram_is_direct_mapped = true;
3556 static const struct attribute *amdgpu_dev_attributes[] = {
3557 &dev_attr_product_name.attr,
3558 &dev_attr_product_number.attr,
3559 &dev_attr_serial_number.attr,
3560 &dev_attr_pcie_replay_count.attr,
3565 * amdgpu_device_init - initialize the driver
3567 * @adev: amdgpu_device pointer
3568 * @flags: driver flags
3570 * Initializes the driver info and hw (all asics).
3571 * Returns 0 for success or an error on failure.
3572 * Called at driver startup.
3574 int amdgpu_device_init(struct amdgpu_device *adev,
3577 struct drm_device *ddev = adev_to_drm(adev);
3578 struct pci_dev *pdev = adev->pdev;
3584 adev->shutdown = false;
3585 adev->flags = flags;
3587 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3588 adev->asic_type = amdgpu_force_asic_type;
3590 adev->asic_type = flags & AMD_ASIC_MASK;
3592 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3593 if (amdgpu_emu_mode == 1)
3594 adev->usec_timeout *= 10;
3595 adev->gmc.gart_size = 512 * 1024 * 1024;
3596 adev->accel_working = false;
3597 adev->num_rings = 0;
3598 RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
3599 adev->mman.buffer_funcs = NULL;
3600 adev->mman.buffer_funcs_ring = NULL;
3601 adev->vm_manager.vm_pte_funcs = NULL;
3602 adev->vm_manager.vm_pte_num_scheds = 0;
3603 adev->gmc.gmc_funcs = NULL;
3604 adev->harvest_ip_mask = 0x0;
3605 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3606 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3608 adev->smc_rreg = &amdgpu_invalid_rreg;
3609 adev->smc_wreg = &amdgpu_invalid_wreg;
3610 adev->pcie_rreg = &amdgpu_invalid_rreg;
3611 adev->pcie_wreg = &amdgpu_invalid_wreg;
3612 adev->pciep_rreg = &amdgpu_invalid_rreg;
3613 adev->pciep_wreg = &amdgpu_invalid_wreg;
3614 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3615 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3616 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3617 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3618 adev->didt_rreg = &amdgpu_invalid_rreg;
3619 adev->didt_wreg = &amdgpu_invalid_wreg;
3620 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3621 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3622 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3623 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3625 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3626 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3627 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3629 /* mutex initialization are all done here so we
3630 * can recall function without having locking issues */
3631 mutex_init(&adev->firmware.mutex);
3632 mutex_init(&adev->pm.mutex);
3633 mutex_init(&adev->gfx.gpu_clock_mutex);
3634 mutex_init(&adev->srbm_mutex);
3635 mutex_init(&adev->gfx.pipe_reserve_mutex);
3636 mutex_init(&adev->gfx.gfx_off_mutex);
3637 mutex_init(&adev->grbm_idx_mutex);
3638 mutex_init(&adev->mn_lock);
3639 mutex_init(&adev->virt.vf_errors.lock);
3640 hash_init(adev->mn_hash);
3641 mutex_init(&adev->psp.mutex);
3642 mutex_init(&adev->notifier_lock);
3643 mutex_init(&adev->pm.stable_pstate_ctx_lock);
3644 mutex_init(&adev->benchmark_mutex);
3646 amdgpu_device_init_apu_flags(adev);
3648 r = amdgpu_device_check_arguments(adev);
3652 spin_lock_init(&adev->mmio_idx_lock);
3653 spin_lock_init(&adev->smc_idx_lock);
3654 spin_lock_init(&adev->pcie_idx_lock);
3655 spin_lock_init(&adev->uvd_ctx_idx_lock);
3656 spin_lock_init(&adev->didt_idx_lock);
3657 spin_lock_init(&adev->gc_cac_idx_lock);
3658 spin_lock_init(&adev->se_cac_idx_lock);
3659 spin_lock_init(&adev->audio_endpt_idx_lock);
3660 spin_lock_init(&adev->mm_stats.lock);
3662 INIT_LIST_HEAD(&adev->shadow_list);
3663 mutex_init(&adev->shadow_list_lock);
3665 INIT_LIST_HEAD(&adev->reset_list);
3667 INIT_LIST_HEAD(&adev->ras_list);
3669 INIT_DELAYED_WORK(&adev->delayed_init_work,
3670 amdgpu_device_delayed_init_work_handler);
3671 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3672 amdgpu_device_delay_enable_gfx_off);
3674 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3676 adev->gfx.gfx_off_req_count = 1;
3677 adev->gfx.gfx_off_residency = 0;
3678 adev->gfx.gfx_off_entrycount = 0;
3679 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3681 atomic_set(&adev->throttling_logging_enabled, 1);
3683 * If throttling continues, logging will be performed every minute
3684 * to avoid log flooding. "-1" is subtracted since the thermal
3685 * throttling interrupt comes every second. Thus, the total logging
3686 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3687 * for throttling interrupt) = 60 seconds.
3689 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3690 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
3692 /* Registers mapping */
3693 /* TODO: block userspace mapping of io register */
3694 if (adev->asic_type >= CHIP_BONAIRE) {
3695 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3696 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3698 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3699 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3702 for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
3703 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
3705 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3706 if (adev->rmmio == NULL) {
3709 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3710 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
3712 amdgpu_device_get_pcie_info(adev);
3715 DRM_INFO("MCBP is enabled\n");
3718 * Reset domain needs to be present early, before XGMI hive discovered
3719 * (if any) and intitialized to use reset sem and in_gpu reset flag
3720 * early on during init and before calling to RREG32.
3722 adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");
3723 if (!adev->reset_domain)
3726 /* detect hw virtualization here */
3727 amdgpu_detect_virtualization(adev);
3729 r = amdgpu_device_get_job_timeout_settings(adev);
3731 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3735 /* early init functions */
3736 r = amdgpu_device_ip_early_init(adev);
3740 /* Get rid of things like offb */
3741 r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver);
3745 /* Enable TMZ based on IP_VERSION */
3746 amdgpu_gmc_tmz_set(adev);
3748 amdgpu_gmc_noretry_set(adev);
3749 /* Need to get xgmi info early to decide the reset behavior*/
3750 if (adev->gmc.xgmi.supported) {
3751 r = adev->gfxhub.funcs->get_xgmi_info(adev);
3756 /* enable PCIE atomic ops */
3757 if (amdgpu_sriov_vf(adev))
3758 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
3759 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
3760 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3762 adev->have_atomics_support =
3763 !pci_enable_atomic_ops_to_root(adev->pdev,
3764 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
3765 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3766 if (!adev->have_atomics_support)
3767 dev_info(adev->dev, "PCIE atomic ops is not supported\n");
3769 /* doorbell bar mapping and doorbell index init*/
3770 amdgpu_device_doorbell_init(adev);
3772 if (amdgpu_emu_mode == 1) {
3773 /* post the asic on emulation mode */
3774 emu_soc_asic_init(adev);
3775 goto fence_driver_init;
3778 amdgpu_reset_init(adev);
3780 /* detect if we are with an SRIOV vbios */
3781 amdgpu_device_detect_sriov_bios(adev);
3783 /* check if we need to reset the asic
3784 * E.g., driver was not cleanly unloaded previously, etc.
3786 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
3787 if (adev->gmc.xgmi.num_physical_nodes) {
3788 dev_info(adev->dev, "Pending hive reset.\n");
3789 adev->gmc.xgmi.pending_reset = true;
3790 /* Only need to init necessary block for SMU to handle the reset */
3791 for (i = 0; i < adev->num_ip_blocks; i++) {
3792 if (!adev->ip_blocks[i].status.valid)
3794 if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3795 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3796 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3797 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) {
3798 DRM_DEBUG("IP %s disabled for hw_init.\n",
3799 adev->ip_blocks[i].version->funcs->name);
3800 adev->ip_blocks[i].status.hw = true;
3804 tmp = amdgpu_reset_method;
3805 /* It should do a default reset when loading or reloading the driver,
3806 * regardless of the module parameter reset_method.
3808 amdgpu_reset_method = AMD_RESET_METHOD_NONE;
3809 r = amdgpu_asic_reset(adev);
3810 amdgpu_reset_method = tmp;
3812 dev_err(adev->dev, "asic reset on init failed\n");
3818 /* Post card if necessary */
3819 if (amdgpu_device_need_post(adev)) {
3821 dev_err(adev->dev, "no vBIOS found\n");
3825 DRM_INFO("GPU posting now...\n");
3826 r = amdgpu_device_asic_init(adev);
3828 dev_err(adev->dev, "gpu post error!\n");
3833 if (adev->is_atom_fw) {
3834 /* Initialize clocks */
3835 r = amdgpu_atomfirmware_get_clock_info(adev);
3837 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
3838 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3842 /* Initialize clocks */
3843 r = amdgpu_atombios_get_clock_info(adev);
3845 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
3846 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3849 /* init i2c buses */
3850 if (!amdgpu_device_has_dc_support(adev))
3851 amdgpu_atombios_i2c_init(adev);
3856 r = amdgpu_fence_driver_sw_init(adev);
3858 dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n");
3859 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
3863 /* init the mode config */
3864 drm_mode_config_init(adev_to_drm(adev));
3866 r = amdgpu_device_ip_init(adev);
3868 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
3869 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
3870 goto release_ras_con;
3873 amdgpu_fence_driver_hw_init(adev);
3876 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
3877 adev->gfx.config.max_shader_engines,
3878 adev->gfx.config.max_sh_per_se,
3879 adev->gfx.config.max_cu_per_sh,
3880 adev->gfx.cu_info.number);
3882 adev->accel_working = true;
3884 amdgpu_vm_check_compute_bug(adev);
3886 /* Initialize the buffer migration limit. */
3887 if (amdgpu_moverate >= 0)
3888 max_MBps = amdgpu_moverate;
3890 max_MBps = 8; /* Allow 8 MB/s. */
3891 /* Get a log2 for easy divisions. */
3892 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
3894 r = amdgpu_pm_sysfs_init(adev);
3896 DRM_ERROR("registering pm sysfs failed (%d).\n", r);
3898 r = amdgpu_ucode_sysfs_init(adev);
3900 adev->ucode_sysfs_en = false;
3901 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
3903 adev->ucode_sysfs_en = true;
3905 r = amdgpu_psp_sysfs_init(adev);
3907 adev->psp_sysfs_en = false;
3908 if (!amdgpu_sriov_vf(adev))
3909 DRM_ERROR("Creating psp sysfs failed\n");
3911 adev->psp_sysfs_en = true;
3914 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3915 * Otherwise the mgpu fan boost feature will be skipped due to the
3916 * gpu instance is counted less.
3918 amdgpu_register_gpu_instance(adev);
3920 /* enable clockgating, etc. after ib tests, etc. since some blocks require
3921 * explicit gating rather than handling it automatically.
3923 if (!adev->gmc.xgmi.pending_reset) {
3924 r = amdgpu_device_ip_late_init(adev);
3926 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
3927 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
3928 goto release_ras_con;
3931 amdgpu_ras_resume(adev);
3932 queue_delayed_work(system_wq, &adev->delayed_init_work,
3933 msecs_to_jiffies(AMDGPU_RESUME_MS));
3936 if (amdgpu_sriov_vf(adev)) {
3937 amdgpu_virt_release_full_gpu(adev, true);
3938 flush_delayed_work(&adev->delayed_init_work);
3941 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
3943 dev_err(adev->dev, "Could not create amdgpu device attr\n");
3945 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3946 r = amdgpu_pmu_init(adev);
3948 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
3950 /* Have stored pci confspace at hand for restore in sudden PCI error */
3951 if (amdgpu_device_cache_pci_state(adev->pdev))
3952 pci_restore_state(pdev);
3954 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
3955 /* this will fail for cards that aren't VGA class devices, just
3957 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3958 vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
3960 px = amdgpu_device_supports_px(ddev);
3962 if (px || (!pci_is_thunderbolt_attached(adev->pdev) &&
3963 apple_gmux_detect(NULL, NULL)))
3964 vga_switcheroo_register_client(adev->pdev,
3965 &amdgpu_switcheroo_ops, px);
3968 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
3970 if (adev->gmc.xgmi.pending_reset)
3971 queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
3972 msecs_to_jiffies(AMDGPU_RESUME_MS));
3974 amdgpu_device_check_iommu_direct_map(adev);
3979 if (amdgpu_sriov_vf(adev))
3980 amdgpu_virt_release_full_gpu(adev, true);
3982 /* failed in exclusive mode due to timeout */
3983 if (amdgpu_sriov_vf(adev) &&
3984 !amdgpu_sriov_runtime(adev) &&
3985 amdgpu_virt_mmio_blocked(adev) &&
3986 !amdgpu_virt_wait_reset(adev)) {
3987 dev_err(adev->dev, "VF exclusive mode timeout\n");
3988 /* Don't send request since VF is inactive. */
3989 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
3990 adev->virt.ops = NULL;
3993 amdgpu_release_ras_context(adev);
3996 amdgpu_vf_error_trans_all(adev);
4001 static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
4004 /* Clear all CPU mappings pointing to this device */
4005 unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
4007 /* Unmap all mapped bars - Doorbell, registers and VRAM */
4008 amdgpu_device_doorbell_fini(adev);
4010 iounmap(adev->rmmio);
4012 if (adev->mman.aper_base_kaddr)
4013 iounmap(adev->mman.aper_base_kaddr);
4014 adev->mman.aper_base_kaddr = NULL;
4016 /* Memory manager related */
4017 if (!adev->gmc.xgmi.connected_to_cpu) {
4018 arch_phys_wc_del(adev->gmc.vram_mtrr);
4019 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
4024 * amdgpu_device_fini_hw - tear down the driver
4026 * @adev: amdgpu_device pointer
4028 * Tear down the driver info (all asics).
4029 * Called at driver shutdown.
4031 void amdgpu_device_fini_hw(struct amdgpu_device *adev)
4033 dev_info(adev->dev, "amdgpu: finishing device.\n");
4034 flush_delayed_work(&adev->delayed_init_work);
4035 adev->shutdown = true;
4037 /* make sure IB test finished before entering exclusive mode
4038 * to avoid preemption on IB test
4040 if (amdgpu_sriov_vf(adev)) {
4041 amdgpu_virt_request_full_gpu(adev, false);
4042 amdgpu_virt_fini_data_exchange(adev);
4045 /* disable all interrupts */
4046 amdgpu_irq_disable_all(adev);
4047 if (adev->mode_info.mode_config_initialized) {
4048 if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
4049 drm_helper_force_disable_all(adev_to_drm(adev));
4051 drm_atomic_helper_shutdown(adev_to_drm(adev));
4053 amdgpu_fence_driver_hw_fini(adev);
4055 if (adev->mman.initialized)
4056 drain_workqueue(adev->mman.bdev.wq);
4058 if (adev->pm.sysfs_initialized)
4059 amdgpu_pm_sysfs_fini(adev);
4060 if (adev->ucode_sysfs_en)
4061 amdgpu_ucode_sysfs_fini(adev);
4062 if (adev->psp_sysfs_en)
4063 amdgpu_psp_sysfs_fini(adev);
4064 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
4066 /* disable ras feature must before hw fini */
4067 amdgpu_ras_pre_fini(adev);
4069 amdgpu_device_ip_fini_early(adev);
4071 amdgpu_irq_fini_hw(adev);
4073 if (adev->mman.initialized)
4074 ttm_device_clear_dma_mappings(&adev->mman.bdev);
4076 amdgpu_gart_dummy_page_fini(adev);
4078 if (drm_dev_is_unplugged(adev_to_drm(adev)))
4079 amdgpu_device_unmap_mmio(adev);
4083 void amdgpu_device_fini_sw(struct amdgpu_device *adev)
4088 amdgpu_fence_driver_sw_fini(adev);
4089 amdgpu_device_ip_fini(adev);
4090 amdgpu_ucode_release(&adev->firmware.gpu_info_fw);
4091 adev->accel_working = false;
4092 dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));
4094 amdgpu_reset_fini(adev);
4096 /* free i2c buses */
4097 if (!amdgpu_device_has_dc_support(adev))
4098 amdgpu_i2c_fini(adev);
4100 if (amdgpu_emu_mode != 1)
4101 amdgpu_atombios_fini(adev);
4106 px = amdgpu_device_supports_px(adev_to_drm(adev));
4108 if (px || (!pci_is_thunderbolt_attached(adev->pdev) &&
4109 apple_gmux_detect(NULL, NULL)))
4110 vga_switcheroo_unregister_client(adev->pdev);
4113 vga_switcheroo_fini_domain_pm_ops(adev->dev);
4115 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4116 vga_client_unregister(adev->pdev);
4118 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
4120 iounmap(adev->rmmio);
4122 amdgpu_device_doorbell_fini(adev);
4126 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4127 amdgpu_pmu_fini(adev);
4128 if (adev->mman.discovery_bin)
4129 amdgpu_discovery_fini(adev);
4131 amdgpu_reset_put_reset_domain(adev->reset_domain);
4132 adev->reset_domain = NULL;
4134 kfree(adev->pci_state);
4139 * amdgpu_device_evict_resources - evict device resources
4140 * @adev: amdgpu device object
4142 * Evicts all ttm device resources(vram BOs, gart table) from the lru list
4143 * of the vram memory type. Mainly used for evicting device resources
4147 static int amdgpu_device_evict_resources(struct amdgpu_device *adev)
4151 /* No need to evict vram on APUs for suspend to ram or s2idle */
4152 if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
4155 ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
4157 DRM_WARN("evicting device resources failed\n");
4165 * amdgpu_device_suspend - initiate device suspend
4167 * @dev: drm dev pointer
4168 * @fbcon : notify the fbdev of suspend
4170 * Puts the hw in the suspend state (all asics).
4171 * Returns 0 for success or an error on failure.
4172 * Called at driver suspend.
4174 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
4176 struct amdgpu_device *adev = drm_to_adev(dev);
4179 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4182 adev->in_suspend = true;
4184 /* Evict the majority of BOs before grabbing the full access */
4185 r = amdgpu_device_evict_resources(adev);
4189 if (amdgpu_sriov_vf(adev)) {
4190 amdgpu_virt_fini_data_exchange(adev);
4191 r = amdgpu_virt_request_full_gpu(adev, false);
4196 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
4197 DRM_WARN("smart shift update failed\n");
4200 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
4202 cancel_delayed_work_sync(&adev->delayed_init_work);
4204 amdgpu_ras_suspend(adev);
4206 amdgpu_device_ip_suspend_phase1(adev);
4209 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
4211 r = amdgpu_device_evict_resources(adev);
4215 amdgpu_fence_driver_hw_fini(adev);
4217 amdgpu_device_ip_suspend_phase2(adev);
4219 if (amdgpu_sriov_vf(adev))
4220 amdgpu_virt_release_full_gpu(adev, false);
4226 * amdgpu_device_resume - initiate device resume
4228 * @dev: drm dev pointer
4229 * @fbcon : notify the fbdev of resume
4231 * Bring the hw back to operating state (all asics).
4232 * Returns 0 for success or an error on failure.
4233 * Called at driver resume.
4235 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
4237 struct amdgpu_device *adev = drm_to_adev(dev);
4240 if (amdgpu_sriov_vf(adev)) {
4241 r = amdgpu_virt_request_full_gpu(adev, true);
4246 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4250 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);
4253 if (amdgpu_device_need_post(adev)) {
4254 r = amdgpu_device_asic_init(adev);
4256 dev_err(adev->dev, "amdgpu asic init failed\n");
4259 r = amdgpu_device_ip_resume(adev);
4262 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
4265 amdgpu_fence_driver_hw_init(adev);
4267 r = amdgpu_device_ip_late_init(adev);
4271 queue_delayed_work(system_wq, &adev->delayed_init_work,
4272 msecs_to_jiffies(AMDGPU_RESUME_MS));
4274 if (!adev->in_s0ix) {
4275 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
4281 if (amdgpu_sriov_vf(adev)) {
4282 amdgpu_virt_init_data_exchange(adev);
4283 amdgpu_virt_release_full_gpu(adev, true);
4289 /* Make sure IB tests flushed */
4290 flush_delayed_work(&adev->delayed_init_work);
4293 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
4295 amdgpu_ras_resume(adev);
4297 if (adev->mode_info.num_crtc) {
4299 * Most of the connector probing functions try to acquire runtime pm
4300 * refs to ensure that the GPU is powered on when connector polling is
4301 * performed. Since we're calling this from a runtime PM callback,
4302 * trying to acquire rpm refs will cause us to deadlock.
4304 * Since we're guaranteed to be holding the rpm lock, it's safe to
4305 * temporarily disable the rpm helpers so this doesn't deadlock us.
4308 dev->dev->power.disable_depth++;
4310 if (!adev->dc_enabled)
4311 drm_helper_hpd_irq_event(dev);
4313 drm_kms_helper_hotplug_event(dev);
4315 dev->dev->power.disable_depth--;
4318 adev->in_suspend = false;
4320 if (adev->enable_mes)
4321 amdgpu_mes_self_test(adev);
4323 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
4324 DRM_WARN("smart shift update failed\n");
4330 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
4332 * @adev: amdgpu_device pointer
4334 * The list of all the hardware IPs that make up the asic is walked and
4335 * the check_soft_reset callbacks are run. check_soft_reset determines
4336 * if the asic is still hung or not.
4337 * Returns true if any of the IPs are still in a hung state, false if not.
4339 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
4342 bool asic_hang = false;
4344 if (amdgpu_sriov_vf(adev))
4347 if (amdgpu_asic_need_full_reset(adev))
4350 for (i = 0; i < adev->num_ip_blocks; i++) {
4351 if (!adev->ip_blocks[i].status.valid)
4353 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
4354 adev->ip_blocks[i].status.hang =
4355 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
4356 if (adev->ip_blocks[i].status.hang) {
4357 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
4365 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
4367 * @adev: amdgpu_device pointer
4369 * The list of all the hardware IPs that make up the asic is walked and the
4370 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
4371 * handles any IP specific hardware or software state changes that are
4372 * necessary for a soft reset to succeed.
4373 * Returns 0 on success, negative error code on failure.
4375 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
4379 for (i = 0; i < adev->num_ip_blocks; i++) {
4380 if (!adev->ip_blocks[i].status.valid)
4382 if (adev->ip_blocks[i].status.hang &&
4383 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
4384 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
4394 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
4396 * @adev: amdgpu_device pointer
4398 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
4399 * reset is necessary to recover.
4400 * Returns true if a full asic reset is required, false if not.
4402 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
4406 if (amdgpu_asic_need_full_reset(adev))
4409 for (i = 0; i < adev->num_ip_blocks; i++) {
4410 if (!adev->ip_blocks[i].status.valid)
4412 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
4413 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
4414 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
4415 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
4416 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
4417 if (adev->ip_blocks[i].status.hang) {
4418 dev_info(adev->dev, "Some block need full reset!\n");
4427 * amdgpu_device_ip_soft_reset - do a soft reset
4429 * @adev: amdgpu_device pointer
4431 * The list of all the hardware IPs that make up the asic is walked and the
4432 * soft_reset callbacks are run if the block is hung. soft_reset handles any
4433 * IP specific hardware or software state changes that are necessary to soft
4435 * Returns 0 on success, negative error code on failure.
4437 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
4441 for (i = 0; i < adev->num_ip_blocks; i++) {
4442 if (!adev->ip_blocks[i].status.valid)
4444 if (adev->ip_blocks[i].status.hang &&
4445 adev->ip_blocks[i].version->funcs->soft_reset) {
4446 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
4456 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
4458 * @adev: amdgpu_device pointer
4460 * The list of all the hardware IPs that make up the asic is walked and the
4461 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
4462 * handles any IP specific hardware or software state changes that are
4463 * necessary after the IP has been soft reset.
4464 * Returns 0 on success, negative error code on failure.
4466 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4470 for (i = 0; i < adev->num_ip_blocks; i++) {
4471 if (!adev->ip_blocks[i].status.valid)
4473 if (adev->ip_blocks[i].status.hang &&
4474 adev->ip_blocks[i].version->funcs->post_soft_reset)
4475 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4484 * amdgpu_device_recover_vram - Recover some VRAM contents
4486 * @adev: amdgpu_device pointer
4488 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4489 * restore things like GPUVM page tables after a GPU reset where
4490 * the contents of VRAM might be lost.
4493 * 0 on success, negative error code on failure.
4495 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4497 struct dma_fence *fence = NULL, *next = NULL;
4498 struct amdgpu_bo *shadow;
4499 struct amdgpu_bo_vm *vmbo;
4502 if (amdgpu_sriov_runtime(adev))
4503 tmo = msecs_to_jiffies(8000);
4505 tmo = msecs_to_jiffies(100);
4507 dev_info(adev->dev, "recover vram bo from shadow start\n");
4508 mutex_lock(&adev->shadow_list_lock);
4509 list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
4511 /* No need to recover an evicted BO */
4512 if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
4513 shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
4514 shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM)
4517 r = amdgpu_bo_restore_shadow(shadow, &next);
4522 tmo = dma_fence_wait_timeout(fence, false, tmo);
4523 dma_fence_put(fence);
4528 } else if (tmo < 0) {
4536 mutex_unlock(&adev->shadow_list_lock);
4539 tmo = dma_fence_wait_timeout(fence, false, tmo);
4540 dma_fence_put(fence);
4542 if (r < 0 || tmo <= 0) {
4543 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4547 dev_info(adev->dev, "recover vram bo from shadow done\n");
4553 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4555 * @adev: amdgpu_device pointer
4556 * @from_hypervisor: request from hypervisor
4558 * do VF FLR and reinitialize Asic
4559 * return 0 means succeeded otherwise failed
4561 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4562 bool from_hypervisor)
4565 struct amdgpu_hive_info *hive = NULL;
4566 int retry_limit = 0;
4569 amdgpu_amdkfd_pre_reset(adev);
4571 if (from_hypervisor)
4572 r = amdgpu_virt_request_full_gpu(adev, true);
4574 r = amdgpu_virt_reset_gpu(adev);
4578 /* Resume IP prior to SMC */
4579 r = amdgpu_device_ip_reinit_early_sriov(adev);
4583 amdgpu_virt_init_data_exchange(adev);
4585 r = amdgpu_device_fw_loading(adev);
4589 /* now we are okay to resume SMC/CP/SDMA */
4590 r = amdgpu_device_ip_reinit_late_sriov(adev);
4594 hive = amdgpu_get_xgmi_hive(adev);
4595 /* Update PSP FW topology after reset */
4596 if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
4597 r = amdgpu_xgmi_update_topology(hive, adev);
4600 amdgpu_put_xgmi_hive(hive);
4603 amdgpu_irq_gpu_reset_resume_helper(adev);
4604 r = amdgpu_ib_ring_tests(adev);
4606 amdgpu_amdkfd_post_reset(adev);
4610 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4611 amdgpu_inc_vram_lost(adev);
4612 r = amdgpu_device_recover_vram(adev);
4614 amdgpu_virt_release_full_gpu(adev, true);
4616 if (AMDGPU_RETRY_SRIOV_RESET(r)) {
4617 if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) {
4621 DRM_ERROR("GPU reset retry is beyond the retry limit\n");
4628 * amdgpu_device_has_job_running - check if there is any job in mirror list
4630 * @adev: amdgpu_device pointer
4632 * check if there is any job in mirror list
4634 bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
4637 struct drm_sched_job *job;
4639 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4640 struct amdgpu_ring *ring = adev->rings[i];
4642 if (!ring || !ring->sched.thread)
4645 spin_lock(&ring->sched.job_list_lock);
4646 job = list_first_entry_or_null(&ring->sched.pending_list,
4647 struct drm_sched_job, list);
4648 spin_unlock(&ring->sched.job_list_lock);
4656 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
4658 * @adev: amdgpu_device pointer
4660 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
4663 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
4666 if (amdgpu_gpu_recovery == 0)
4669 /* Skip soft reset check in fatal error mode */
4670 if (!amdgpu_ras_is_poison_mode_supported(adev))
4673 if (amdgpu_sriov_vf(adev))
4676 if (amdgpu_gpu_recovery == -1) {
4677 switch (adev->asic_type) {
4678 #ifdef CONFIG_DRM_AMDGPU_SI
4685 #ifdef CONFIG_DRM_AMDGPU_CIK
4692 case CHIP_CYAN_SKILLFISH:
4702 dev_info(adev->dev, "GPU recovery disabled.\n");
4706 int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
4711 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
4713 dev_info(adev->dev, "GPU mode1 reset\n");
4716 pci_clear_master(adev->pdev);
4718 amdgpu_device_cache_pci_state(adev->pdev);
4720 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
4721 dev_info(adev->dev, "GPU smu mode1 reset\n");
4722 ret = amdgpu_dpm_mode1_reset(adev);
4724 dev_info(adev->dev, "GPU psp mode1 reset\n");
4725 ret = psp_gpu_reset(adev);
4729 dev_err(adev->dev, "GPU mode1 reset failed\n");
4731 amdgpu_device_load_pci_state(adev->pdev);
4733 /* wait for asic to come out of reset */
4734 for (i = 0; i < adev->usec_timeout; i++) {
4735 u32 memsize = adev->nbio.funcs->get_memsize(adev);
4737 if (memsize != 0xffffffff)
4742 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
4746 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
4747 struct amdgpu_reset_context *reset_context)
4750 struct amdgpu_job *job = NULL;
4751 bool need_full_reset =
4752 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4754 if (reset_context->reset_req_dev == adev)
4755 job = reset_context->job;
4757 if (amdgpu_sriov_vf(adev)) {
4758 /* stop the data exchange thread */
4759 amdgpu_virt_fini_data_exchange(adev);
4762 amdgpu_fence_driver_isr_toggle(adev, true);
4764 /* block all schedulers and reset given job's ring */
4765 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4766 struct amdgpu_ring *ring = adev->rings[i];
4768 if (!ring || !ring->sched.thread)
4771 /*clear job fence from fence drv to avoid force_completion
4772 *leave NULL and vm flush fence in fence drv */
4773 amdgpu_fence_driver_clear_job_fences(ring);
4775 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
4776 amdgpu_fence_driver_force_completion(ring);
4779 amdgpu_fence_driver_isr_toggle(adev, false);
4782 drm_sched_increase_karma(&job->base);
4784 r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
4785 /* If reset handler not implemented, continue; otherwise return */
4791 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
4792 if (!amdgpu_sriov_vf(adev)) {
4794 if (!need_full_reset)
4795 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
4797 if (!need_full_reset && amdgpu_gpu_recovery &&
4798 amdgpu_device_ip_check_soft_reset(adev)) {
4799 amdgpu_device_ip_pre_soft_reset(adev);
4800 r = amdgpu_device_ip_soft_reset(adev);
4801 amdgpu_device_ip_post_soft_reset(adev);
4802 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
4803 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
4804 need_full_reset = true;
4808 if (need_full_reset)
4809 r = amdgpu_device_ip_suspend(adev);
4810 if (need_full_reset)
4811 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4813 clear_bit(AMDGPU_NEED_FULL_RESET,
4814 &reset_context->flags);
4820 static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
4824 lockdep_assert_held(&adev->reset_domain->sem);
4826 for (i = 0; i < adev->num_regs; i++) {
4827 adev->reset_dump_reg_value[i] = RREG32(adev->reset_dump_reg_list[i]);
4828 trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i],
4829 adev->reset_dump_reg_value[i]);
4835 #ifdef CONFIG_DEV_COREDUMP
4836 static ssize_t amdgpu_devcoredump_read(char *buffer, loff_t offset,
4837 size_t count, void *data, size_t datalen)
4839 struct drm_printer p;
4840 struct amdgpu_device *adev = data;
4841 struct drm_print_iterator iter;
4846 iter.start = offset;
4847 iter.remain = count;
4849 p = drm_coredump_printer(&iter);
4851 drm_printf(&p, "**** AMDGPU Device Coredump ****\n");
4852 drm_printf(&p, "kernel: " UTS_RELEASE "\n");
4853 drm_printf(&p, "module: " KBUILD_MODNAME "\n");
4854 drm_printf(&p, "time: %lld.%09ld\n", adev->reset_time.tv_sec, adev->reset_time.tv_nsec);
4855 if (adev->reset_task_info.pid)
4856 drm_printf(&p, "process_name: %s PID: %d\n",
4857 adev->reset_task_info.process_name,
4858 adev->reset_task_info.pid);
4860 if (adev->reset_vram_lost)
4861 drm_printf(&p, "VRAM is lost due to GPU reset!\n");
4862 if (adev->num_regs) {
4863 drm_printf(&p, "AMDGPU register dumps:\nOffset: Value:\n");
4865 for (i = 0; i < adev->num_regs; i++)
4866 drm_printf(&p, "0x%08x: 0x%08x\n",
4867 adev->reset_dump_reg_list[i],
4868 adev->reset_dump_reg_value[i]);
4871 return count - iter.remain;
4874 static void amdgpu_devcoredump_free(void *data)
4878 static void amdgpu_reset_capture_coredumpm(struct amdgpu_device *adev)
4880 struct drm_device *dev = adev_to_drm(adev);
4882 ktime_get_ts64(&adev->reset_time);
4883 dev_coredumpm(dev->dev, THIS_MODULE, adev, 0, GFP_KERNEL,
4884 amdgpu_devcoredump_read, amdgpu_devcoredump_free);
4888 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
4889 struct amdgpu_reset_context *reset_context)
4891 struct amdgpu_device *tmp_adev = NULL;
4892 bool need_full_reset, skip_hw_reset, vram_lost = false;
4894 bool gpu_reset_for_dev_remove = 0;
4896 /* Try reset handler method first */
4897 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
4899 amdgpu_reset_reg_dumps(tmp_adev);
4901 reset_context->reset_device_list = device_list_handle;
4902 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
4903 /* If reset handler not implemented, continue; otherwise return */
4909 /* Reset handler not implemented, use the default method */
4911 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4912 skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
4914 gpu_reset_for_dev_remove =
4915 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
4916 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4919 * ASIC reset has to be done on all XGMI hive nodes ASAP
4920 * to allow proper links negotiation in FW (within 1 sec)
4922 if (!skip_hw_reset && need_full_reset) {
4923 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4924 /* For XGMI run all resets in parallel to speed up the process */
4925 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4926 tmp_adev->gmc.xgmi.pending_reset = false;
4927 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
4930 r = amdgpu_asic_reset(tmp_adev);
4933 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
4934 r, adev_to_drm(tmp_adev)->unique);
4939 /* For XGMI wait for all resets to complete before proceed */
4941 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4942 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4943 flush_work(&tmp_adev->xgmi_reset_work);
4944 r = tmp_adev->asic_reset_res;
4952 if (!r && amdgpu_ras_intr_triggered()) {
4953 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4954 if (tmp_adev->mmhub.ras && tmp_adev->mmhub.ras->ras_block.hw_ops &&
4955 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
4956 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev);
4959 amdgpu_ras_intr_cleared();
4962 /* Since the mode1 reset affects base ip blocks, the
4963 * phase1 ip blocks need to be resumed. Otherwise there
4964 * will be a BIOS signature error and the psp bootloader
4965 * can't load kdb on the next amdgpu install.
4967 if (gpu_reset_for_dev_remove) {
4968 list_for_each_entry(tmp_adev, device_list_handle, reset_list)
4969 amdgpu_device_ip_resume_phase1(tmp_adev);
4974 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4975 if (need_full_reset) {
4977 r = amdgpu_device_asic_init(tmp_adev);
4979 dev_warn(tmp_adev->dev, "asic atom init failed!");
4981 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
4982 r = amdgpu_amdkfd_resume_iommu(tmp_adev);
4986 r = amdgpu_device_ip_resume_phase1(tmp_adev);
4990 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
4991 #ifdef CONFIG_DEV_COREDUMP
4992 tmp_adev->reset_vram_lost = vram_lost;
4993 memset(&tmp_adev->reset_task_info, 0,
4994 sizeof(tmp_adev->reset_task_info));
4995 if (reset_context->job && reset_context->job->vm)
4996 tmp_adev->reset_task_info =
4997 reset_context->job->vm->task_info;
4998 amdgpu_reset_capture_coredumpm(tmp_adev);
5001 DRM_INFO("VRAM is lost due to GPU reset!\n");
5002 amdgpu_inc_vram_lost(tmp_adev);
5005 r = amdgpu_device_fw_loading(tmp_adev);
5009 r = amdgpu_device_ip_resume_phase2(tmp_adev);
5014 amdgpu_device_fill_reset_magic(tmp_adev);
5017 * Add this ASIC as tracked as reset was already
5018 * complete successfully.
5020 amdgpu_register_gpu_instance(tmp_adev);
5022 if (!reset_context->hive &&
5023 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5024 amdgpu_xgmi_add_device(tmp_adev);
5026 r = amdgpu_device_ip_late_init(tmp_adev);
5030 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false);
5033 * The GPU enters bad state once faulty pages
5034 * by ECC has reached the threshold, and ras
5035 * recovery is scheduled next. So add one check
5036 * here to break recovery if it indeed exceeds
5037 * bad page threshold, and remind user to
5038 * retire this GPU or setting one bigger
5039 * bad_page_threshold value to fix this once
5040 * probing driver again.
5042 if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {
5044 amdgpu_ras_resume(tmp_adev);
5050 /* Update PSP FW topology after reset */
5051 if (reset_context->hive &&
5052 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5053 r = amdgpu_xgmi_update_topology(
5054 reset_context->hive, tmp_adev);
5060 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
5061 r = amdgpu_ib_ring_tests(tmp_adev);
5063 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
5064 need_full_reset = true;
5071 r = amdgpu_device_recover_vram(tmp_adev);
5073 tmp_adev->asic_reset_res = r;
5077 if (need_full_reset)
5078 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5080 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5084 static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)
5087 switch (amdgpu_asic_reset_method(adev)) {
5088 case AMD_RESET_METHOD_MODE1:
5089 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
5091 case AMD_RESET_METHOD_MODE2:
5092 adev->mp1_state = PP_MP1_STATE_RESET;
5095 adev->mp1_state = PP_MP1_STATE_NONE;
5100 static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev)
5102 amdgpu_vf_error_trans_all(adev);
5103 adev->mp1_state = PP_MP1_STATE_NONE;
5106 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
5108 struct pci_dev *p = NULL;
5110 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5111 adev->pdev->bus->number, 1);
5113 pm_runtime_enable(&(p->dev));
5114 pm_runtime_resume(&(p->dev));
5120 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
5122 enum amd_reset_method reset_method;
5123 struct pci_dev *p = NULL;
5127 * For now, only BACO and mode1 reset are confirmed
5128 * to suffer the audio issue without proper suspended.
5130 reset_method = amdgpu_asic_reset_method(adev);
5131 if ((reset_method != AMD_RESET_METHOD_BACO) &&
5132 (reset_method != AMD_RESET_METHOD_MODE1))
5135 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5136 adev->pdev->bus->number, 1);
5140 expires = pm_runtime_autosuspend_expiration(&(p->dev));
5143 * If we cannot get the audio device autosuspend delay,
5144 * a fixed 4S interval will be used. Considering 3S is
5145 * the audio controller default autosuspend delay setting.
5146 * 4S used here is guaranteed to cover that.
5148 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
5150 while (!pm_runtime_status_suspended(&(p->dev))) {
5151 if (!pm_runtime_suspend(&(p->dev)))
5154 if (expires < ktime_get_mono_fast_ns()) {
5155 dev_warn(adev->dev, "failed to suspend display audio\n");
5157 /* TODO: abort the succeeding gpu reset? */
5162 pm_runtime_disable(&(p->dev));
5168 static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
5170 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
5172 #if defined(CONFIG_DEBUG_FS)
5173 if (!amdgpu_sriov_vf(adev))
5174 cancel_work(&adev->reset_work);
5178 cancel_work(&adev->kfd.reset_work);
5180 if (amdgpu_sriov_vf(adev))
5181 cancel_work(&adev->virt.flr_work);
5183 if (con && adev->ras_enabled)
5184 cancel_work(&con->recovery_work);
5189 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
5191 * @adev: amdgpu_device pointer
5192 * @job: which job trigger hang
5193 * @reset_context: amdgpu reset context pointer
5195 * Attempt to reset the GPU if it has hung (all asics).
5196 * Attempt to do soft-reset or full-reset and reinitialize Asic
5197 * Returns 0 for success or an error on failure.
5200 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5201 struct amdgpu_job *job,
5202 struct amdgpu_reset_context *reset_context)
5204 struct list_head device_list, *device_list_handle = NULL;
5205 bool job_signaled = false;
5206 struct amdgpu_hive_info *hive = NULL;
5207 struct amdgpu_device *tmp_adev = NULL;
5209 bool need_emergency_restart = false;
5210 bool audio_suspended = false;
5211 bool gpu_reset_for_dev_remove = false;
5213 gpu_reset_for_dev_remove =
5214 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
5215 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5218 * Special case: RAS triggered and full reset isn't supported
5220 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
5223 * Flush RAM to disk so that after reboot
5224 * the user can read log and see why the system rebooted.
5226 if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) {
5227 DRM_WARN("Emergency reboot.");
5230 emergency_restart();
5233 dev_info(adev->dev, "GPU %s begin!\n",
5234 need_emergency_restart ? "jobs stop":"reset");
5236 if (!amdgpu_sriov_vf(adev))
5237 hive = amdgpu_get_xgmi_hive(adev);
5239 mutex_lock(&hive->hive_lock);
5241 reset_context->job = job;
5242 reset_context->hive = hive;
5244 * Build list of devices to reset.
5245 * In case we are in XGMI hive mode, resort the device list
5246 * to put adev in the 1st position.
5248 INIT_LIST_HEAD(&device_list);
5249 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) {
5250 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
5251 list_add_tail(&tmp_adev->reset_list, &device_list);
5252 if (gpu_reset_for_dev_remove && adev->shutdown)
5253 tmp_adev->shutdown = true;
5255 if (!list_is_first(&adev->reset_list, &device_list))
5256 list_rotate_to_front(&adev->reset_list, &device_list);
5257 device_list_handle = &device_list;
5259 list_add_tail(&adev->reset_list, &device_list);
5260 device_list_handle = &device_list;
5263 /* We need to lock reset domain only once both for XGMI and single device */
5264 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5266 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5268 /* block all schedulers and reset given job's ring */
5269 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5271 amdgpu_device_set_mp1_state(tmp_adev);
5274 * Try to put the audio codec into suspend state
5275 * before gpu reset started.
5277 * Due to the power domain of the graphics device
5278 * is shared with AZ power domain. Without this,
5279 * we may change the audio hardware from behind
5280 * the audio driver's back. That will trigger
5281 * some audio codec errors.
5283 if (!amdgpu_device_suspend_display_audio(tmp_adev))
5284 audio_suspended = true;
5286 amdgpu_ras_set_error_query_ready(tmp_adev, false);
5288 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
5290 if (!amdgpu_sriov_vf(tmp_adev))
5291 amdgpu_amdkfd_pre_reset(tmp_adev);
5294 * Mark these ASICs to be reseted as untracked first
5295 * And add them back after reset completed
5297 amdgpu_unregister_gpu_instance(tmp_adev);
5299 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
5301 /* disable ras on ALL IPs */
5302 if (!need_emergency_restart &&
5303 amdgpu_device_ip_need_full_reset(tmp_adev))
5304 amdgpu_ras_suspend(tmp_adev);
5306 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5307 struct amdgpu_ring *ring = tmp_adev->rings[i];
5309 if (!ring || !ring->sched.thread)
5312 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
5314 if (need_emergency_restart)
5315 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
5317 atomic_inc(&tmp_adev->gpu_reset_counter);
5320 if (need_emergency_restart)
5321 goto skip_sched_resume;
5324 * Must check guilty signal here since after this point all old
5325 * HW fences are force signaled.
5327 * job->base holds a reference to parent fence
5329 if (job && dma_fence_is_signaled(&job->hw_fence)) {
5330 job_signaled = true;
5331 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
5335 retry: /* Rest of adevs pre asic reset from XGMI hive. */
5336 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5337 if (gpu_reset_for_dev_remove) {
5338 /* Workaroud for ASICs need to disable SMC first */
5339 amdgpu_device_smu_fini_early(tmp_adev);
5341 r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
5342 /*TODO Should we stop ?*/
5344 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
5345 r, adev_to_drm(tmp_adev)->unique);
5346 tmp_adev->asic_reset_res = r;
5350 * Drop all pending non scheduler resets. Scheduler resets
5351 * were already dropped during drm_sched_stop
5353 amdgpu_device_stop_pending_resets(tmp_adev);
5356 /* Actual ASIC resets if needed.*/
5357 /* Host driver will handle XGMI hive reset for SRIOV */
5358 if (amdgpu_sriov_vf(adev)) {
5359 r = amdgpu_device_reset_sriov(adev, job ? false : true);
5361 adev->asic_reset_res = r;
5363 /* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */
5364 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||
5365 adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3))
5366 amdgpu_ras_resume(adev);
5368 r = amdgpu_do_asic_reset(device_list_handle, reset_context);
5369 if (r && r == -EAGAIN)
5372 if (!r && gpu_reset_for_dev_remove)
5378 /* Post ASIC reset for all devs .*/
5379 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5381 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5382 struct amdgpu_ring *ring = tmp_adev->rings[i];
5384 if (!ring || !ring->sched.thread)
5387 drm_sched_start(&ring->sched, true);
5390 if (adev->enable_mes && adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))
5391 amdgpu_mes_self_test(tmp_adev);
5393 if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) {
5394 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
5397 if (tmp_adev->asic_reset_res)
5398 r = tmp_adev->asic_reset_res;
5400 tmp_adev->asic_reset_res = 0;
5403 /* bad news, how to tell it to userspace ? */
5404 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
5405 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
5407 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
5408 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
5409 DRM_WARN("smart shift update failed\n");
5414 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5415 /* unlock kfd: SRIOV would do it separately */
5416 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
5417 amdgpu_amdkfd_post_reset(tmp_adev);
5419 /* kfd_post_reset will do nothing if kfd device is not initialized,
5420 * need to bring up kfd here if it's not be initialized before
5422 if (!adev->kfd.init_complete)
5423 amdgpu_amdkfd_device_init(adev);
5425 if (audio_suspended)
5426 amdgpu_device_resume_display_audio(tmp_adev);
5428 amdgpu_device_unset_mp1_state(tmp_adev);
5430 amdgpu_ras_set_error_query_ready(tmp_adev, true);
5434 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5436 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
5439 mutex_unlock(&hive->hive_lock);
5440 amdgpu_put_xgmi_hive(hive);
5444 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
5446 atomic_set(&adev->reset_domain->reset_res, r);
5451 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
5453 * @adev: amdgpu_device pointer
5455 * Fetchs and stores in the driver the PCIE capabilities (gen speed
5456 * and lanes) of the slot the device is in. Handles APUs and
5457 * virtualized environments where PCIE config space may not be available.
5459 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
5461 struct pci_dev *pdev;
5462 enum pci_bus_speed speed_cap, platform_speed_cap;
5463 enum pcie_link_width platform_link_width;
5465 if (amdgpu_pcie_gen_cap)
5466 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
5468 if (amdgpu_pcie_lane_cap)
5469 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
5471 /* covers APUs as well */
5472 if (pci_is_root_bus(adev->pdev->bus)) {
5473 if (adev->pm.pcie_gen_mask == 0)
5474 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
5475 if (adev->pm.pcie_mlw_mask == 0)
5476 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
5480 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
5483 pcie_bandwidth_available(adev->pdev, NULL,
5484 &platform_speed_cap, &platform_link_width);
5486 if (adev->pm.pcie_gen_mask == 0) {
5489 speed_cap = pcie_get_speed_cap(pdev);
5490 if (speed_cap == PCI_SPEED_UNKNOWN) {
5491 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5492 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5493 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5495 if (speed_cap == PCIE_SPEED_32_0GT)
5496 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5497 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5498 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5499 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5500 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
5501 else if (speed_cap == PCIE_SPEED_16_0GT)
5502 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5503 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5504 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5505 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
5506 else if (speed_cap == PCIE_SPEED_8_0GT)
5507 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5508 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5509 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5510 else if (speed_cap == PCIE_SPEED_5_0GT)
5511 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5512 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
5514 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
5517 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
5518 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5519 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5521 if (platform_speed_cap == PCIE_SPEED_32_0GT)
5522 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5523 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5524 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5525 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5526 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
5527 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
5528 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5529 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5530 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5531 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
5532 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
5533 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5534 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5535 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
5536 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
5537 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5538 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5540 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
5544 if (adev->pm.pcie_mlw_mask == 0) {
5545 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
5546 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
5548 switch (platform_link_width) {
5550 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
5551 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5552 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5553 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5554 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5555 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5556 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5559 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5560 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5561 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5562 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5563 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5564 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5567 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5568 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5569 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5570 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5571 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5574 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5575 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5576 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5577 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5580 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5581 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5582 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5585 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5586 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5589 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
5599 * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
5601 * @adev: amdgpu_device pointer
5602 * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
5604 * Return true if @peer_adev can access (DMA) @adev through the PCIe
5605 * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
5608 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
5609 struct amdgpu_device *peer_adev)
5611 #ifdef CONFIG_HSA_AMD_P2P
5612 uint64_t address_mask = peer_adev->dev->dma_mask ?
5613 ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
5614 resource_size_t aper_limit =
5615 adev->gmc.aper_base + adev->gmc.aper_size - 1;
5617 !adev->gmc.xgmi.connected_to_cpu &&
5618 !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
5620 return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
5621 adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
5622 !(adev->gmc.aper_base & address_mask ||
5623 aper_limit & address_mask));
5629 int amdgpu_device_baco_enter(struct drm_device *dev)
5631 struct amdgpu_device *adev = drm_to_adev(dev);
5632 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5634 if (!amdgpu_device_supports_baco(dev))
5637 if (ras && adev->ras_enabled &&
5638 adev->nbio.funcs->enable_doorbell_interrupt)
5639 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
5641 return amdgpu_dpm_baco_enter(adev);
5644 int amdgpu_device_baco_exit(struct drm_device *dev)
5646 struct amdgpu_device *adev = drm_to_adev(dev);
5647 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5650 if (!amdgpu_device_supports_baco(dev))
5653 ret = amdgpu_dpm_baco_exit(adev);
5657 if (ras && adev->ras_enabled &&
5658 adev->nbio.funcs->enable_doorbell_interrupt)
5659 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
5661 if (amdgpu_passthrough(adev) &&
5662 adev->nbio.funcs->clear_doorbell_interrupt)
5663 adev->nbio.funcs->clear_doorbell_interrupt(adev);
5669 * amdgpu_pci_error_detected - Called when a PCI error is detected.
5670 * @pdev: PCI device struct
5671 * @state: PCI channel state
5673 * Description: Called when a PCI error is detected.
5675 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
5677 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5679 struct drm_device *dev = pci_get_drvdata(pdev);
5680 struct amdgpu_device *adev = drm_to_adev(dev);
5683 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
5685 if (adev->gmc.xgmi.num_physical_nodes > 1) {
5686 DRM_WARN("No support for XGMI hive yet...");
5687 return PCI_ERS_RESULT_DISCONNECT;
5690 adev->pci_channel_state = state;
5693 case pci_channel_io_normal:
5694 return PCI_ERS_RESULT_CAN_RECOVER;
5695 /* Fatal error, prepare for slot reset */
5696 case pci_channel_io_frozen:
5698 * Locking adev->reset_domain->sem will prevent any external access
5699 * to GPU during PCI error recovery
5701 amdgpu_device_lock_reset_domain(adev->reset_domain);
5702 amdgpu_device_set_mp1_state(adev);
5705 * Block any work scheduling as we do for regular GPU reset
5706 * for the duration of the recovery
5708 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5709 struct amdgpu_ring *ring = adev->rings[i];
5711 if (!ring || !ring->sched.thread)
5714 drm_sched_stop(&ring->sched, NULL);
5716 atomic_inc(&adev->gpu_reset_counter);
5717 return PCI_ERS_RESULT_NEED_RESET;
5718 case pci_channel_io_perm_failure:
5719 /* Permanent error, prepare for device removal */
5720 return PCI_ERS_RESULT_DISCONNECT;
5723 return PCI_ERS_RESULT_NEED_RESET;
5727 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
5728 * @pdev: pointer to PCI device
5730 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
5733 DRM_INFO("PCI error: mmio enabled callback!!\n");
5735 /* TODO - dump whatever for debugging purposes */
5737 /* This called only if amdgpu_pci_error_detected returns
5738 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
5739 * works, no need to reset slot.
5742 return PCI_ERS_RESULT_RECOVERED;
5746 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
5747 * @pdev: PCI device struct
5749 * Description: This routine is called by the pci error recovery
5750 * code after the PCI slot has been reset, just before we
5751 * should resume normal operations.
5753 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
5755 struct drm_device *dev = pci_get_drvdata(pdev);
5756 struct amdgpu_device *adev = drm_to_adev(dev);
5758 struct amdgpu_reset_context reset_context;
5760 struct list_head device_list;
5762 DRM_INFO("PCI error: slot reset callback!!\n");
5764 memset(&reset_context, 0, sizeof(reset_context));
5766 INIT_LIST_HEAD(&device_list);
5767 list_add_tail(&adev->reset_list, &device_list);
5769 /* wait for asic to come out of reset */
5772 /* Restore PCI confspace */
5773 amdgpu_device_load_pci_state(pdev);
5775 /* confirm ASIC came out of reset */
5776 for (i = 0; i < adev->usec_timeout; i++) {
5777 memsize = amdgpu_asic_get_config_memsize(adev);
5779 if (memsize != 0xffffffff)
5783 if (memsize == 0xffffffff) {
5788 reset_context.method = AMD_RESET_METHOD_NONE;
5789 reset_context.reset_req_dev = adev;
5790 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
5791 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
5793 adev->no_hw_access = true;
5794 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
5795 adev->no_hw_access = false;
5799 r = amdgpu_do_asic_reset(&device_list, &reset_context);
5803 if (amdgpu_device_cache_pci_state(adev->pdev))
5804 pci_restore_state(adev->pdev);
5806 DRM_INFO("PCIe error recovery succeeded\n");
5808 DRM_ERROR("PCIe error recovery failed, err:%d", r);
5809 amdgpu_device_unset_mp1_state(adev);
5810 amdgpu_device_unlock_reset_domain(adev->reset_domain);
5813 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
5817 * amdgpu_pci_resume() - resume normal ops after PCI reset
5818 * @pdev: pointer to PCI device
5820 * Called when the error recovery driver tells us that its
5821 * OK to resume normal operation.
5823 void amdgpu_pci_resume(struct pci_dev *pdev)
5825 struct drm_device *dev = pci_get_drvdata(pdev);
5826 struct amdgpu_device *adev = drm_to_adev(dev);
5830 DRM_INFO("PCI error: resume callback!!\n");
5832 /* Only continue execution for the case of pci_channel_io_frozen */
5833 if (adev->pci_channel_state != pci_channel_io_frozen)
5836 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5837 struct amdgpu_ring *ring = adev->rings[i];
5839 if (!ring || !ring->sched.thread)
5842 drm_sched_start(&ring->sched, true);
5845 amdgpu_device_unset_mp1_state(adev);
5846 amdgpu_device_unlock_reset_domain(adev->reset_domain);
5849 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
5851 struct drm_device *dev = pci_get_drvdata(pdev);
5852 struct amdgpu_device *adev = drm_to_adev(dev);
5855 r = pci_save_state(pdev);
5857 kfree(adev->pci_state);
5859 adev->pci_state = pci_store_saved_state(pdev);
5861 if (!adev->pci_state) {
5862 DRM_ERROR("Failed to store PCI saved state");
5866 DRM_WARN("Failed to save PCI state, err:%d\n", r);
5873 bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
5875 struct drm_device *dev = pci_get_drvdata(pdev);
5876 struct amdgpu_device *adev = drm_to_adev(dev);
5879 if (!adev->pci_state)
5882 r = pci_load_saved_state(pdev, adev->pci_state);
5885 pci_restore_state(pdev);
5887 DRM_WARN("Failed to load PCI state, err:%d\n", r);
5894 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
5895 struct amdgpu_ring *ring)
5897 #ifdef CONFIG_X86_64
5898 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
5901 if (adev->gmc.xgmi.connected_to_cpu)
5904 if (ring && ring->funcs->emit_hdp_flush)
5905 amdgpu_ring_emit_hdp_flush(ring);
5907 amdgpu_asic_flush_hdp(adev, ring);
5910 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
5911 struct amdgpu_ring *ring)
5913 #ifdef CONFIG_X86_64
5914 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
5917 if (adev->gmc.xgmi.connected_to_cpu)
5920 amdgpu_asic_invalidate_hdp(adev, ring);
5923 int amdgpu_in_reset(struct amdgpu_device *adev)
5925 return atomic_read(&adev->reset_domain->in_gpu_reset);
5929 * amdgpu_device_halt() - bring hardware to some kind of halt state
5931 * @adev: amdgpu_device pointer
5933 * Bring hardware to some kind of halt state so that no one can touch it
5934 * any more. It will help to maintain error context when error occurred.
5935 * Compare to a simple hang, the system will keep stable at least for SSH
5936 * access. Then it should be trivial to inspect the hardware state and
5937 * see what's going on. Implemented as following:
5939 * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc),
5940 * clears all CPU mappings to device, disallows remappings through page faults
5941 * 2. amdgpu_irq_disable_all() disables all interrupts
5942 * 3. amdgpu_fence_driver_hw_fini() signals all HW fences
5943 * 4. set adev->no_hw_access to avoid potential crashes after setp 5
5944 * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings
5945 * 6. pci_disable_device() and pci_wait_for_pending_transaction()
5946 * flush any in flight DMA operations
5948 void amdgpu_device_halt(struct amdgpu_device *adev)
5950 struct pci_dev *pdev = adev->pdev;
5951 struct drm_device *ddev = adev_to_drm(adev);
5953 drm_dev_unplug(ddev);
5955 amdgpu_irq_disable_all(adev);
5957 amdgpu_fence_driver_hw_fini(adev);
5959 adev->no_hw_access = true;
5961 amdgpu_device_unmap_mmio(adev);
5963 pci_disable_device(pdev);
5964 pci_wait_for_pending_transaction(pdev);
5967 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
5970 unsigned long flags, address, data;
5973 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
5974 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
5976 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
5977 WREG32(address, reg * 4);
5978 (void)RREG32(address);
5980 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
5984 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
5987 unsigned long flags, address, data;
5989 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
5990 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
5992 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
5993 WREG32(address, reg * 4);
5994 (void)RREG32(address);
5997 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6001 * amdgpu_device_switch_gang - switch to a new gang
6002 * @adev: amdgpu_device pointer
6003 * @gang: the gang to switch to
6005 * Try to switch to a new gang.
6006 * Returns: NULL if we switched to the new gang or a reference to the current
6009 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
6010 struct dma_fence *gang)
6012 struct dma_fence *old = NULL;
6017 old = dma_fence_get_rcu_safe(&adev->gang_submit);
6023 if (!dma_fence_is_signaled(old))
6026 } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit,
6033 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
6035 switch (adev->asic_type) {
6036 #ifdef CONFIG_DRM_AMDGPU_SI
6040 /* chips with no display hardware */
6042 #ifdef CONFIG_DRM_AMDGPU_SI
6048 #ifdef CONFIG_DRM_AMDGPU_CIK
6057 case CHIP_POLARIS10:
6058 case CHIP_POLARIS11:
6059 case CHIP_POLARIS12:
6063 /* chips with display hardware */
6067 if (!adev->ip_versions[DCE_HWIP][0] ||
6068 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))