2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/power_supply.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/console.h>
32 #include <linux/slab.h>
33 #include <linux/iommu.h>
34 #include <linux/pci.h>
35 #include <linux/devcoredump.h>
36 #include <generated/utsrelease.h>
37 #include <linux/pci-p2pdma.h>
38 #include <linux/apple-gmux.h>
40 #include <drm/drm_aperture.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_fb_helper.h>
44 #include <drm/drm_probe_helper.h>
45 #include <drm/amdgpu_drm.h>
46 #include <linux/vgaarb.h>
47 #include <linux/vga_switcheroo.h>
48 #include <linux/efi.h>
50 #include "amdgpu_trace.h"
51 #include "amdgpu_i2c.h"
53 #include "amdgpu_atombios.h"
54 #include "amdgpu_atomfirmware.h"
56 #ifdef CONFIG_DRM_AMDGPU_SI
59 #ifdef CONFIG_DRM_AMDGPU_CIK
65 #include "bif/bif_4_1_d.h"
66 #include <linux/firmware.h>
67 #include "amdgpu_vf_error.h"
69 #include "amdgpu_amdkfd.h"
70 #include "amdgpu_pm.h"
72 #include "amdgpu_xgmi.h"
73 #include "amdgpu_ras.h"
74 #include "amdgpu_pmu.h"
75 #include "amdgpu_fru_eeprom.h"
76 #include "amdgpu_reset.h"
78 #include <linux/suspend.h>
79 #include <drm/task_barrier.h>
80 #include <linux/pm_runtime.h>
82 #include <drm/drm_drv.h>
84 #if IS_ENABLED(CONFIG_X86)
85 #include <asm/intel-family.h>
88 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
89 MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
90 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
91 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
92 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
93 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
94 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
96 #define AMDGPU_RESUME_MS 2000
97 #define AMDGPU_MAX_RETRY_LIMIT 2
98 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
100 static const struct drm_driver amdgpu_kms_driver;
102 const char *amdgpu_asic_name[] = {
144 * DOC: pcie_replay_count
146 * The amdgpu driver provides a sysfs API for reporting the total number
147 * of PCIe replays (NAKs)
148 * The file pcie_replay_count is used for this and returns the total
149 * number of replays as a sum of the NAKs generated and NAKs received
152 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
153 struct device_attribute *attr, char *buf)
155 struct drm_device *ddev = dev_get_drvdata(dev);
156 struct amdgpu_device *adev = drm_to_adev(ddev);
157 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
159 return sysfs_emit(buf, "%llu\n", cnt);
162 static DEVICE_ATTR(pcie_replay_count, 0444,
163 amdgpu_device_get_pcie_replay_count, NULL);
165 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
170 * The amdgpu driver provides a sysfs API for reporting the product name
172 * The file product_name is used for this and returns the product name
173 * as returned from the FRU.
174 * NOTE: This is only available for certain server cards
177 static ssize_t amdgpu_device_get_product_name(struct device *dev,
178 struct device_attribute *attr, char *buf)
180 struct drm_device *ddev = dev_get_drvdata(dev);
181 struct amdgpu_device *adev = drm_to_adev(ddev);
183 return sysfs_emit(buf, "%s\n", adev->product_name);
186 static DEVICE_ATTR(product_name, 0444,
187 amdgpu_device_get_product_name, NULL);
190 * DOC: product_number
192 * The amdgpu driver provides a sysfs API for reporting the part number
194 * The file product_number is used for this and returns the part number
195 * as returned from the FRU.
196 * NOTE: This is only available for certain server cards
199 static ssize_t amdgpu_device_get_product_number(struct device *dev,
200 struct device_attribute *attr, char *buf)
202 struct drm_device *ddev = dev_get_drvdata(dev);
203 struct amdgpu_device *adev = drm_to_adev(ddev);
205 return sysfs_emit(buf, "%s\n", adev->product_number);
208 static DEVICE_ATTR(product_number, 0444,
209 amdgpu_device_get_product_number, NULL);
214 * The amdgpu driver provides a sysfs API for reporting the serial number
216 * The file serial_number is used for this and returns the serial number
217 * as returned from the FRU.
218 * NOTE: This is only available for certain server cards
221 static ssize_t amdgpu_device_get_serial_number(struct device *dev,
222 struct device_attribute *attr, char *buf)
224 struct drm_device *ddev = dev_get_drvdata(dev);
225 struct amdgpu_device *adev = drm_to_adev(ddev);
227 return sysfs_emit(buf, "%s\n", adev->serial);
230 static DEVICE_ATTR(serial_number, 0444,
231 amdgpu_device_get_serial_number, NULL);
234 * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control
236 * @dev: drm_device pointer
238 * Returns true if the device is a dGPU with ATPX power control,
239 * otherwise return false.
241 bool amdgpu_device_supports_px(struct drm_device *dev)
243 struct amdgpu_device *adev = drm_to_adev(dev);
245 if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())
251 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
253 * @dev: drm_device pointer
255 * Returns true if the device is a dGPU with ACPI power control,
256 * otherwise return false.
258 bool amdgpu_device_supports_boco(struct drm_device *dev)
260 struct amdgpu_device *adev = drm_to_adev(dev);
263 ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))
269 * amdgpu_device_supports_baco - Does the device support BACO
271 * @dev: drm_device pointer
273 * Returns true if the device supporte BACO,
274 * otherwise return false.
276 bool amdgpu_device_supports_baco(struct drm_device *dev)
278 struct amdgpu_device *adev = drm_to_adev(dev);
280 return amdgpu_asic_supports_baco(adev);
284 * amdgpu_device_supports_smart_shift - Is the device dGPU with
285 * smart shift support
287 * @dev: drm_device pointer
289 * Returns true if the device is a dGPU with Smart Shift support,
290 * otherwise returns false.
292 bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
294 return (amdgpu_device_supports_boco(dev) &&
295 amdgpu_acpi_is_power_shift_control_supported());
299 * VRAM access helper functions
303 * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
305 * @adev: amdgpu_device pointer
306 * @pos: offset of the buffer in vram
307 * @buf: virtual address of the buffer in system memory
308 * @size: read/write size, sizeof(@buf) must > @size
309 * @write: true - write to vram, otherwise - read from vram
311 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
312 void *buf, size_t size, bool write)
315 uint32_t hi = ~0, tmp = 0;
316 uint32_t *data = buf;
320 if (!drm_dev_enter(adev_to_drm(adev), &idx))
323 BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
325 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
326 for (last = pos + size; pos < last; pos += 4) {
329 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
331 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
335 WREG32_NO_KIQ(mmMM_DATA, *data++);
337 *data++ = RREG32_NO_KIQ(mmMM_DATA);
340 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
345 * amdgpu_device_aper_access - access vram by vram aperature
347 * @adev: amdgpu_device pointer
348 * @pos: offset of the buffer in vram
349 * @buf: virtual address of the buffer in system memory
350 * @size: read/write size, sizeof(@buf) must > @size
351 * @write: true - write to vram, otherwise - read from vram
353 * The return value means how many bytes have been transferred.
355 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
356 void *buf, size_t size, bool write)
363 if (!adev->mman.aper_base_kaddr)
366 last = min(pos + size, adev->gmc.visible_vram_size);
368 addr = adev->mman.aper_base_kaddr + pos;
372 memcpy_toio(addr, buf, count);
374 amdgpu_device_flush_hdp(adev, NULL);
376 amdgpu_device_invalidate_hdp(adev, NULL);
378 memcpy_fromio(buf, addr, count);
390 * amdgpu_device_vram_access - read/write a buffer in vram
392 * @adev: amdgpu_device pointer
393 * @pos: offset of the buffer in vram
394 * @buf: virtual address of the buffer in system memory
395 * @size: read/write size, sizeof(@buf) must > @size
396 * @write: true - write to vram, otherwise - read from vram
398 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
399 void *buf, size_t size, bool write)
403 /* try to using vram apreature to access vram first */
404 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
407 /* using MM to access rest vram */
410 amdgpu_device_mm_access(adev, pos, buf, size, write);
415 * register access helper functions.
418 /* Check if hw access should be skipped because of hotplug or device error */
419 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
421 if (adev->no_hw_access)
424 #ifdef CONFIG_LOCKDEP
426 * This is a bit complicated to understand, so worth a comment. What we assert
427 * here is that the GPU reset is not running on another thread in parallel.
429 * For this we trylock the read side of the reset semaphore, if that succeeds
430 * we know that the reset is not running in paralell.
432 * If the trylock fails we assert that we are either already holding the read
433 * side of the lock or are the reset thread itself and hold the write side of
437 if (down_read_trylock(&adev->reset_domain->sem))
438 up_read(&adev->reset_domain->sem);
440 lockdep_assert_held(&adev->reset_domain->sem);
447 * amdgpu_device_rreg - read a memory mapped IO or indirect register
449 * @adev: amdgpu_device pointer
450 * @reg: dword aligned register offset
451 * @acc_flags: access flags which require special behavior
453 * Returns the 32 bit value from the offset specified.
455 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
456 uint32_t reg, uint32_t acc_flags)
460 if (amdgpu_device_skip_hw_access(adev))
463 if ((reg * 4) < adev->rmmio_size) {
464 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
465 amdgpu_sriov_runtime(adev) &&
466 down_read_trylock(&adev->reset_domain->sem)) {
467 ret = amdgpu_kiq_rreg(adev, reg);
468 up_read(&adev->reset_domain->sem);
470 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
473 ret = adev->pcie_rreg(adev, reg * 4);
476 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
482 * MMIO register read with bytes helper functions
483 * @offset:bytes offset from MMIO start
487 * amdgpu_mm_rreg8 - read a memory mapped IO register
489 * @adev: amdgpu_device pointer
490 * @offset: byte aligned register offset
492 * Returns the 8 bit value from the offset specified.
494 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
496 if (amdgpu_device_skip_hw_access(adev))
499 if (offset < adev->rmmio_size)
500 return (readb(adev->rmmio + offset));
505 * MMIO register write with bytes helper functions
506 * @offset:bytes offset from MMIO start
507 * @value: the value want to be written to the register
511 * amdgpu_mm_wreg8 - read a memory mapped IO register
513 * @adev: amdgpu_device pointer
514 * @offset: byte aligned register offset
515 * @value: 8 bit value to write
517 * Writes the value specified to the offset specified.
519 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
521 if (amdgpu_device_skip_hw_access(adev))
524 if (offset < adev->rmmio_size)
525 writeb(value, adev->rmmio + offset);
531 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
533 * @adev: amdgpu_device pointer
534 * @reg: dword aligned register offset
535 * @v: 32 bit value to write to the register
536 * @acc_flags: access flags which require special behavior
538 * Writes the value specified to the offset specified.
540 void amdgpu_device_wreg(struct amdgpu_device *adev,
541 uint32_t reg, uint32_t v,
544 if (amdgpu_device_skip_hw_access(adev))
547 if ((reg * 4) < adev->rmmio_size) {
548 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
549 amdgpu_sriov_runtime(adev) &&
550 down_read_trylock(&adev->reset_domain->sem)) {
551 amdgpu_kiq_wreg(adev, reg, v);
552 up_read(&adev->reset_domain->sem);
554 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
557 adev->pcie_wreg(adev, reg * 4, v);
560 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
564 * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range
566 * @adev: amdgpu_device pointer
567 * @reg: mmio/rlc register
570 * this function is invoked only for the debugfs register access
572 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
573 uint32_t reg, uint32_t v,
576 if (amdgpu_device_skip_hw_access(adev))
579 if (amdgpu_sriov_fullaccess(adev) &&
580 adev->gfx.rlc.funcs &&
581 adev->gfx.rlc.funcs->is_rlcg_access_range) {
582 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
583 return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id);
584 } else if ((reg * 4) >= adev->rmmio_size) {
585 adev->pcie_wreg(adev, reg * 4, v);
587 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
592 * amdgpu_device_indirect_rreg - read an indirect register
594 * @adev: amdgpu_device pointer
595 * @reg_addr: indirect register address to read from
597 * Returns the value of indirect register @reg_addr
599 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
602 unsigned long flags, pcie_index, pcie_data;
603 void __iomem *pcie_index_offset;
604 void __iomem *pcie_data_offset;
607 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
608 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
610 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
611 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
612 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
614 writel(reg_addr, pcie_index_offset);
615 readl(pcie_index_offset);
616 r = readl(pcie_data_offset);
617 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
622 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
625 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
627 void __iomem *pcie_index_offset;
628 void __iomem *pcie_index_hi_offset;
629 void __iomem *pcie_data_offset;
631 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
632 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
633 if (adev->nbio.funcs->get_pcie_index_hi_offset)
634 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
638 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
639 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
640 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
641 if (pcie_index_hi != 0)
642 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
645 writel(reg_addr, pcie_index_offset);
646 readl(pcie_index_offset);
647 if (pcie_index_hi != 0) {
648 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
649 readl(pcie_index_hi_offset);
651 r = readl(pcie_data_offset);
653 /* clear the high bits */
654 if (pcie_index_hi != 0) {
655 writel(0, pcie_index_hi_offset);
656 readl(pcie_index_hi_offset);
659 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
665 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
667 * @adev: amdgpu_device pointer
668 * @reg_addr: indirect register address to read from
670 * Returns the value of indirect register @reg_addr
672 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
675 unsigned long flags, pcie_index, pcie_data;
676 void __iomem *pcie_index_offset;
677 void __iomem *pcie_data_offset;
680 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
681 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
683 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
684 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
685 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
687 /* read low 32 bits */
688 writel(reg_addr, pcie_index_offset);
689 readl(pcie_index_offset);
690 r = readl(pcie_data_offset);
691 /* read high 32 bits */
692 writel(reg_addr + 4, pcie_index_offset);
693 readl(pcie_index_offset);
694 r |= ((u64)readl(pcie_data_offset) << 32);
695 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
701 * amdgpu_device_indirect_wreg - write an indirect register address
703 * @adev: amdgpu_device pointer
704 * @reg_addr: indirect register offset
705 * @reg_data: indirect register data
708 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
709 u32 reg_addr, u32 reg_data)
711 unsigned long flags, pcie_index, pcie_data;
712 void __iomem *pcie_index_offset;
713 void __iomem *pcie_data_offset;
715 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
716 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
718 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
719 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
720 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
722 writel(reg_addr, pcie_index_offset);
723 readl(pcie_index_offset);
724 writel(reg_data, pcie_data_offset);
725 readl(pcie_data_offset);
726 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
729 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
730 u64 reg_addr, u32 reg_data)
732 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
733 void __iomem *pcie_index_offset;
734 void __iomem *pcie_index_hi_offset;
735 void __iomem *pcie_data_offset;
737 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
738 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
739 if (adev->nbio.funcs->get_pcie_index_hi_offset)
740 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
744 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
745 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
746 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
747 if (pcie_index_hi != 0)
748 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
751 writel(reg_addr, pcie_index_offset);
752 readl(pcie_index_offset);
753 if (pcie_index_hi != 0) {
754 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
755 readl(pcie_index_hi_offset);
757 writel(reg_data, pcie_data_offset);
758 readl(pcie_data_offset);
760 /* clear the high bits */
761 if (pcie_index_hi != 0) {
762 writel(0, pcie_index_hi_offset);
763 readl(pcie_index_hi_offset);
766 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
770 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
772 * @adev: amdgpu_device pointer
773 * @reg_addr: indirect register offset
774 * @reg_data: indirect register data
777 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
778 u32 reg_addr, u64 reg_data)
780 unsigned long flags, pcie_index, pcie_data;
781 void __iomem *pcie_index_offset;
782 void __iomem *pcie_data_offset;
784 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
785 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
787 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
788 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
789 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
791 /* write low 32 bits */
792 writel(reg_addr, pcie_index_offset);
793 readl(pcie_index_offset);
794 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
795 readl(pcie_data_offset);
796 /* write high 32 bits */
797 writel(reg_addr + 4, pcie_index_offset);
798 readl(pcie_index_offset);
799 writel((u32)(reg_data >> 32), pcie_data_offset);
800 readl(pcie_data_offset);
801 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
805 * amdgpu_device_get_rev_id - query device rev_id
807 * @adev: amdgpu_device pointer
809 * Return device rev_id
811 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev)
813 return adev->nbio.funcs->get_rev_id(adev);
817 * amdgpu_invalid_rreg - dummy reg read function
819 * @adev: amdgpu_device pointer
820 * @reg: offset of register
822 * Dummy register read function. Used for register blocks
823 * that certain asics don't have (all asics).
824 * Returns the value in the register.
826 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
828 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
833 static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg)
835 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
841 * amdgpu_invalid_wreg - dummy reg write function
843 * @adev: amdgpu_device pointer
844 * @reg: offset of register
845 * @v: value to write to the register
847 * Dummy register read function. Used for register blocks
848 * that certain asics don't have (all asics).
850 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
852 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
857 static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)
859 DRM_ERROR("Invalid callback to write register 0x%llX with 0x%08X\n",
865 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
867 * @adev: amdgpu_device pointer
868 * @reg: offset of register
870 * Dummy register read function. Used for register blocks
871 * that certain asics don't have (all asics).
872 * Returns the value in the register.
874 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
876 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
882 * amdgpu_invalid_wreg64 - dummy reg write function
884 * @adev: amdgpu_device pointer
885 * @reg: offset of register
886 * @v: value to write to the register
888 * Dummy register read function. Used for register blocks
889 * that certain asics don't have (all asics).
891 static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
893 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
899 * amdgpu_block_invalid_rreg - dummy reg read function
901 * @adev: amdgpu_device pointer
902 * @block: offset of instance
903 * @reg: offset of register
905 * Dummy register read function. Used for register blocks
906 * that certain asics don't have (all asics).
907 * Returns the value in the register.
909 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
910 uint32_t block, uint32_t reg)
912 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
919 * amdgpu_block_invalid_wreg - dummy reg write function
921 * @adev: amdgpu_device pointer
922 * @block: offset of instance
923 * @reg: offset of register
924 * @v: value to write to the register
926 * Dummy register read function. Used for register blocks
927 * that certain asics don't have (all asics).
929 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
931 uint32_t reg, uint32_t v)
933 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
939 * amdgpu_device_asic_init - Wrapper for atom asic_init
941 * @adev: amdgpu_device pointer
943 * Does any asic specific work and then calls atom asic init.
945 static int amdgpu_device_asic_init(struct amdgpu_device *adev)
947 amdgpu_asic_pre_asic_init(adev);
949 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) ||
950 adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
951 return amdgpu_atomfirmware_asic_init(adev, true);
953 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
957 * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page
959 * @adev: amdgpu_device pointer
961 * Allocates a scratch page of VRAM for use by various things in the
964 static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev)
966 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
967 AMDGPU_GEM_DOMAIN_VRAM |
968 AMDGPU_GEM_DOMAIN_GTT,
969 &adev->mem_scratch.robj,
970 &adev->mem_scratch.gpu_addr,
971 (void **)&adev->mem_scratch.ptr);
975 * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page
977 * @adev: amdgpu_device pointer
979 * Frees the VRAM scratch page.
981 static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev)
983 amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL);
987 * amdgpu_device_program_register_sequence - program an array of registers.
989 * @adev: amdgpu_device pointer
990 * @registers: pointer to the register array
991 * @array_size: size of the register array
993 * Programs an array or registers with and or masks.
994 * This is a helper for setting golden registers.
996 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
997 const u32 *registers,
998 const u32 array_size)
1000 u32 tmp, reg, and_mask, or_mask;
1006 for (i = 0; i < array_size; i += 3) {
1007 reg = registers[i + 0];
1008 and_mask = registers[i + 1];
1009 or_mask = registers[i + 2];
1011 if (and_mask == 0xffffffff) {
1016 if (adev->family >= AMDGPU_FAMILY_AI)
1017 tmp |= (or_mask & and_mask);
1026 * amdgpu_device_pci_config_reset - reset the GPU
1028 * @adev: amdgpu_device pointer
1030 * Resets the GPU using the pci config reset sequence.
1031 * Only applicable to asics prior to vega10.
1033 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
1035 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
1039 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
1041 * @adev: amdgpu_device pointer
1043 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
1045 int amdgpu_device_pci_reset(struct amdgpu_device *adev)
1047 return pci_reset_function(adev->pdev);
1051 * amdgpu_device_wb_*()
1052 * Writeback is the method by which the GPU updates special pages in memory
1053 * with the status of certain GPU events (fences, ring pointers,etc.).
1057 * amdgpu_device_wb_fini - Disable Writeback and free memory
1059 * @adev: amdgpu_device pointer
1061 * Disables Writeback and frees the Writeback memory (all asics).
1062 * Used at driver shutdown.
1064 static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1066 if (adev->wb.wb_obj) {
1067 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1069 (void **)&adev->wb.wb);
1070 adev->wb.wb_obj = NULL;
1075 * amdgpu_device_wb_init - Init Writeback driver info and allocate memory
1077 * @adev: amdgpu_device pointer
1079 * Initializes writeback and allocates writeback memory (all asics).
1080 * Used at driver startup.
1081 * Returns 0 on success or an -error on failure.
1083 static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1087 if (adev->wb.wb_obj == NULL) {
1088 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1089 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1090 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1091 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1092 (void **)&adev->wb.wb);
1094 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1098 adev->wb.num_wb = AMDGPU_MAX_WB;
1099 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1101 /* clear wb memory */
1102 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1109 * amdgpu_device_wb_get - Allocate a wb entry
1111 * @adev: amdgpu_device pointer
1114 * Allocate a wb slot for use by the driver (all asics).
1115 * Returns 0 on success or -EINVAL on failure.
1117 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1119 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1121 if (offset < adev->wb.num_wb) {
1122 __set_bit(offset, adev->wb.used);
1123 *wb = offset << 3; /* convert to dw offset */
1131 * amdgpu_device_wb_free - Free a wb entry
1133 * @adev: amdgpu_device pointer
1136 * Free a wb slot allocated for use by the driver (all asics)
1138 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1141 if (wb < adev->wb.num_wb)
1142 __clear_bit(wb, adev->wb.used);
1146 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1148 * @adev: amdgpu_device pointer
1150 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1151 * to fail, but if any of the BARs is not accessible after the size we abort
1152 * driver loading by returning -ENODEV.
1154 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1156 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1157 struct pci_bus *root;
1158 struct resource *res;
1163 if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
1167 if (amdgpu_sriov_vf(adev))
1170 /* skip if the bios has already enabled large BAR */
1171 if (adev->gmc.real_vram_size &&
1172 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1175 /* Check if the root BUS has 64bit memory resources */
1176 root = adev->pdev->bus;
1177 while (root->parent)
1178 root = root->parent;
1180 pci_bus_for_each_resource(root, res, i) {
1181 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1182 res->start > 0x100000000ull)
1186 /* Trying to resize is pointless without a root hub window above 4GB */
1190 /* Limit the BAR size to what is available */
1191 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1194 /* Disable memory decoding while we change the BAR addresses and size */
1195 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1196 pci_write_config_word(adev->pdev, PCI_COMMAND,
1197 cmd & ~PCI_COMMAND_MEMORY);
1199 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1200 amdgpu_doorbell_fini(adev);
1201 if (adev->asic_type >= CHIP_BONAIRE)
1202 pci_release_resource(adev->pdev, 2);
1204 pci_release_resource(adev->pdev, 0);
1206 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1208 DRM_INFO("Not enough PCI address space for a large BAR.");
1209 else if (r && r != -ENOTSUPP)
1210 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1212 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1214 /* When the doorbell or fb BAR isn't available we have no chance of
1217 r = amdgpu_doorbell_init(adev);
1218 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1221 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1226 static bool amdgpu_device_read_bios(struct amdgpu_device *adev)
1228 if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU))
1235 * GPU helpers function.
1238 * amdgpu_device_need_post - check if the hw need post or not
1240 * @adev: amdgpu_device pointer
1242 * Check if the asic has been initialized (all asics) at driver startup
1243 * or post is needed if hw reset is performed.
1244 * Returns true if need or false if not.
1246 bool amdgpu_device_need_post(struct amdgpu_device *adev)
1250 if (amdgpu_sriov_vf(adev))
1253 if (!amdgpu_device_read_bios(adev))
1256 if (amdgpu_passthrough(adev)) {
1257 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1258 * some old smc fw still need driver do vPost otherwise gpu hang, while
1259 * those smc fw version above 22.15 doesn't have this flaw, so we force
1260 * vpost executed for smc version below 22.15
1262 if (adev->asic_type == CHIP_FIJI) {
1266 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1267 /* force vPost if error occured */
1271 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1272 if (fw_ver < 0x00160e00)
1277 /* Don't post if we need to reset whole hive on init */
1278 if (adev->gmc.xgmi.pending_reset)
1281 if (adev->has_hw_reset) {
1282 adev->has_hw_reset = false;
1286 /* bios scratch used on CIK+ */
1287 if (adev->asic_type >= CHIP_BONAIRE)
1288 return amdgpu_atombios_scratch_need_asic_init(adev);
1290 /* check MEM_SIZE for older asics */
1291 reg = amdgpu_asic_get_config_memsize(adev);
1293 if ((reg != 0) && (reg != 0xffffffff))
1300 * On APUs with >= 64GB white flickering has been observed w/ SG enabled.
1301 * Disable S/G on such systems until we have a proper fix.
1302 * https://gitlab.freedesktop.org/drm/amd/-/issues/2354
1303 * https://gitlab.freedesktop.org/drm/amd/-/issues/2735
1305 bool amdgpu_sg_display_supported(struct amdgpu_device *adev)
1307 switch (amdgpu_sg_display) {
1317 if ((totalram_pages() << (PAGE_SHIFT - 10)) +
1318 (adev->gmc.real_vram_size / 1024) >= 64000000) {
1319 DRM_WARN("Disabling S/G due to >=64GB RAM\n");
1326 * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic
1327 * speed switching. Until we have confirmation from Intel that a specific host
1328 * supports it, it's safer that we keep it disabled for all.
1330 * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
1331 * https://gitlab.freedesktop.org/drm/amd/-/issues/2663
1333 bool amdgpu_device_pcie_dynamic_switching_supported(void)
1335 #if IS_ENABLED(CONFIG_X86)
1336 struct cpuinfo_x86 *c = &cpu_data(0);
1338 if (c->x86_vendor == X86_VENDOR_INTEL)
1345 * amdgpu_device_should_use_aspm - check if the device should program ASPM
1347 * @adev: amdgpu_device pointer
1349 * Confirm whether the module parameter and pcie bridge agree that ASPM should
1350 * be set for this device.
1352 * Returns true if it should be used or false if not.
1354 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
1356 switch (amdgpu_aspm) {
1366 return pcie_aspm_enabled(adev->pdev);
1369 bool amdgpu_device_aspm_support_quirk(void)
1371 #if IS_ENABLED(CONFIG_X86)
1372 struct cpuinfo_x86 *c = &cpu_data(0);
1374 return !(c->x86 == 6 && c->x86_model == INTEL_FAM6_ALDERLAKE);
1380 /* if we get transitioned to only one device, take VGA back */
1382 * amdgpu_device_vga_set_decode - enable/disable vga decode
1384 * @pdev: PCI device pointer
1385 * @state: enable/disable vga decode
1387 * Enable/disable vga decode (all asics).
1388 * Returns VGA resource flags.
1390 static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev,
1393 struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev));
1395 amdgpu_asic_set_vga_state(adev, state);
1397 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1398 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1400 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1404 * amdgpu_device_check_block_size - validate the vm block size
1406 * @adev: amdgpu_device pointer
1408 * Validates the vm block size specified via module parameter.
1409 * The vm block size defines number of bits in page table versus page directory,
1410 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1411 * page table and the remaining bits are in the page directory.
1413 static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1415 /* defines number of bits in page table versus page directory,
1416 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1417 * page table and the remaining bits are in the page directory
1419 if (amdgpu_vm_block_size == -1)
1422 if (amdgpu_vm_block_size < 9) {
1423 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1424 amdgpu_vm_block_size);
1425 amdgpu_vm_block_size = -1;
1430 * amdgpu_device_check_vm_size - validate the vm size
1432 * @adev: amdgpu_device pointer
1434 * Validates the vm size in GB specified via module parameter.
1435 * The VM size is the size of the GPU virtual memory space in GB.
1437 static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1439 /* no need to check the default value */
1440 if (amdgpu_vm_size == -1)
1443 if (amdgpu_vm_size < 1) {
1444 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1446 amdgpu_vm_size = -1;
1450 static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1453 bool is_os_64 = (sizeof(void *) == 8);
1454 uint64_t total_memory;
1455 uint64_t dram_size_seven_GB = 0x1B8000000;
1456 uint64_t dram_size_three_GB = 0xB8000000;
1458 if (amdgpu_smu_memory_pool_size == 0)
1462 DRM_WARN("Not 64-bit OS, feature not supported\n");
1466 total_memory = (uint64_t)si.totalram * si.mem_unit;
1468 if ((amdgpu_smu_memory_pool_size == 1) ||
1469 (amdgpu_smu_memory_pool_size == 2)) {
1470 if (total_memory < dram_size_three_GB)
1472 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1473 (amdgpu_smu_memory_pool_size == 8)) {
1474 if (total_memory < dram_size_seven_GB)
1477 DRM_WARN("Smu memory pool size not supported\n");
1480 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1485 DRM_WARN("No enough system memory\n");
1487 adev->pm.smu_prv_buffer_size = 0;
1490 static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)
1492 if (!(adev->flags & AMD_IS_APU) ||
1493 adev->asic_type < CHIP_RAVEN)
1496 switch (adev->asic_type) {
1498 if (adev->pdev->device == 0x15dd)
1499 adev->apu_flags |= AMD_APU_IS_RAVEN;
1500 if (adev->pdev->device == 0x15d8)
1501 adev->apu_flags |= AMD_APU_IS_PICASSO;
1504 if ((adev->pdev->device == 0x1636) ||
1505 (adev->pdev->device == 0x164c))
1506 adev->apu_flags |= AMD_APU_IS_RENOIR;
1508 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1511 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1513 case CHIP_YELLOW_CARP:
1515 case CHIP_CYAN_SKILLFISH:
1516 if ((adev->pdev->device == 0x13FE) ||
1517 (adev->pdev->device == 0x143F))
1518 adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2;
1528 * amdgpu_device_check_arguments - validate module params
1530 * @adev: amdgpu_device pointer
1532 * Validates certain module parameters and updates
1533 * the associated values used by the driver (all asics).
1535 static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1537 if (amdgpu_sched_jobs < 4) {
1538 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1540 amdgpu_sched_jobs = 4;
1541 } else if (!is_power_of_2(amdgpu_sched_jobs)) {
1542 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1544 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1547 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1548 /* gart size must be greater or equal to 32M */
1549 dev_warn(adev->dev, "gart size (%d) too small\n",
1551 amdgpu_gart_size = -1;
1554 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1555 /* gtt size must be greater or equal to 32M */
1556 dev_warn(adev->dev, "gtt size (%d) too small\n",
1558 amdgpu_gtt_size = -1;
1561 /* valid range is between 4 and 9 inclusive */
1562 if (amdgpu_vm_fragment_size != -1 &&
1563 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1564 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1565 amdgpu_vm_fragment_size = -1;
1568 if (amdgpu_sched_hw_submission < 2) {
1569 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1570 amdgpu_sched_hw_submission);
1571 amdgpu_sched_hw_submission = 2;
1572 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1573 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1574 amdgpu_sched_hw_submission);
1575 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1578 if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) {
1579 dev_warn(adev->dev, "invalid option for reset method, reverting to default\n");
1580 amdgpu_reset_method = -1;
1583 amdgpu_device_check_smu_prv_buffer_size(adev);
1585 amdgpu_device_check_vm_size(adev);
1587 amdgpu_device_check_block_size(adev);
1589 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1595 * amdgpu_switcheroo_set_state - set switcheroo state
1597 * @pdev: pci dev pointer
1598 * @state: vga_switcheroo state
1600 * Callback for the switcheroo driver. Suspends or resumes
1601 * the asics before or after it is powered up using ACPI methods.
1603 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1604 enum vga_switcheroo_state state)
1606 struct drm_device *dev = pci_get_drvdata(pdev);
1609 if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF)
1612 if (state == VGA_SWITCHEROO_ON) {
1613 pr_info("switched on\n");
1614 /* don't suspend or resume card normally */
1615 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1617 pci_set_power_state(pdev, PCI_D0);
1618 amdgpu_device_load_pci_state(pdev);
1619 r = pci_enable_device(pdev);
1621 DRM_WARN("pci_enable_device failed (%d)\n", r);
1622 amdgpu_device_resume(dev, true);
1624 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1626 pr_info("switched off\n");
1627 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1628 amdgpu_device_suspend(dev, true);
1629 amdgpu_device_cache_pci_state(pdev);
1630 /* Shut down the device */
1631 pci_disable_device(pdev);
1632 pci_set_power_state(pdev, PCI_D3cold);
1633 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1638 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1640 * @pdev: pci dev pointer
1642 * Callback for the switcheroo driver. Check of the switcheroo
1643 * state can be changed.
1644 * Returns true if the state can be changed, false if not.
1646 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1648 struct drm_device *dev = pci_get_drvdata(pdev);
1651 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1652 * locking inversion with the driver load path. And the access here is
1653 * completely racy anyway. So don't bother with locking for now.
1655 return atomic_read(&dev->open_count) == 0;
1658 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1659 .set_gpu_state = amdgpu_switcheroo_set_state,
1661 .can_switch = amdgpu_switcheroo_can_switch,
1665 * amdgpu_device_ip_set_clockgating_state - set the CG state
1667 * @dev: amdgpu_device pointer
1668 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1669 * @state: clockgating state (gate or ungate)
1671 * Sets the requested clockgating state for all instances of
1672 * the hardware IP specified.
1673 * Returns the error code from the last instance.
1675 int amdgpu_device_ip_set_clockgating_state(void *dev,
1676 enum amd_ip_block_type block_type,
1677 enum amd_clockgating_state state)
1679 struct amdgpu_device *adev = dev;
1682 for (i = 0; i < adev->num_ip_blocks; i++) {
1683 if (!adev->ip_blocks[i].status.valid)
1685 if (adev->ip_blocks[i].version->type != block_type)
1687 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1689 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1690 (void *)adev, state);
1692 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1693 adev->ip_blocks[i].version->funcs->name, r);
1699 * amdgpu_device_ip_set_powergating_state - set the PG state
1701 * @dev: amdgpu_device pointer
1702 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1703 * @state: powergating state (gate or ungate)
1705 * Sets the requested powergating state for all instances of
1706 * the hardware IP specified.
1707 * Returns the error code from the last instance.
1709 int amdgpu_device_ip_set_powergating_state(void *dev,
1710 enum amd_ip_block_type block_type,
1711 enum amd_powergating_state state)
1713 struct amdgpu_device *adev = dev;
1716 for (i = 0; i < adev->num_ip_blocks; i++) {
1717 if (!adev->ip_blocks[i].status.valid)
1719 if (adev->ip_blocks[i].version->type != block_type)
1721 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1723 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1724 (void *)adev, state);
1726 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1727 adev->ip_blocks[i].version->funcs->name, r);
1733 * amdgpu_device_ip_get_clockgating_state - get the CG state
1735 * @adev: amdgpu_device pointer
1736 * @flags: clockgating feature flags
1738 * Walks the list of IPs on the device and updates the clockgating
1739 * flags for each IP.
1740 * Updates @flags with the feature flags for each hardware IP where
1741 * clockgating is enabled.
1743 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1748 for (i = 0; i < adev->num_ip_blocks; i++) {
1749 if (!adev->ip_blocks[i].status.valid)
1751 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1752 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1757 * amdgpu_device_ip_wait_for_idle - wait for idle
1759 * @adev: amdgpu_device pointer
1760 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1762 * Waits for the request hardware IP to be idle.
1763 * Returns 0 for success or a negative error code on failure.
1765 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1766 enum amd_ip_block_type block_type)
1770 for (i = 0; i < adev->num_ip_blocks; i++) {
1771 if (!adev->ip_blocks[i].status.valid)
1773 if (adev->ip_blocks[i].version->type == block_type) {
1774 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1785 * amdgpu_device_ip_is_idle - is the hardware IP idle
1787 * @adev: amdgpu_device pointer
1788 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1790 * Check if the hardware IP is idle or not.
1791 * Returns true if it the IP is idle, false if not.
1793 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1794 enum amd_ip_block_type block_type)
1798 for (i = 0; i < adev->num_ip_blocks; i++) {
1799 if (!adev->ip_blocks[i].status.valid)
1801 if (adev->ip_blocks[i].version->type == block_type)
1802 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1809 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1811 * @adev: amdgpu_device pointer
1812 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1814 * Returns a pointer to the hardware IP block structure
1815 * if it exists for the asic, otherwise NULL.
1817 struct amdgpu_ip_block *
1818 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1819 enum amd_ip_block_type type)
1823 for (i = 0; i < adev->num_ip_blocks; i++)
1824 if (adev->ip_blocks[i].version->type == type)
1825 return &adev->ip_blocks[i];
1831 * amdgpu_device_ip_block_version_cmp
1833 * @adev: amdgpu_device pointer
1834 * @type: enum amd_ip_block_type
1835 * @major: major version
1836 * @minor: minor version
1838 * return 0 if equal or greater
1839 * return 1 if smaller or the ip_block doesn't exist
1841 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1842 enum amd_ip_block_type type,
1843 u32 major, u32 minor)
1845 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1847 if (ip_block && ((ip_block->version->major > major) ||
1848 ((ip_block->version->major == major) &&
1849 (ip_block->version->minor >= minor))))
1856 * amdgpu_device_ip_block_add
1858 * @adev: amdgpu_device pointer
1859 * @ip_block_version: pointer to the IP to add
1861 * Adds the IP block driver information to the collection of IPs
1864 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1865 const struct amdgpu_ip_block_version *ip_block_version)
1867 if (!ip_block_version)
1870 switch (ip_block_version->type) {
1871 case AMD_IP_BLOCK_TYPE_VCN:
1872 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1875 case AMD_IP_BLOCK_TYPE_JPEG:
1876 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
1883 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1884 ip_block_version->funcs->name);
1886 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1892 * amdgpu_device_enable_virtual_display - enable virtual display feature
1894 * @adev: amdgpu_device pointer
1896 * Enabled the virtual display feature if the user has enabled it via
1897 * the module parameter virtual_display. This feature provides a virtual
1898 * display hardware on headless boards or in virtualized environments.
1899 * This function parses and validates the configuration string specified by
1900 * the user and configues the virtual display configuration (number of
1901 * virtual connectors, crtcs, etc.) specified.
1903 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1905 adev->enable_virtual_display = false;
1907 if (amdgpu_virtual_display) {
1908 const char *pci_address_name = pci_name(adev->pdev);
1909 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1911 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1912 pciaddstr_tmp = pciaddstr;
1913 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1914 pciaddname = strsep(&pciaddname_tmp, ",");
1915 if (!strcmp("all", pciaddname)
1916 || !strcmp(pci_address_name, pciaddname)) {
1920 adev->enable_virtual_display = true;
1923 res = kstrtol(pciaddname_tmp, 10,
1931 adev->mode_info.num_crtc = num_crtc;
1933 adev->mode_info.num_crtc = 1;
1939 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1940 amdgpu_virtual_display, pci_address_name,
1941 adev->enable_virtual_display, adev->mode_info.num_crtc);
1947 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)
1949 if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {
1950 adev->mode_info.num_crtc = 1;
1951 adev->enable_virtual_display = true;
1952 DRM_INFO("virtual_display:%d, num_crtc:%d\n",
1953 adev->enable_virtual_display, adev->mode_info.num_crtc);
1958 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1960 * @adev: amdgpu_device pointer
1962 * Parses the asic configuration parameters specified in the gpu info
1963 * firmware and makes them availale to the driver for use in configuring
1965 * Returns 0 on success, -EINVAL on failure.
1967 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1969 const char *chip_name;
1972 const struct gpu_info_firmware_header_v1_0 *hdr;
1974 adev->firmware.gpu_info_fw = NULL;
1976 if (adev->mman.discovery_bin) {
1978 * FIXME: The bounding box is still needed by Navi12, so
1979 * temporarily read it from gpu_info firmware. Should be dropped
1980 * when DAL no longer needs it.
1982 if (adev->asic_type != CHIP_NAVI12)
1986 switch (adev->asic_type) {
1990 chip_name = "vega10";
1993 chip_name = "vega12";
1996 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1997 chip_name = "raven2";
1998 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1999 chip_name = "picasso";
2001 chip_name = "raven";
2004 chip_name = "arcturus";
2007 chip_name = "navi12";
2011 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
2012 err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw, fw_name);
2015 "Failed to get gpu_info firmware \"%s\"\n",
2020 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
2021 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
2023 switch (hdr->version_major) {
2026 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
2027 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
2028 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2031 * Should be droped when DAL no longer needs it.
2033 if (adev->asic_type == CHIP_NAVI12)
2034 goto parse_soc_bounding_box;
2036 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
2037 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
2038 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
2039 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
2040 adev->gfx.config.max_texture_channel_caches =
2041 le32_to_cpu(gpu_info_fw->gc_num_tccs);
2042 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
2043 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
2044 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
2045 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
2046 adev->gfx.config.double_offchip_lds_buf =
2047 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
2048 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
2049 adev->gfx.cu_info.max_waves_per_simd =
2050 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
2051 adev->gfx.cu_info.max_scratch_slots_per_cu =
2052 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
2053 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
2054 if (hdr->version_minor >= 1) {
2055 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
2056 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
2057 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2058 adev->gfx.config.num_sc_per_sh =
2059 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
2060 adev->gfx.config.num_packer_per_sc =
2061 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
2064 parse_soc_bounding_box:
2066 * soc bounding box info is not integrated in disocovery table,
2067 * we always need to parse it from gpu info firmware if needed.
2069 if (hdr->version_minor == 2) {
2070 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
2071 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
2072 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2073 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
2079 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
2088 * amdgpu_device_ip_early_init - run early init for hardware IPs
2090 * @adev: amdgpu_device pointer
2092 * Early initialization pass for hardware IPs. The hardware IPs that make
2093 * up each asic are discovered each IP's early_init callback is run. This
2094 * is the first stage in initializing the asic.
2095 * Returns 0 on success, negative error code on failure.
2097 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
2099 struct drm_device *dev = adev_to_drm(adev);
2100 struct pci_dev *parent;
2104 amdgpu_device_enable_virtual_display(adev);
2106 if (amdgpu_sriov_vf(adev)) {
2107 r = amdgpu_virt_request_full_gpu(adev, true);
2112 switch (adev->asic_type) {
2113 #ifdef CONFIG_DRM_AMDGPU_SI
2119 adev->family = AMDGPU_FAMILY_SI;
2120 r = si_set_ip_blocks(adev);
2125 #ifdef CONFIG_DRM_AMDGPU_CIK
2131 if (adev->flags & AMD_IS_APU)
2132 adev->family = AMDGPU_FAMILY_KV;
2134 adev->family = AMDGPU_FAMILY_CI;
2136 r = cik_set_ip_blocks(adev);
2144 case CHIP_POLARIS10:
2145 case CHIP_POLARIS11:
2146 case CHIP_POLARIS12:
2150 if (adev->flags & AMD_IS_APU)
2151 adev->family = AMDGPU_FAMILY_CZ;
2153 adev->family = AMDGPU_FAMILY_VI;
2155 r = vi_set_ip_blocks(adev);
2160 r = amdgpu_discovery_set_ip_blocks(adev);
2166 if (amdgpu_has_atpx() &&
2167 (amdgpu_is_atpx_hybrid() ||
2168 amdgpu_has_atpx_dgpu_power_cntl()) &&
2169 ((adev->flags & AMD_IS_APU) == 0) &&
2170 !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
2171 adev->flags |= AMD_IS_PX;
2173 if (!(adev->flags & AMD_IS_APU)) {
2174 parent = pci_upstream_bridge(adev->pdev);
2175 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2179 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2180 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2181 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2182 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2183 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2186 for (i = 0; i < adev->num_ip_blocks; i++) {
2187 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2188 DRM_WARN("disabled ip block: %d <%s>\n",
2189 i, adev->ip_blocks[i].version->funcs->name);
2190 adev->ip_blocks[i].status.valid = false;
2192 if (adev->ip_blocks[i].version->funcs->early_init) {
2193 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2195 adev->ip_blocks[i].status.valid = false;
2197 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2198 adev->ip_blocks[i].version->funcs->name, r);
2201 adev->ip_blocks[i].status.valid = true;
2204 adev->ip_blocks[i].status.valid = true;
2207 /* get the vbios after the asic_funcs are set up */
2208 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2209 r = amdgpu_device_parse_gpu_info_fw(adev);
2214 if (amdgpu_device_read_bios(adev)) {
2215 if (!amdgpu_get_bios(adev))
2218 r = amdgpu_atombios_init(adev);
2220 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2221 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2226 /*get pf2vf msg info at it's earliest time*/
2227 if (amdgpu_sriov_vf(adev))
2228 amdgpu_virt_init_data_exchange(adev);
2235 amdgpu_amdkfd_device_probe(adev);
2236 adev->cg_flags &= amdgpu_cg_mask;
2237 adev->pg_flags &= amdgpu_pg_mask;
2242 static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2246 for (i = 0; i < adev->num_ip_blocks; i++) {
2247 if (!adev->ip_blocks[i].status.sw)
2249 if (adev->ip_blocks[i].status.hw)
2251 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2252 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2253 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2254 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2256 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2257 adev->ip_blocks[i].version->funcs->name, r);
2260 adev->ip_blocks[i].status.hw = true;
2267 static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2271 for (i = 0; i < adev->num_ip_blocks; i++) {
2272 if (!adev->ip_blocks[i].status.sw)
2274 if (adev->ip_blocks[i].status.hw)
2276 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2278 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2279 adev->ip_blocks[i].version->funcs->name, r);
2282 adev->ip_blocks[i].status.hw = true;
2288 static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2292 uint32_t smu_version;
2294 if (adev->asic_type >= CHIP_VEGA10) {
2295 for (i = 0; i < adev->num_ip_blocks; i++) {
2296 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2299 if (!adev->ip_blocks[i].status.sw)
2302 /* no need to do the fw loading again if already done*/
2303 if (adev->ip_blocks[i].status.hw == true)
2306 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2307 r = adev->ip_blocks[i].version->funcs->resume(adev);
2309 DRM_ERROR("resume of IP block <%s> failed %d\n",
2310 adev->ip_blocks[i].version->funcs->name, r);
2314 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2316 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2317 adev->ip_blocks[i].version->funcs->name, r);
2322 adev->ip_blocks[i].status.hw = true;
2327 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2328 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2333 static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
2338 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2339 struct amdgpu_ring *ring = adev->rings[i];
2341 /* No need to setup the GPU scheduler for rings that don't need it */
2342 if (!ring || ring->no_scheduler)
2345 switch (ring->funcs->type) {
2346 case AMDGPU_RING_TYPE_GFX:
2347 timeout = adev->gfx_timeout;
2349 case AMDGPU_RING_TYPE_COMPUTE:
2350 timeout = adev->compute_timeout;
2352 case AMDGPU_RING_TYPE_SDMA:
2353 timeout = adev->sdma_timeout;
2356 timeout = adev->video_timeout;
2360 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
2361 ring->num_hw_submission, 0,
2362 timeout, adev->reset_domain->wq,
2363 ring->sched_score, ring->name,
2366 DRM_ERROR("Failed to create scheduler on ring %s.\n",
2372 amdgpu_xcp_update_partition_sched_list(adev);
2379 * amdgpu_device_ip_init - run init for hardware IPs
2381 * @adev: amdgpu_device pointer
2383 * Main initialization pass for hardware IPs. The list of all the hardware
2384 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2385 * are run. sw_init initializes the software state associated with each IP
2386 * and hw_init initializes the hardware associated with each IP.
2387 * Returns 0 on success, negative error code on failure.
2389 static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2393 r = amdgpu_ras_init(adev);
2397 for (i = 0; i < adev->num_ip_blocks; i++) {
2398 if (!adev->ip_blocks[i].status.valid)
2400 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2402 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2403 adev->ip_blocks[i].version->funcs->name, r);
2406 adev->ip_blocks[i].status.sw = true;
2408 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2409 /* need to do common hw init early so everything is set up for gmc */
2410 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2412 DRM_ERROR("hw_init %d failed %d\n", i, r);
2415 adev->ip_blocks[i].status.hw = true;
2416 } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2417 /* need to do gmc hw init early so we can allocate gpu mem */
2418 /* Try to reserve bad pages early */
2419 if (amdgpu_sriov_vf(adev))
2420 amdgpu_virt_exchange_data(adev);
2422 r = amdgpu_device_mem_scratch_init(adev);
2424 DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);
2427 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2429 DRM_ERROR("hw_init %d failed %d\n", i, r);
2432 r = amdgpu_device_wb_init(adev);
2434 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2437 adev->ip_blocks[i].status.hw = true;
2439 /* right after GMC hw init, we create CSA */
2440 if (adev->gfx.mcbp) {
2441 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2442 AMDGPU_GEM_DOMAIN_VRAM |
2443 AMDGPU_GEM_DOMAIN_GTT,
2446 DRM_ERROR("allocate CSA failed %d\n", r);
2453 if (amdgpu_sriov_vf(adev))
2454 amdgpu_virt_init_data_exchange(adev);
2456 r = amdgpu_ib_pool_init(adev);
2458 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2459 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2463 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2467 r = amdgpu_device_ip_hw_init_phase1(adev);
2471 r = amdgpu_device_fw_loading(adev);
2475 r = amdgpu_device_ip_hw_init_phase2(adev);
2480 * retired pages will be loaded from eeprom and reserved here,
2481 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2482 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2483 * for I2C communication which only true at this point.
2485 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2486 * failure from bad gpu situation and stop amdgpu init process
2487 * accordingly. For other failed cases, it will still release all
2488 * the resource and print error message, rather than returning one
2489 * negative value to upper level.
2491 * Note: theoretically, this should be called before all vram allocations
2492 * to protect retired page from abusing
2494 r = amdgpu_ras_recovery_init(adev);
2499 * In case of XGMI grab extra reference for reset domain for this device
2501 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2502 if (amdgpu_xgmi_add_device(adev) == 0) {
2503 if (!amdgpu_sriov_vf(adev)) {
2504 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2506 if (WARN_ON(!hive)) {
2511 if (!hive->reset_domain ||
2512 !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
2514 amdgpu_put_xgmi_hive(hive);
2518 /* Drop the early temporary reset domain we created for device */
2519 amdgpu_reset_put_reset_domain(adev->reset_domain);
2520 adev->reset_domain = hive->reset_domain;
2521 amdgpu_put_xgmi_hive(hive);
2526 r = amdgpu_device_init_schedulers(adev);
2530 /* Don't init kfd if whole hive need to be reset during init */
2531 if (!adev->gmc.xgmi.pending_reset) {
2532 kgd2kfd_init_zone_device(adev);
2533 amdgpu_amdkfd_device_init(adev);
2536 amdgpu_fru_get_product_info(adev);
2544 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2546 * @adev: amdgpu_device pointer
2548 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2549 * this function before a GPU reset. If the value is retained after a
2550 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2552 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2554 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2558 * amdgpu_device_check_vram_lost - check if vram is valid
2560 * @adev: amdgpu_device pointer
2562 * Checks the reset magic value written to the gart pointer in VRAM.
2563 * The driver calls this after a GPU reset to see if the contents of
2564 * VRAM is lost or now.
2565 * returns true if vram is lost, false if not.
2567 static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2569 if (memcmp(adev->gart.ptr, adev->reset_magic,
2570 AMDGPU_RESET_MAGIC_NUM))
2573 if (!amdgpu_in_reset(adev))
2577 * For all ASICs with baco/mode1 reset, the VRAM is
2578 * always assumed to be lost.
2580 switch (amdgpu_asic_reset_method(adev)) {
2581 case AMD_RESET_METHOD_BACO:
2582 case AMD_RESET_METHOD_MODE1:
2590 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2592 * @adev: amdgpu_device pointer
2593 * @state: clockgating state (gate or ungate)
2595 * The list of all the hardware IPs that make up the asic is walked and the
2596 * set_clockgating_state callbacks are run.
2597 * Late initialization pass enabling clockgating for hardware IPs.
2598 * Fini or suspend, pass disabling clockgating for hardware IPs.
2599 * Returns 0 on success, negative error code on failure.
2602 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2603 enum amd_clockgating_state state)
2607 if (amdgpu_emu_mode == 1)
2610 for (j = 0; j < adev->num_ip_blocks; j++) {
2611 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2612 if (!adev->ip_blocks[i].status.late_initialized)
2614 /* skip CG for GFX, SDMA on S0ix */
2615 if (adev->in_s0ix &&
2616 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2617 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2619 /* skip CG for VCE/UVD, it's handled specially */
2620 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2621 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2622 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2623 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2624 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2625 /* enable clockgating to save power */
2626 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2629 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2630 adev->ip_blocks[i].version->funcs->name, r);
2639 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
2640 enum amd_powergating_state state)
2644 if (amdgpu_emu_mode == 1)
2647 for (j = 0; j < adev->num_ip_blocks; j++) {
2648 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2649 if (!adev->ip_blocks[i].status.late_initialized)
2651 /* skip PG for GFX, SDMA on S0ix */
2652 if (adev->in_s0ix &&
2653 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2654 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2656 /* skip CG for VCE/UVD, it's handled specially */
2657 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2658 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2659 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2660 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2661 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2662 /* enable powergating to save power */
2663 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2666 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2667 adev->ip_blocks[i].version->funcs->name, r);
2675 static int amdgpu_device_enable_mgpu_fan_boost(void)
2677 struct amdgpu_gpu_instance *gpu_ins;
2678 struct amdgpu_device *adev;
2681 mutex_lock(&mgpu_info.mutex);
2684 * MGPU fan boost feature should be enabled
2685 * only when there are two or more dGPUs in
2688 if (mgpu_info.num_dgpu < 2)
2691 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2692 gpu_ins = &(mgpu_info.gpu_ins[i]);
2693 adev = gpu_ins->adev;
2694 if (!(adev->flags & AMD_IS_APU) &&
2695 !gpu_ins->mgpu_fan_enabled) {
2696 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2700 gpu_ins->mgpu_fan_enabled = 1;
2705 mutex_unlock(&mgpu_info.mutex);
2711 * amdgpu_device_ip_late_init - run late init for hardware IPs
2713 * @adev: amdgpu_device pointer
2715 * Late initialization pass for hardware IPs. The list of all the hardware
2716 * IPs that make up the asic is walked and the late_init callbacks are run.
2717 * late_init covers any special initialization that an IP requires
2718 * after all of the have been initialized or something that needs to happen
2719 * late in the init process.
2720 * Returns 0 on success, negative error code on failure.
2722 static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2724 struct amdgpu_gpu_instance *gpu_instance;
2727 for (i = 0; i < adev->num_ip_blocks; i++) {
2728 if (!adev->ip_blocks[i].status.hw)
2730 if (adev->ip_blocks[i].version->funcs->late_init) {
2731 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2733 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2734 adev->ip_blocks[i].version->funcs->name, r);
2738 adev->ip_blocks[i].status.late_initialized = true;
2741 r = amdgpu_ras_late_init(adev);
2743 DRM_ERROR("amdgpu_ras_late_init failed %d", r);
2747 amdgpu_ras_set_error_query_ready(adev, true);
2749 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2750 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2752 amdgpu_device_fill_reset_magic(adev);
2754 r = amdgpu_device_enable_mgpu_fan_boost();
2756 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2758 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
2759 if (amdgpu_passthrough(adev) &&
2760 ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1) ||
2761 adev->asic_type == CHIP_ALDEBARAN))
2762 amdgpu_dpm_handle_passthrough_sbr(adev, true);
2764 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2765 mutex_lock(&mgpu_info.mutex);
2768 * Reset device p-state to low as this was booted with high.
2770 * This should be performed only after all devices from the same
2771 * hive get initialized.
2773 * However, it's unknown how many device in the hive in advance.
2774 * As this is counted one by one during devices initializations.
2776 * So, we wait for all XGMI interlinked devices initialized.
2777 * This may bring some delays as those devices may come from
2778 * different hives. But that should be OK.
2780 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2781 for (i = 0; i < mgpu_info.num_gpu; i++) {
2782 gpu_instance = &(mgpu_info.gpu_ins[i]);
2783 if (gpu_instance->adev->flags & AMD_IS_APU)
2786 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
2787 AMDGPU_XGMI_PSTATE_MIN);
2789 DRM_ERROR("pstate setting failed (%d).\n", r);
2795 mutex_unlock(&mgpu_info.mutex);
2802 * amdgpu_device_smu_fini_early - smu hw_fini wrapper
2804 * @adev: amdgpu_device pointer
2806 * For ASICs need to disable SMC first
2808 static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)
2812 if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
2815 for (i = 0; i < adev->num_ip_blocks; i++) {
2816 if (!adev->ip_blocks[i].status.hw)
2818 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2819 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2820 /* XXX handle errors */
2822 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2823 adev->ip_blocks[i].version->funcs->name, r);
2825 adev->ip_blocks[i].status.hw = false;
2831 static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
2835 for (i = 0; i < adev->num_ip_blocks; i++) {
2836 if (!adev->ip_blocks[i].version->funcs->early_fini)
2839 r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev);
2841 DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
2842 adev->ip_blocks[i].version->funcs->name, r);
2846 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2847 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2849 amdgpu_amdkfd_suspend(adev, false);
2851 /* Workaroud for ASICs need to disable SMC first */
2852 amdgpu_device_smu_fini_early(adev);
2854 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2855 if (!adev->ip_blocks[i].status.hw)
2858 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2859 /* XXX handle errors */
2861 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2862 adev->ip_blocks[i].version->funcs->name, r);
2865 adev->ip_blocks[i].status.hw = false;
2868 if (amdgpu_sriov_vf(adev)) {
2869 if (amdgpu_virt_release_full_gpu(adev, false))
2870 DRM_ERROR("failed to release exclusive mode on fini\n");
2877 * amdgpu_device_ip_fini - run fini for hardware IPs
2879 * @adev: amdgpu_device pointer
2881 * Main teardown pass for hardware IPs. The list of all the hardware
2882 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2883 * are run. hw_fini tears down the hardware associated with each IP
2884 * and sw_fini tears down any software state associated with each IP.
2885 * Returns 0 on success, negative error code on failure.
2887 static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2891 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
2892 amdgpu_virt_release_ras_err_handler_data(adev);
2894 if (adev->gmc.xgmi.num_physical_nodes > 1)
2895 amdgpu_xgmi_remove_device(adev);
2897 amdgpu_amdkfd_device_fini_sw(adev);
2899 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2900 if (!adev->ip_blocks[i].status.sw)
2903 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2904 amdgpu_ucode_free_bo(adev);
2905 amdgpu_free_static_csa(&adev->virt.csa_obj);
2906 amdgpu_device_wb_fini(adev);
2907 amdgpu_device_mem_scratch_fini(adev);
2908 amdgpu_ib_pool_fini(adev);
2911 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2912 /* XXX handle errors */
2914 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2915 adev->ip_blocks[i].version->funcs->name, r);
2917 adev->ip_blocks[i].status.sw = false;
2918 adev->ip_blocks[i].status.valid = false;
2921 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2922 if (!adev->ip_blocks[i].status.late_initialized)
2924 if (adev->ip_blocks[i].version->funcs->late_fini)
2925 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2926 adev->ip_blocks[i].status.late_initialized = false;
2929 amdgpu_ras_fini(adev);
2935 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2937 * @work: work_struct.
2939 static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2941 struct amdgpu_device *adev =
2942 container_of(work, struct amdgpu_device, delayed_init_work.work);
2945 r = amdgpu_ib_ring_tests(adev);
2947 DRM_ERROR("ib ring test failed (%d).\n", r);
2950 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2952 struct amdgpu_device *adev =
2953 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2955 WARN_ON_ONCE(adev->gfx.gfx_off_state);
2956 WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
2958 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2959 adev->gfx.gfx_off_state = true;
2963 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2965 * @adev: amdgpu_device pointer
2967 * Main suspend function for hardware IPs. The list of all the hardware
2968 * IPs that make up the asic is walked, clockgating is disabled and the
2969 * suspend callbacks are run. suspend puts the hardware and software state
2970 * in each IP into a state suitable for suspend.
2971 * Returns 0 on success, negative error code on failure.
2973 static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2977 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2978 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2981 * Per PMFW team's suggestion, driver needs to handle gfxoff
2982 * and df cstate features disablement for gpu reset(e.g. Mode1Reset)
2983 * scenario. Add the missing df cstate disablement here.
2985 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
2986 dev_warn(adev->dev, "Failed to disallow df cstate");
2988 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2989 if (!adev->ip_blocks[i].status.valid)
2992 /* displays are handled separately */
2993 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
2996 /* XXX handle errors */
2997 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2998 /* XXX handle errors */
3000 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3001 adev->ip_blocks[i].version->funcs->name, r);
3005 adev->ip_blocks[i].status.hw = false;
3012 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
3014 * @adev: amdgpu_device pointer
3016 * Main suspend function for hardware IPs. The list of all the hardware
3017 * IPs that make up the asic is walked, clockgating is disabled and the
3018 * suspend callbacks are run. suspend puts the hardware and software state
3019 * in each IP into a state suitable for suspend.
3020 * Returns 0 on success, negative error code on failure.
3022 static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
3027 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);
3029 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3030 if (!adev->ip_blocks[i].status.valid)
3032 /* displays are handled in phase1 */
3033 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
3035 /* PSP lost connection when err_event_athub occurs */
3036 if (amdgpu_ras_intr_triggered() &&
3037 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3038 adev->ip_blocks[i].status.hw = false;
3042 /* skip unnecessary suspend if we do not initialize them yet */
3043 if (adev->gmc.xgmi.pending_reset &&
3044 !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3045 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC ||
3046 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3047 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) {
3048 adev->ip_blocks[i].status.hw = false;
3052 /* skip suspend of gfx/mes and psp for S0ix
3053 * gfx is in gfxoff state, so on resume it will exit gfxoff just
3054 * like at runtime. PSP is also part of the always on hardware
3055 * so no need to suspend it.
3057 if (adev->in_s0ix &&
3058 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
3059 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3060 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
3063 /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
3064 if (adev->in_s0ix &&
3065 (adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 0, 0)) &&
3066 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
3069 /* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot.
3070 * These are in TMR, hence are expected to be reused by PSP-TOS to reload
3071 * from this location and RLC Autoload automatically also gets loaded
3072 * from here based on PMFW -> PSP message during re-init sequence.
3073 * Therefore, the psp suspend & resume should be skipped to avoid destroy
3074 * the TMR and reload FWs again for IMU enabled APU ASICs.
3076 if (amdgpu_in_reset(adev) &&
3077 (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs &&
3078 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3081 /* XXX handle errors */
3082 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3083 /* XXX handle errors */
3085 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3086 adev->ip_blocks[i].version->funcs->name, r);
3088 adev->ip_blocks[i].status.hw = false;
3089 /* handle putting the SMC in the appropriate state */
3090 if (!amdgpu_sriov_vf(adev)) {
3091 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3092 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
3094 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
3095 adev->mp1_state, r);
3106 * amdgpu_device_ip_suspend - run suspend for hardware IPs
3108 * @adev: amdgpu_device pointer
3110 * Main suspend function for hardware IPs. The list of all the hardware
3111 * IPs that make up the asic is walked, clockgating is disabled and the
3112 * suspend callbacks are run. suspend puts the hardware and software state
3113 * in each IP into a state suitable for suspend.
3114 * Returns 0 on success, negative error code on failure.
3116 int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
3120 if (amdgpu_sriov_vf(adev)) {
3121 amdgpu_virt_fini_data_exchange(adev);
3122 amdgpu_virt_request_full_gpu(adev, false);
3125 r = amdgpu_device_ip_suspend_phase1(adev);
3128 r = amdgpu_device_ip_suspend_phase2(adev);
3130 if (amdgpu_sriov_vf(adev))
3131 amdgpu_virt_release_full_gpu(adev, false);
3136 static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
3140 static enum amd_ip_block_type ip_order[] = {
3141 AMD_IP_BLOCK_TYPE_COMMON,
3142 AMD_IP_BLOCK_TYPE_GMC,
3143 AMD_IP_BLOCK_TYPE_PSP,
3144 AMD_IP_BLOCK_TYPE_IH,
3147 for (i = 0; i < adev->num_ip_blocks; i++) {
3149 struct amdgpu_ip_block *block;
3151 block = &adev->ip_blocks[i];
3152 block->status.hw = false;
3154 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
3156 if (block->version->type != ip_order[j] ||
3157 !block->status.valid)
3160 r = block->version->funcs->hw_init(adev);
3161 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3164 block->status.hw = true;
3171 static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
3175 static enum amd_ip_block_type ip_order[] = {
3176 AMD_IP_BLOCK_TYPE_SMC,
3177 AMD_IP_BLOCK_TYPE_DCE,
3178 AMD_IP_BLOCK_TYPE_GFX,
3179 AMD_IP_BLOCK_TYPE_SDMA,
3180 AMD_IP_BLOCK_TYPE_MES,
3181 AMD_IP_BLOCK_TYPE_UVD,
3182 AMD_IP_BLOCK_TYPE_VCE,
3183 AMD_IP_BLOCK_TYPE_VCN,
3184 AMD_IP_BLOCK_TYPE_JPEG
3187 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
3189 struct amdgpu_ip_block *block;
3191 for (j = 0; j < adev->num_ip_blocks; j++) {
3192 block = &adev->ip_blocks[j];
3194 if (block->version->type != ip_order[i] ||
3195 !block->status.valid ||
3199 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
3200 r = block->version->funcs->resume(adev);
3202 r = block->version->funcs->hw_init(adev);
3204 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3207 block->status.hw = true;
3215 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
3217 * @adev: amdgpu_device pointer
3219 * First resume function for hardware IPs. The list of all the hardware
3220 * IPs that make up the asic is walked and the resume callbacks are run for
3221 * COMMON, GMC, and IH. resume puts the hardware into a functional state
3222 * after a suspend and updates the software state as necessary. This
3223 * function is also used for restoring the GPU after a GPU reset.
3224 * Returns 0 on success, negative error code on failure.
3226 static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
3230 for (i = 0; i < adev->num_ip_blocks; i++) {
3231 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3233 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3234 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3235 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3236 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {
3238 r = adev->ip_blocks[i].version->funcs->resume(adev);
3240 DRM_ERROR("resume of IP block <%s> failed %d\n",
3241 adev->ip_blocks[i].version->funcs->name, r);
3244 adev->ip_blocks[i].status.hw = true;
3252 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
3254 * @adev: amdgpu_device pointer
3256 * First resume function for hardware IPs. The list of all the hardware
3257 * IPs that make up the asic is walked and the resume callbacks are run for
3258 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
3259 * functional state after a suspend and updates the software state as
3260 * necessary. This function is also used for restoring the GPU after a GPU
3262 * Returns 0 on success, negative error code on failure.
3264 static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
3268 for (i = 0; i < adev->num_ip_blocks; i++) {
3269 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3271 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3272 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3273 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3274 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3276 r = adev->ip_blocks[i].version->funcs->resume(adev);
3278 DRM_ERROR("resume of IP block <%s> failed %d\n",
3279 adev->ip_blocks[i].version->funcs->name, r);
3282 adev->ip_blocks[i].status.hw = true;
3289 * amdgpu_device_ip_resume - run resume for hardware IPs
3291 * @adev: amdgpu_device pointer
3293 * Main resume function for hardware IPs. The hardware IPs
3294 * are split into two resume functions because they are
3295 * also used in recovering from a GPU reset and some additional
3296 * steps need to be take between them. In this case (S3/S4) they are
3298 * Returns 0 on success, negative error code on failure.
3300 static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
3304 if (!adev->in_s0ix) {
3305 r = amdgpu_amdkfd_resume_iommu(adev);
3310 r = amdgpu_device_ip_resume_phase1(adev);
3314 r = amdgpu_device_fw_loading(adev);
3318 r = amdgpu_device_ip_resume_phase2(adev);
3324 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
3326 * @adev: amdgpu_device pointer
3328 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3330 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3332 if (amdgpu_sriov_vf(adev)) {
3333 if (adev->is_atom_fw) {
3334 if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
3335 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3337 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3338 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3341 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3342 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3347 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3349 * @asic_type: AMD asic type
3351 * Check if there is DC (new modesetting infrastructre) support for an asic.
3352 * returns true if DC has support, false if not.
3354 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3356 switch (asic_type) {
3357 #ifdef CONFIG_DRM_AMDGPU_SI
3361 /* chips with no display hardware */
3363 #if defined(CONFIG_DRM_AMD_DC)
3369 * We have systems in the wild with these ASICs that require
3370 * LVDS and VGA support which is not supported with DC.
3372 * Fallback to the non-DC driver here by default so as not to
3373 * cause regressions.
3375 #if defined(CONFIG_DRM_AMD_DC_SI)
3376 return amdgpu_dc > 0;
3385 * We have systems in the wild with these ASICs that require
3386 * VGA support which is not supported with DC.
3388 * Fallback to the non-DC driver here by default so as not to
3389 * cause regressions.
3391 return amdgpu_dc > 0;
3393 return amdgpu_dc != 0;
3397 DRM_INFO_ONCE("Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n");
3404 * amdgpu_device_has_dc_support - check if dc is supported
3406 * @adev: amdgpu_device pointer
3408 * Returns true for supported, false for not supported
3410 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3412 if (adev->enable_virtual_display ||
3413 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3416 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3419 static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3421 struct amdgpu_device *adev =
3422 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3423 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3425 /* It's a bug to not have a hive within this function */
3430 * Use task barrier to synchronize all xgmi reset works across the
3431 * hive. task_barrier_enter and task_barrier_exit will block
3432 * until all the threads running the xgmi reset works reach
3433 * those points. task_barrier_full will do both blocks.
3435 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3437 task_barrier_enter(&hive->tb);
3438 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3440 if (adev->asic_reset_res)
3443 task_barrier_exit(&hive->tb);
3444 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3446 if (adev->asic_reset_res)
3449 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops &&
3450 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
3451 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev);
3454 task_barrier_full(&hive->tb);
3455 adev->asic_reset_res = amdgpu_asic_reset(adev);
3459 if (adev->asic_reset_res)
3460 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3461 adev->asic_reset_res, adev_to_drm(adev)->unique);
3462 amdgpu_put_xgmi_hive(hive);
3465 static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3467 char *input = amdgpu_lockup_timeout;
3468 char *timeout_setting = NULL;
3474 * By default timeout for non compute jobs is 10000
3475 * and 60000 for compute jobs.
3476 * In SR-IOV or passthrough mode, timeout for compute
3477 * jobs are 60000 by default.
3479 adev->gfx_timeout = msecs_to_jiffies(10000);
3480 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3481 if (amdgpu_sriov_vf(adev))
3482 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3483 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3485 adev->compute_timeout = msecs_to_jiffies(60000);
3487 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3488 while ((timeout_setting = strsep(&input, ",")) &&
3489 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3490 ret = kstrtol(timeout_setting, 0, &timeout);
3497 } else if (timeout < 0) {
3498 timeout = MAX_SCHEDULE_TIMEOUT;
3499 dev_warn(adev->dev, "lockup timeout disabled");
3500 add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
3502 timeout = msecs_to_jiffies(timeout);
3507 adev->gfx_timeout = timeout;
3510 adev->compute_timeout = timeout;
3513 adev->sdma_timeout = timeout;
3516 adev->video_timeout = timeout;
3523 * There is only one value specified and
3524 * it should apply to all non-compute jobs.
3527 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3528 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3529 adev->compute_timeout = adev->gfx_timeout;
3537 * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU
3539 * @adev: amdgpu_device pointer
3541 * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode
3543 static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)
3545 struct iommu_domain *domain;
3547 domain = iommu_get_domain_for_dev(adev->dev);
3548 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
3549 adev->ram_is_direct_mapped = true;
3552 static const struct attribute *amdgpu_dev_attributes[] = {
3553 &dev_attr_product_name.attr,
3554 &dev_attr_product_number.attr,
3555 &dev_attr_serial_number.attr,
3556 &dev_attr_pcie_replay_count.attr,
3560 static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)
3562 if (amdgpu_mcbp == 1)
3563 adev->gfx.mcbp = true;
3565 if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 0, 0)) &&
3566 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 0, 0)) &&
3567 adev->gfx.num_gfx_rings)
3568 adev->gfx.mcbp = true;
3570 if (amdgpu_sriov_vf(adev))
3571 adev->gfx.mcbp = true;
3574 DRM_INFO("MCBP is enabled\n");
3578 * amdgpu_device_init - initialize the driver
3580 * @adev: amdgpu_device pointer
3581 * @flags: driver flags
3583 * Initializes the driver info and hw (all asics).
3584 * Returns 0 for success or an error on failure.
3585 * Called at driver startup.
3587 int amdgpu_device_init(struct amdgpu_device *adev,
3590 struct drm_device *ddev = adev_to_drm(adev);
3591 struct pci_dev *pdev = adev->pdev;
3597 adev->shutdown = false;
3598 adev->flags = flags;
3600 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3601 adev->asic_type = amdgpu_force_asic_type;
3603 adev->asic_type = flags & AMD_ASIC_MASK;
3605 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3606 if (amdgpu_emu_mode == 1)
3607 adev->usec_timeout *= 10;
3608 adev->gmc.gart_size = 512 * 1024 * 1024;
3609 adev->accel_working = false;
3610 adev->num_rings = 0;
3611 RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
3612 adev->mman.buffer_funcs = NULL;
3613 adev->mman.buffer_funcs_ring = NULL;
3614 adev->vm_manager.vm_pte_funcs = NULL;
3615 adev->vm_manager.vm_pte_num_scheds = 0;
3616 adev->gmc.gmc_funcs = NULL;
3617 adev->harvest_ip_mask = 0x0;
3618 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3619 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3621 adev->smc_rreg = &amdgpu_invalid_rreg;
3622 adev->smc_wreg = &amdgpu_invalid_wreg;
3623 adev->pcie_rreg = &amdgpu_invalid_rreg;
3624 adev->pcie_wreg = &amdgpu_invalid_wreg;
3625 adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext;
3626 adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext;
3627 adev->pciep_rreg = &amdgpu_invalid_rreg;
3628 adev->pciep_wreg = &amdgpu_invalid_wreg;
3629 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3630 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3631 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3632 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3633 adev->didt_rreg = &amdgpu_invalid_rreg;
3634 adev->didt_wreg = &amdgpu_invalid_wreg;
3635 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3636 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3637 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3638 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3640 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3641 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3642 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3644 /* mutex initialization are all done here so we
3645 * can recall function without having locking issues
3647 mutex_init(&adev->firmware.mutex);
3648 mutex_init(&adev->pm.mutex);
3649 mutex_init(&adev->gfx.gpu_clock_mutex);
3650 mutex_init(&adev->srbm_mutex);
3651 mutex_init(&adev->gfx.pipe_reserve_mutex);
3652 mutex_init(&adev->gfx.gfx_off_mutex);
3653 mutex_init(&adev->gfx.partition_mutex);
3654 mutex_init(&adev->grbm_idx_mutex);
3655 mutex_init(&adev->mn_lock);
3656 mutex_init(&adev->virt.vf_errors.lock);
3657 hash_init(adev->mn_hash);
3658 mutex_init(&adev->psp.mutex);
3659 mutex_init(&adev->notifier_lock);
3660 mutex_init(&adev->pm.stable_pstate_ctx_lock);
3661 mutex_init(&adev->benchmark_mutex);
3663 amdgpu_device_init_apu_flags(adev);
3665 r = amdgpu_device_check_arguments(adev);
3669 spin_lock_init(&adev->mmio_idx_lock);
3670 spin_lock_init(&adev->smc_idx_lock);
3671 spin_lock_init(&adev->pcie_idx_lock);
3672 spin_lock_init(&adev->uvd_ctx_idx_lock);
3673 spin_lock_init(&adev->didt_idx_lock);
3674 spin_lock_init(&adev->gc_cac_idx_lock);
3675 spin_lock_init(&adev->se_cac_idx_lock);
3676 spin_lock_init(&adev->audio_endpt_idx_lock);
3677 spin_lock_init(&adev->mm_stats.lock);
3679 INIT_LIST_HEAD(&adev->shadow_list);
3680 mutex_init(&adev->shadow_list_lock);
3682 INIT_LIST_HEAD(&adev->reset_list);
3684 INIT_LIST_HEAD(&adev->ras_list);
3686 INIT_DELAYED_WORK(&adev->delayed_init_work,
3687 amdgpu_device_delayed_init_work_handler);
3688 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3689 amdgpu_device_delay_enable_gfx_off);
3691 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3693 adev->gfx.gfx_off_req_count = 1;
3694 adev->gfx.gfx_off_residency = 0;
3695 adev->gfx.gfx_off_entrycount = 0;
3696 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3698 atomic_set(&adev->throttling_logging_enabled, 1);
3700 * If throttling continues, logging will be performed every minute
3701 * to avoid log flooding. "-1" is subtracted since the thermal
3702 * throttling interrupt comes every second. Thus, the total logging
3703 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3704 * for throttling interrupt) = 60 seconds.
3706 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3707 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
3709 /* Registers mapping */
3710 /* TODO: block userspace mapping of io register */
3711 if (adev->asic_type >= CHIP_BONAIRE) {
3712 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3713 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3715 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3716 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3719 for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
3720 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
3722 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3726 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3727 DRM_INFO("register mmio size: %u\n", (unsigned int)adev->rmmio_size);
3730 * Reset domain needs to be present early, before XGMI hive discovered
3731 * (if any) and intitialized to use reset sem and in_gpu reset flag
3732 * early on during init and before calling to RREG32.
3734 adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");
3735 if (!adev->reset_domain)
3738 /* detect hw virtualization here */
3739 amdgpu_detect_virtualization(adev);
3741 amdgpu_device_get_pcie_info(adev);
3743 r = amdgpu_device_get_job_timeout_settings(adev);
3745 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3749 /* early init functions */
3750 r = amdgpu_device_ip_early_init(adev);
3754 amdgpu_device_set_mcbp(adev);
3756 /* Get rid of things like offb */
3757 r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver);
3761 /* Enable TMZ based on IP_VERSION */
3762 amdgpu_gmc_tmz_set(adev);
3764 amdgpu_gmc_noretry_set(adev);
3765 /* Need to get xgmi info early to decide the reset behavior*/
3766 if (adev->gmc.xgmi.supported) {
3767 r = adev->gfxhub.funcs->get_xgmi_info(adev);
3772 /* enable PCIE atomic ops */
3773 if (amdgpu_sriov_vf(adev)) {
3774 if (adev->virt.fw_reserve.p_pf2vf)
3775 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
3776 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
3777 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3778 /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a
3779 * internal path natively support atomics, set have_atomics_support to true.
3781 } else if ((adev->flags & AMD_IS_APU) &&
3782 (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))) {
3783 adev->have_atomics_support = true;
3785 adev->have_atomics_support =
3786 !pci_enable_atomic_ops_to_root(adev->pdev,
3787 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
3788 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3791 if (!adev->have_atomics_support)
3792 dev_info(adev->dev, "PCIE atomic ops is not supported\n");
3794 /* doorbell bar mapping and doorbell index init*/
3795 amdgpu_doorbell_init(adev);
3797 if (amdgpu_emu_mode == 1) {
3798 /* post the asic on emulation mode */
3799 emu_soc_asic_init(adev);
3800 goto fence_driver_init;
3803 amdgpu_reset_init(adev);
3805 /* detect if we are with an SRIOV vbios */
3807 amdgpu_device_detect_sriov_bios(adev);
3809 /* check if we need to reset the asic
3810 * E.g., driver was not cleanly unloaded previously, etc.
3812 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
3813 if (adev->gmc.xgmi.num_physical_nodes) {
3814 dev_info(adev->dev, "Pending hive reset.\n");
3815 adev->gmc.xgmi.pending_reset = true;
3816 /* Only need to init necessary block for SMU to handle the reset */
3817 for (i = 0; i < adev->num_ip_blocks; i++) {
3818 if (!adev->ip_blocks[i].status.valid)
3820 if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3821 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3822 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3823 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) {
3824 DRM_DEBUG("IP %s disabled for hw_init.\n",
3825 adev->ip_blocks[i].version->funcs->name);
3826 adev->ip_blocks[i].status.hw = true;
3830 tmp = amdgpu_reset_method;
3831 /* It should do a default reset when loading or reloading the driver,
3832 * regardless of the module parameter reset_method.
3834 amdgpu_reset_method = AMD_RESET_METHOD_NONE;
3835 r = amdgpu_asic_reset(adev);
3836 amdgpu_reset_method = tmp;
3838 dev_err(adev->dev, "asic reset on init failed\n");
3844 /* Post card if necessary */
3845 if (amdgpu_device_need_post(adev)) {
3847 dev_err(adev->dev, "no vBIOS found\n");
3851 DRM_INFO("GPU posting now...\n");
3852 r = amdgpu_device_asic_init(adev);
3854 dev_err(adev->dev, "gpu post error!\n");
3860 if (adev->is_atom_fw) {
3861 /* Initialize clocks */
3862 r = amdgpu_atomfirmware_get_clock_info(adev);
3864 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
3865 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3869 /* Initialize clocks */
3870 r = amdgpu_atombios_get_clock_info(adev);
3872 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
3873 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3876 /* init i2c buses */
3877 if (!amdgpu_device_has_dc_support(adev))
3878 amdgpu_atombios_i2c_init(adev);
3884 r = amdgpu_fence_driver_sw_init(adev);
3886 dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n");
3887 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
3891 /* init the mode config */
3892 drm_mode_config_init(adev_to_drm(adev));
3894 r = amdgpu_device_ip_init(adev);
3896 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
3897 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
3898 goto release_ras_con;
3901 amdgpu_fence_driver_hw_init(adev);
3904 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
3905 adev->gfx.config.max_shader_engines,
3906 adev->gfx.config.max_sh_per_se,
3907 adev->gfx.config.max_cu_per_sh,
3908 adev->gfx.cu_info.number);
3910 adev->accel_working = true;
3912 amdgpu_vm_check_compute_bug(adev);
3914 /* Initialize the buffer migration limit. */
3915 if (amdgpu_moverate >= 0)
3916 max_MBps = amdgpu_moverate;
3918 max_MBps = 8; /* Allow 8 MB/s. */
3919 /* Get a log2 for easy divisions. */
3920 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
3922 r = amdgpu_atombios_sysfs_init(adev);
3924 drm_err(&adev->ddev,
3925 "registering atombios sysfs failed (%d).\n", r);
3927 r = amdgpu_pm_sysfs_init(adev);
3929 DRM_ERROR("registering pm sysfs failed (%d).\n", r);
3931 r = amdgpu_ucode_sysfs_init(adev);
3933 adev->ucode_sysfs_en = false;
3934 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
3936 adev->ucode_sysfs_en = true;
3939 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3940 * Otherwise the mgpu fan boost feature will be skipped due to the
3941 * gpu instance is counted less.
3943 amdgpu_register_gpu_instance(adev);
3945 /* enable clockgating, etc. after ib tests, etc. since some blocks require
3946 * explicit gating rather than handling it automatically.
3948 if (!adev->gmc.xgmi.pending_reset) {
3949 r = amdgpu_device_ip_late_init(adev);
3951 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
3952 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
3953 goto release_ras_con;
3956 amdgpu_ras_resume(adev);
3957 queue_delayed_work(system_wq, &adev->delayed_init_work,
3958 msecs_to_jiffies(AMDGPU_RESUME_MS));
3961 if (amdgpu_sriov_vf(adev)) {
3962 amdgpu_virt_release_full_gpu(adev, true);
3963 flush_delayed_work(&adev->delayed_init_work);
3966 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
3968 dev_err(adev->dev, "Could not create amdgpu device attr\n");
3970 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3971 r = amdgpu_pmu_init(adev);
3973 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
3975 /* Have stored pci confspace at hand for restore in sudden PCI error */
3976 if (amdgpu_device_cache_pci_state(adev->pdev))
3977 pci_restore_state(pdev);
3979 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
3980 /* this will fail for cards that aren't VGA class devices, just
3983 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3984 vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
3986 px = amdgpu_device_supports_px(ddev);
3988 if (px || (!pci_is_thunderbolt_attached(adev->pdev) &&
3989 apple_gmux_detect(NULL, NULL)))
3990 vga_switcheroo_register_client(adev->pdev,
3991 &amdgpu_switcheroo_ops, px);
3994 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
3996 if (adev->gmc.xgmi.pending_reset)
3997 queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
3998 msecs_to_jiffies(AMDGPU_RESUME_MS));
4000 amdgpu_device_check_iommu_direct_map(adev);
4005 if (amdgpu_sriov_vf(adev))
4006 amdgpu_virt_release_full_gpu(adev, true);
4008 /* failed in exclusive mode due to timeout */
4009 if (amdgpu_sriov_vf(adev) &&
4010 !amdgpu_sriov_runtime(adev) &&
4011 amdgpu_virt_mmio_blocked(adev) &&
4012 !amdgpu_virt_wait_reset(adev)) {
4013 dev_err(adev->dev, "VF exclusive mode timeout\n");
4014 /* Don't send request since VF is inactive. */
4015 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
4016 adev->virt.ops = NULL;
4019 amdgpu_release_ras_context(adev);
4022 amdgpu_vf_error_trans_all(adev);
4027 static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
4030 /* Clear all CPU mappings pointing to this device */
4031 unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
4033 /* Unmap all mapped bars - Doorbell, registers and VRAM */
4034 amdgpu_doorbell_fini(adev);
4036 iounmap(adev->rmmio);
4038 if (adev->mman.aper_base_kaddr)
4039 iounmap(adev->mman.aper_base_kaddr);
4040 adev->mman.aper_base_kaddr = NULL;
4042 /* Memory manager related */
4043 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
4044 arch_phys_wc_del(adev->gmc.vram_mtrr);
4045 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
4050 * amdgpu_device_fini_hw - tear down the driver
4052 * @adev: amdgpu_device pointer
4054 * Tear down the driver info (all asics).
4055 * Called at driver shutdown.
4057 void amdgpu_device_fini_hw(struct amdgpu_device *adev)
4059 dev_info(adev->dev, "amdgpu: finishing device.\n");
4060 flush_delayed_work(&adev->delayed_init_work);
4061 adev->shutdown = true;
4063 /* make sure IB test finished before entering exclusive mode
4064 * to avoid preemption on IB test
4066 if (amdgpu_sriov_vf(adev)) {
4067 amdgpu_virt_request_full_gpu(adev, false);
4068 amdgpu_virt_fini_data_exchange(adev);
4071 /* disable all interrupts */
4072 amdgpu_irq_disable_all(adev);
4073 if (adev->mode_info.mode_config_initialized) {
4074 if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
4075 drm_helper_force_disable_all(adev_to_drm(adev));
4077 drm_atomic_helper_shutdown(adev_to_drm(adev));
4079 amdgpu_fence_driver_hw_fini(adev);
4081 if (adev->mman.initialized)
4082 drain_workqueue(adev->mman.bdev.wq);
4084 if (adev->pm.sysfs_initialized)
4085 amdgpu_pm_sysfs_fini(adev);
4086 if (adev->ucode_sysfs_en)
4087 amdgpu_ucode_sysfs_fini(adev);
4088 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
4090 /* disable ras feature must before hw fini */
4091 amdgpu_ras_pre_fini(adev);
4093 amdgpu_device_ip_fini_early(adev);
4095 amdgpu_irq_fini_hw(adev);
4097 if (adev->mman.initialized)
4098 ttm_device_clear_dma_mappings(&adev->mman.bdev);
4100 amdgpu_gart_dummy_page_fini(adev);
4102 if (drm_dev_is_unplugged(adev_to_drm(adev)))
4103 amdgpu_device_unmap_mmio(adev);
4107 void amdgpu_device_fini_sw(struct amdgpu_device *adev)
4112 amdgpu_fence_driver_sw_fini(adev);
4113 amdgpu_device_ip_fini(adev);
4114 amdgpu_ucode_release(&adev->firmware.gpu_info_fw);
4115 adev->accel_working = false;
4116 dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));
4118 amdgpu_reset_fini(adev);
4120 /* free i2c buses */
4121 if (!amdgpu_device_has_dc_support(adev))
4122 amdgpu_i2c_fini(adev);
4124 if (amdgpu_emu_mode != 1)
4125 amdgpu_atombios_fini(adev);
4130 px = amdgpu_device_supports_px(adev_to_drm(adev));
4132 if (px || (!pci_is_thunderbolt_attached(adev->pdev) &&
4133 apple_gmux_detect(NULL, NULL)))
4134 vga_switcheroo_unregister_client(adev->pdev);
4137 vga_switcheroo_fini_domain_pm_ops(adev->dev);
4139 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4140 vga_client_unregister(adev->pdev);
4142 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
4144 iounmap(adev->rmmio);
4146 amdgpu_doorbell_fini(adev);
4150 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4151 amdgpu_pmu_fini(adev);
4152 if (adev->mman.discovery_bin)
4153 amdgpu_discovery_fini(adev);
4155 amdgpu_reset_put_reset_domain(adev->reset_domain);
4156 adev->reset_domain = NULL;
4158 kfree(adev->pci_state);
4163 * amdgpu_device_evict_resources - evict device resources
4164 * @adev: amdgpu device object
4166 * Evicts all ttm device resources(vram BOs, gart table) from the lru list
4167 * of the vram memory type. Mainly used for evicting device resources
4171 static int amdgpu_device_evict_resources(struct amdgpu_device *adev)
4175 /* No need to evict vram on APUs for suspend to ram or s2idle */
4176 if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
4179 ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
4181 DRM_WARN("evicting device resources failed\n");
4189 * amdgpu_device_suspend - initiate device suspend
4191 * @dev: drm dev pointer
4192 * @fbcon : notify the fbdev of suspend
4194 * Puts the hw in the suspend state (all asics).
4195 * Returns 0 for success or an error on failure.
4196 * Called at driver suspend.
4198 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
4200 struct amdgpu_device *adev = drm_to_adev(dev);
4203 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4206 adev->in_suspend = true;
4208 /* Evict the majority of BOs before grabbing the full access */
4209 r = amdgpu_device_evict_resources(adev);
4213 if (amdgpu_sriov_vf(adev)) {
4214 amdgpu_virt_fini_data_exchange(adev);
4215 r = amdgpu_virt_request_full_gpu(adev, false);
4220 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
4221 DRM_WARN("smart shift update failed\n");
4224 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
4226 cancel_delayed_work_sync(&adev->delayed_init_work);
4228 amdgpu_ras_suspend(adev);
4230 amdgpu_device_ip_suspend_phase1(adev);
4233 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
4235 r = amdgpu_device_evict_resources(adev);
4239 amdgpu_fence_driver_hw_fini(adev);
4241 amdgpu_device_ip_suspend_phase2(adev);
4243 if (amdgpu_sriov_vf(adev))
4244 amdgpu_virt_release_full_gpu(adev, false);
4250 * amdgpu_device_resume - initiate device resume
4252 * @dev: drm dev pointer
4253 * @fbcon : notify the fbdev of resume
4255 * Bring the hw back to operating state (all asics).
4256 * Returns 0 for success or an error on failure.
4257 * Called at driver resume.
4259 int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
4261 struct amdgpu_device *adev = drm_to_adev(dev);
4264 if (amdgpu_sriov_vf(adev)) {
4265 r = amdgpu_virt_request_full_gpu(adev, true);
4270 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4274 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);
4277 if (amdgpu_device_need_post(adev)) {
4278 r = amdgpu_device_asic_init(adev);
4280 dev_err(adev->dev, "amdgpu asic init failed\n");
4283 r = amdgpu_device_ip_resume(adev);
4286 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
4289 amdgpu_fence_driver_hw_init(adev);
4291 r = amdgpu_device_ip_late_init(adev);
4295 queue_delayed_work(system_wq, &adev->delayed_init_work,
4296 msecs_to_jiffies(AMDGPU_RESUME_MS));
4298 if (!adev->in_s0ix) {
4299 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
4305 if (amdgpu_sriov_vf(adev)) {
4306 amdgpu_virt_init_data_exchange(adev);
4307 amdgpu_virt_release_full_gpu(adev, true);
4313 /* Make sure IB tests flushed */
4314 flush_delayed_work(&adev->delayed_init_work);
4317 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
4319 amdgpu_ras_resume(adev);
4321 if (adev->mode_info.num_crtc) {
4323 * Most of the connector probing functions try to acquire runtime pm
4324 * refs to ensure that the GPU is powered on when connector polling is
4325 * performed. Since we're calling this from a runtime PM callback,
4326 * trying to acquire rpm refs will cause us to deadlock.
4328 * Since we're guaranteed to be holding the rpm lock, it's safe to
4329 * temporarily disable the rpm helpers so this doesn't deadlock us.
4332 dev->dev->power.disable_depth++;
4334 if (!adev->dc_enabled)
4335 drm_helper_hpd_irq_event(dev);
4337 drm_kms_helper_hotplug_event(dev);
4339 dev->dev->power.disable_depth--;
4342 adev->in_suspend = false;
4344 if (adev->enable_mes)
4345 amdgpu_mes_self_test(adev);
4347 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
4348 DRM_WARN("smart shift update failed\n");
4354 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
4356 * @adev: amdgpu_device pointer
4358 * The list of all the hardware IPs that make up the asic is walked and
4359 * the check_soft_reset callbacks are run. check_soft_reset determines
4360 * if the asic is still hung or not.
4361 * Returns true if any of the IPs are still in a hung state, false if not.
4363 static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
4366 bool asic_hang = false;
4368 if (amdgpu_sriov_vf(adev))
4371 if (amdgpu_asic_need_full_reset(adev))
4374 for (i = 0; i < adev->num_ip_blocks; i++) {
4375 if (!adev->ip_blocks[i].status.valid)
4377 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
4378 adev->ip_blocks[i].status.hang =
4379 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
4380 if (adev->ip_blocks[i].status.hang) {
4381 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
4389 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
4391 * @adev: amdgpu_device pointer
4393 * The list of all the hardware IPs that make up the asic is walked and the
4394 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
4395 * handles any IP specific hardware or software state changes that are
4396 * necessary for a soft reset to succeed.
4397 * Returns 0 on success, negative error code on failure.
4399 static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
4403 for (i = 0; i < adev->num_ip_blocks; i++) {
4404 if (!adev->ip_blocks[i].status.valid)
4406 if (adev->ip_blocks[i].status.hang &&
4407 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
4408 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
4418 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
4420 * @adev: amdgpu_device pointer
4422 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
4423 * reset is necessary to recover.
4424 * Returns true if a full asic reset is required, false if not.
4426 static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
4430 if (amdgpu_asic_need_full_reset(adev))
4433 for (i = 0; i < adev->num_ip_blocks; i++) {
4434 if (!adev->ip_blocks[i].status.valid)
4436 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
4437 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
4438 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
4439 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
4440 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
4441 if (adev->ip_blocks[i].status.hang) {
4442 dev_info(adev->dev, "Some block need full reset!\n");
4451 * amdgpu_device_ip_soft_reset - do a soft reset
4453 * @adev: amdgpu_device pointer
4455 * The list of all the hardware IPs that make up the asic is walked and the
4456 * soft_reset callbacks are run if the block is hung. soft_reset handles any
4457 * IP specific hardware or software state changes that are necessary to soft
4459 * Returns 0 on success, negative error code on failure.
4461 static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
4465 for (i = 0; i < adev->num_ip_blocks; i++) {
4466 if (!adev->ip_blocks[i].status.valid)
4468 if (adev->ip_blocks[i].status.hang &&
4469 adev->ip_blocks[i].version->funcs->soft_reset) {
4470 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
4480 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
4482 * @adev: amdgpu_device pointer
4484 * The list of all the hardware IPs that make up the asic is walked and the
4485 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
4486 * handles any IP specific hardware or software state changes that are
4487 * necessary after the IP has been soft reset.
4488 * Returns 0 on success, negative error code on failure.
4490 static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4494 for (i = 0; i < adev->num_ip_blocks; i++) {
4495 if (!adev->ip_blocks[i].status.valid)
4497 if (adev->ip_blocks[i].status.hang &&
4498 adev->ip_blocks[i].version->funcs->post_soft_reset)
4499 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4508 * amdgpu_device_recover_vram - Recover some VRAM contents
4510 * @adev: amdgpu_device pointer
4512 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4513 * restore things like GPUVM page tables after a GPU reset where
4514 * the contents of VRAM might be lost.
4517 * 0 on success, negative error code on failure.
4519 static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4521 struct dma_fence *fence = NULL, *next = NULL;
4522 struct amdgpu_bo *shadow;
4523 struct amdgpu_bo_vm *vmbo;
4526 if (amdgpu_sriov_runtime(adev))
4527 tmo = msecs_to_jiffies(8000);
4529 tmo = msecs_to_jiffies(100);
4531 dev_info(adev->dev, "recover vram bo from shadow start\n");
4532 mutex_lock(&adev->shadow_list_lock);
4533 list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
4534 /* If vm is compute context or adev is APU, shadow will be NULL */
4537 shadow = vmbo->shadow;
4539 /* No need to recover an evicted BO */
4540 if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
4541 shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
4542 shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM)
4545 r = amdgpu_bo_restore_shadow(shadow, &next);
4550 tmo = dma_fence_wait_timeout(fence, false, tmo);
4551 dma_fence_put(fence);
4556 } else if (tmo < 0) {
4564 mutex_unlock(&adev->shadow_list_lock);
4567 tmo = dma_fence_wait_timeout(fence, false, tmo);
4568 dma_fence_put(fence);
4570 if (r < 0 || tmo <= 0) {
4571 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4575 dev_info(adev->dev, "recover vram bo from shadow done\n");
4581 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4583 * @adev: amdgpu_device pointer
4584 * @from_hypervisor: request from hypervisor
4586 * do VF FLR and reinitialize Asic
4587 * return 0 means succeeded otherwise failed
4589 static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4590 bool from_hypervisor)
4593 struct amdgpu_hive_info *hive = NULL;
4594 int retry_limit = 0;
4597 amdgpu_amdkfd_pre_reset(adev);
4599 if (from_hypervisor)
4600 r = amdgpu_virt_request_full_gpu(adev, true);
4602 r = amdgpu_virt_reset_gpu(adev);
4606 /* some sw clean up VF needs to do before recover */
4607 amdgpu_virt_post_reset(adev);
4609 /* Resume IP prior to SMC */
4610 r = amdgpu_device_ip_reinit_early_sriov(adev);
4614 amdgpu_virt_init_data_exchange(adev);
4616 r = amdgpu_device_fw_loading(adev);
4620 /* now we are okay to resume SMC/CP/SDMA */
4621 r = amdgpu_device_ip_reinit_late_sriov(adev);
4625 hive = amdgpu_get_xgmi_hive(adev);
4626 /* Update PSP FW topology after reset */
4627 if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
4628 r = amdgpu_xgmi_update_topology(hive, adev);
4631 amdgpu_put_xgmi_hive(hive);
4634 amdgpu_irq_gpu_reset_resume_helper(adev);
4635 r = amdgpu_ib_ring_tests(adev);
4637 amdgpu_amdkfd_post_reset(adev);
4641 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4642 amdgpu_inc_vram_lost(adev);
4643 r = amdgpu_device_recover_vram(adev);
4645 amdgpu_virt_release_full_gpu(adev, true);
4647 if (AMDGPU_RETRY_SRIOV_RESET(r)) {
4648 if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) {
4652 DRM_ERROR("GPU reset retry is beyond the retry limit\n");
4659 * amdgpu_device_has_job_running - check if there is any job in mirror list
4661 * @adev: amdgpu_device pointer
4663 * check if there is any job in mirror list
4665 bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
4668 struct drm_sched_job *job;
4670 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4671 struct amdgpu_ring *ring = adev->rings[i];
4673 if (!ring || !ring->sched.thread)
4676 spin_lock(&ring->sched.job_list_lock);
4677 job = list_first_entry_or_null(&ring->sched.pending_list,
4678 struct drm_sched_job, list);
4679 spin_unlock(&ring->sched.job_list_lock);
4687 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
4689 * @adev: amdgpu_device pointer
4691 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
4694 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
4697 if (amdgpu_gpu_recovery == 0)
4700 /* Skip soft reset check in fatal error mode */
4701 if (!amdgpu_ras_is_poison_mode_supported(adev))
4704 if (amdgpu_sriov_vf(adev))
4707 if (amdgpu_gpu_recovery == -1) {
4708 switch (adev->asic_type) {
4709 #ifdef CONFIG_DRM_AMDGPU_SI
4716 #ifdef CONFIG_DRM_AMDGPU_CIK
4723 case CHIP_CYAN_SKILLFISH:
4733 dev_info(adev->dev, "GPU recovery disabled.\n");
4737 int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
4742 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
4744 dev_info(adev->dev, "GPU mode1 reset\n");
4747 pci_clear_master(adev->pdev);
4749 amdgpu_device_cache_pci_state(adev->pdev);
4751 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
4752 dev_info(adev->dev, "GPU smu mode1 reset\n");
4753 ret = amdgpu_dpm_mode1_reset(adev);
4755 dev_info(adev->dev, "GPU psp mode1 reset\n");
4756 ret = psp_gpu_reset(adev);
4760 dev_err(adev->dev, "GPU mode1 reset failed\n");
4762 amdgpu_device_load_pci_state(adev->pdev);
4764 /* wait for asic to come out of reset */
4765 for (i = 0; i < adev->usec_timeout; i++) {
4766 u32 memsize = adev->nbio.funcs->get_memsize(adev);
4768 if (memsize != 0xffffffff)
4773 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
4777 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
4778 struct amdgpu_reset_context *reset_context)
4781 struct amdgpu_job *job = NULL;
4782 bool need_full_reset =
4783 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4785 if (reset_context->reset_req_dev == adev)
4786 job = reset_context->job;
4788 if (amdgpu_sriov_vf(adev)) {
4789 /* stop the data exchange thread */
4790 amdgpu_virt_fini_data_exchange(adev);
4793 amdgpu_fence_driver_isr_toggle(adev, true);
4795 /* block all schedulers and reset given job's ring */
4796 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4797 struct amdgpu_ring *ring = adev->rings[i];
4799 if (!ring || !ring->sched.thread)
4802 /* Clear job fence from fence drv to avoid force_completion
4803 * leave NULL and vm flush fence in fence drv
4805 amdgpu_fence_driver_clear_job_fences(ring);
4807 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
4808 amdgpu_fence_driver_force_completion(ring);
4811 amdgpu_fence_driver_isr_toggle(adev, false);
4814 drm_sched_increase_karma(&job->base);
4816 r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
4817 /* If reset handler not implemented, continue; otherwise return */
4818 if (r == -EOPNOTSUPP)
4823 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
4824 if (!amdgpu_sriov_vf(adev)) {
4826 if (!need_full_reset)
4827 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
4829 if (!need_full_reset && amdgpu_gpu_recovery &&
4830 amdgpu_device_ip_check_soft_reset(adev)) {
4831 amdgpu_device_ip_pre_soft_reset(adev);
4832 r = amdgpu_device_ip_soft_reset(adev);
4833 amdgpu_device_ip_post_soft_reset(adev);
4834 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
4835 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
4836 need_full_reset = true;
4840 if (need_full_reset)
4841 r = amdgpu_device_ip_suspend(adev);
4842 if (need_full_reset)
4843 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4845 clear_bit(AMDGPU_NEED_FULL_RESET,
4846 &reset_context->flags);
4852 static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
4856 lockdep_assert_held(&adev->reset_domain->sem);
4858 for (i = 0; i < adev->num_regs; i++) {
4859 adev->reset_dump_reg_value[i] = RREG32(adev->reset_dump_reg_list[i]);
4860 trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i],
4861 adev->reset_dump_reg_value[i]);
4867 #ifdef CONFIG_DEV_COREDUMP
4868 static ssize_t amdgpu_devcoredump_read(char *buffer, loff_t offset,
4869 size_t count, void *data, size_t datalen)
4871 struct drm_printer p;
4872 struct amdgpu_device *adev = data;
4873 struct drm_print_iterator iter;
4878 iter.start = offset;
4879 iter.remain = count;
4881 p = drm_coredump_printer(&iter);
4883 drm_printf(&p, "**** AMDGPU Device Coredump ****\n");
4884 drm_printf(&p, "kernel: " UTS_RELEASE "\n");
4885 drm_printf(&p, "module: " KBUILD_MODNAME "\n");
4886 drm_printf(&p, "time: %lld.%09ld\n", adev->reset_time.tv_sec, adev->reset_time.tv_nsec);
4887 if (adev->reset_task_info.pid)
4888 drm_printf(&p, "process_name: %s PID: %d\n",
4889 adev->reset_task_info.process_name,
4890 adev->reset_task_info.pid);
4892 if (adev->reset_vram_lost)
4893 drm_printf(&p, "VRAM is lost due to GPU reset!\n");
4894 if (adev->num_regs) {
4895 drm_printf(&p, "AMDGPU register dumps:\nOffset: Value:\n");
4897 for (i = 0; i < adev->num_regs; i++)
4898 drm_printf(&p, "0x%08x: 0x%08x\n",
4899 adev->reset_dump_reg_list[i],
4900 adev->reset_dump_reg_value[i]);
4903 return count - iter.remain;
4906 static void amdgpu_devcoredump_free(void *data)
4910 static void amdgpu_reset_capture_coredumpm(struct amdgpu_device *adev)
4912 struct drm_device *dev = adev_to_drm(adev);
4914 ktime_get_ts64(&adev->reset_time);
4915 dev_coredumpm(dev->dev, THIS_MODULE, adev, 0, GFP_KERNEL,
4916 amdgpu_devcoredump_read, amdgpu_devcoredump_free);
4920 int amdgpu_do_asic_reset(struct list_head *device_list_handle,
4921 struct amdgpu_reset_context *reset_context)
4923 struct amdgpu_device *tmp_adev = NULL;
4924 bool need_full_reset, skip_hw_reset, vram_lost = false;
4926 bool gpu_reset_for_dev_remove = 0;
4928 /* Try reset handler method first */
4929 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
4931 amdgpu_reset_reg_dumps(tmp_adev);
4933 reset_context->reset_device_list = device_list_handle;
4934 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
4935 /* If reset handler not implemented, continue; otherwise return */
4936 if (r == -EOPNOTSUPP)
4941 /* Reset handler not implemented, use the default method */
4943 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4944 skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
4946 gpu_reset_for_dev_remove =
4947 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
4948 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4951 * ASIC reset has to be done on all XGMI hive nodes ASAP
4952 * to allow proper links negotiation in FW (within 1 sec)
4954 if (!skip_hw_reset && need_full_reset) {
4955 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4956 /* For XGMI run all resets in parallel to speed up the process */
4957 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4958 tmp_adev->gmc.xgmi.pending_reset = false;
4959 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
4962 r = amdgpu_asic_reset(tmp_adev);
4965 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
4966 r, adev_to_drm(tmp_adev)->unique);
4971 /* For XGMI wait for all resets to complete before proceed */
4973 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4974 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4975 flush_work(&tmp_adev->xgmi_reset_work);
4976 r = tmp_adev->asic_reset_res;
4984 if (!r && amdgpu_ras_intr_triggered()) {
4985 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4986 if (tmp_adev->mmhub.ras && tmp_adev->mmhub.ras->ras_block.hw_ops &&
4987 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
4988 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev);
4991 amdgpu_ras_intr_cleared();
4994 /* Since the mode1 reset affects base ip blocks, the
4995 * phase1 ip blocks need to be resumed. Otherwise there
4996 * will be a BIOS signature error and the psp bootloader
4997 * can't load kdb on the next amdgpu install.
4999 if (gpu_reset_for_dev_remove) {
5000 list_for_each_entry(tmp_adev, device_list_handle, reset_list)
5001 amdgpu_device_ip_resume_phase1(tmp_adev);
5006 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5007 if (need_full_reset) {
5009 r = amdgpu_device_asic_init(tmp_adev);
5011 dev_warn(tmp_adev->dev, "asic atom init failed!");
5013 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
5014 r = amdgpu_amdkfd_resume_iommu(tmp_adev);
5018 r = amdgpu_device_ip_resume_phase1(tmp_adev);
5022 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
5023 #ifdef CONFIG_DEV_COREDUMP
5024 tmp_adev->reset_vram_lost = vram_lost;
5025 memset(&tmp_adev->reset_task_info, 0,
5026 sizeof(tmp_adev->reset_task_info));
5027 if (reset_context->job && reset_context->job->vm)
5028 tmp_adev->reset_task_info =
5029 reset_context->job->vm->task_info;
5030 amdgpu_reset_capture_coredumpm(tmp_adev);
5033 DRM_INFO("VRAM is lost due to GPU reset!\n");
5034 amdgpu_inc_vram_lost(tmp_adev);
5037 r = amdgpu_device_fw_loading(tmp_adev);
5041 r = amdgpu_device_ip_resume_phase2(tmp_adev);
5046 amdgpu_device_fill_reset_magic(tmp_adev);
5049 * Add this ASIC as tracked as reset was already
5050 * complete successfully.
5052 amdgpu_register_gpu_instance(tmp_adev);
5054 if (!reset_context->hive &&
5055 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5056 amdgpu_xgmi_add_device(tmp_adev);
5058 r = amdgpu_device_ip_late_init(tmp_adev);
5062 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false);
5065 * The GPU enters bad state once faulty pages
5066 * by ECC has reached the threshold, and ras
5067 * recovery is scheduled next. So add one check
5068 * here to break recovery if it indeed exceeds
5069 * bad page threshold, and remind user to
5070 * retire this GPU or setting one bigger
5071 * bad_page_threshold value to fix this once
5072 * probing driver again.
5074 if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {
5076 amdgpu_ras_resume(tmp_adev);
5082 /* Update PSP FW topology after reset */
5083 if (reset_context->hive &&
5084 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5085 r = amdgpu_xgmi_update_topology(
5086 reset_context->hive, tmp_adev);
5092 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
5093 r = amdgpu_ib_ring_tests(tmp_adev);
5095 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
5096 need_full_reset = true;
5103 r = amdgpu_device_recover_vram(tmp_adev);
5105 tmp_adev->asic_reset_res = r;
5109 if (need_full_reset)
5110 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5112 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5116 static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)
5119 switch (amdgpu_asic_reset_method(adev)) {
5120 case AMD_RESET_METHOD_MODE1:
5121 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
5123 case AMD_RESET_METHOD_MODE2:
5124 adev->mp1_state = PP_MP1_STATE_RESET;
5127 adev->mp1_state = PP_MP1_STATE_NONE;
5132 static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev)
5134 amdgpu_vf_error_trans_all(adev);
5135 adev->mp1_state = PP_MP1_STATE_NONE;
5138 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
5140 struct pci_dev *p = NULL;
5142 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5143 adev->pdev->bus->number, 1);
5145 pm_runtime_enable(&(p->dev));
5146 pm_runtime_resume(&(p->dev));
5152 static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
5154 enum amd_reset_method reset_method;
5155 struct pci_dev *p = NULL;
5159 * For now, only BACO and mode1 reset are confirmed
5160 * to suffer the audio issue without proper suspended.
5162 reset_method = amdgpu_asic_reset_method(adev);
5163 if ((reset_method != AMD_RESET_METHOD_BACO) &&
5164 (reset_method != AMD_RESET_METHOD_MODE1))
5167 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5168 adev->pdev->bus->number, 1);
5172 expires = pm_runtime_autosuspend_expiration(&(p->dev));
5175 * If we cannot get the audio device autosuspend delay,
5176 * a fixed 4S interval will be used. Considering 3S is
5177 * the audio controller default autosuspend delay setting.
5178 * 4S used here is guaranteed to cover that.
5180 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
5182 while (!pm_runtime_status_suspended(&(p->dev))) {
5183 if (!pm_runtime_suspend(&(p->dev)))
5186 if (expires < ktime_get_mono_fast_ns()) {
5187 dev_warn(adev->dev, "failed to suspend display audio\n");
5189 /* TODO: abort the succeeding gpu reset? */
5194 pm_runtime_disable(&(p->dev));
5200 static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
5202 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
5204 #if defined(CONFIG_DEBUG_FS)
5205 if (!amdgpu_sriov_vf(adev))
5206 cancel_work(&adev->reset_work);
5210 cancel_work(&adev->kfd.reset_work);
5212 if (amdgpu_sriov_vf(adev))
5213 cancel_work(&adev->virt.flr_work);
5215 if (con && adev->ras_enabled)
5216 cancel_work(&con->recovery_work);
5221 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
5223 * @adev: amdgpu_device pointer
5224 * @job: which job trigger hang
5225 * @reset_context: amdgpu reset context pointer
5227 * Attempt to reset the GPU if it has hung (all asics).
5228 * Attempt to do soft-reset or full-reset and reinitialize Asic
5229 * Returns 0 for success or an error on failure.
5232 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5233 struct amdgpu_job *job,
5234 struct amdgpu_reset_context *reset_context)
5236 struct list_head device_list, *device_list_handle = NULL;
5237 bool job_signaled = false;
5238 struct amdgpu_hive_info *hive = NULL;
5239 struct amdgpu_device *tmp_adev = NULL;
5241 bool need_emergency_restart = false;
5242 bool audio_suspended = false;
5243 bool gpu_reset_for_dev_remove = false;
5245 gpu_reset_for_dev_remove =
5246 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
5247 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5250 * Special case: RAS triggered and full reset isn't supported
5252 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
5255 * Flush RAM to disk so that after reboot
5256 * the user can read log and see why the system rebooted.
5258 if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) {
5259 DRM_WARN("Emergency reboot.");
5262 emergency_restart();
5265 dev_info(adev->dev, "GPU %s begin!\n",
5266 need_emergency_restart ? "jobs stop":"reset");
5268 if (!amdgpu_sriov_vf(adev))
5269 hive = amdgpu_get_xgmi_hive(adev);
5271 mutex_lock(&hive->hive_lock);
5273 reset_context->job = job;
5274 reset_context->hive = hive;
5276 * Build list of devices to reset.
5277 * In case we are in XGMI hive mode, resort the device list
5278 * to put adev in the 1st position.
5280 INIT_LIST_HEAD(&device_list);
5281 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) {
5282 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
5283 list_add_tail(&tmp_adev->reset_list, &device_list);
5284 if (gpu_reset_for_dev_remove && adev->shutdown)
5285 tmp_adev->shutdown = true;
5287 if (!list_is_first(&adev->reset_list, &device_list))
5288 list_rotate_to_front(&adev->reset_list, &device_list);
5289 device_list_handle = &device_list;
5291 list_add_tail(&adev->reset_list, &device_list);
5292 device_list_handle = &device_list;
5295 /* We need to lock reset domain only once both for XGMI and single device */
5296 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5298 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5300 /* block all schedulers and reset given job's ring */
5301 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5303 amdgpu_device_set_mp1_state(tmp_adev);
5306 * Try to put the audio codec into suspend state
5307 * before gpu reset started.
5309 * Due to the power domain of the graphics device
5310 * is shared with AZ power domain. Without this,
5311 * we may change the audio hardware from behind
5312 * the audio driver's back. That will trigger
5313 * some audio codec errors.
5315 if (!amdgpu_device_suspend_display_audio(tmp_adev))
5316 audio_suspended = true;
5318 amdgpu_ras_set_error_query_ready(tmp_adev, false);
5320 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
5322 if (!amdgpu_sriov_vf(tmp_adev))
5323 amdgpu_amdkfd_pre_reset(tmp_adev);
5326 * Mark these ASICs to be reseted as untracked first
5327 * And add them back after reset completed
5329 amdgpu_unregister_gpu_instance(tmp_adev);
5331 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
5333 /* disable ras on ALL IPs */
5334 if (!need_emergency_restart &&
5335 amdgpu_device_ip_need_full_reset(tmp_adev))
5336 amdgpu_ras_suspend(tmp_adev);
5338 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5339 struct amdgpu_ring *ring = tmp_adev->rings[i];
5341 if (!ring || !ring->sched.thread)
5344 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
5346 if (need_emergency_restart)
5347 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
5349 atomic_inc(&tmp_adev->gpu_reset_counter);
5352 if (need_emergency_restart)
5353 goto skip_sched_resume;
5356 * Must check guilty signal here since after this point all old
5357 * HW fences are force signaled.
5359 * job->base holds a reference to parent fence
5361 if (job && dma_fence_is_signaled(&job->hw_fence)) {
5362 job_signaled = true;
5363 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
5367 retry: /* Rest of adevs pre asic reset from XGMI hive. */
5368 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5369 if (gpu_reset_for_dev_remove) {
5370 /* Workaroud for ASICs need to disable SMC first */
5371 amdgpu_device_smu_fini_early(tmp_adev);
5373 r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
5374 /*TODO Should we stop ?*/
5376 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
5377 r, adev_to_drm(tmp_adev)->unique);
5378 tmp_adev->asic_reset_res = r;
5382 * Drop all pending non scheduler resets. Scheduler resets
5383 * were already dropped during drm_sched_stop
5385 amdgpu_device_stop_pending_resets(tmp_adev);
5388 /* Actual ASIC resets if needed.*/
5389 /* Host driver will handle XGMI hive reset for SRIOV */
5390 if (amdgpu_sriov_vf(adev)) {
5391 r = amdgpu_device_reset_sriov(adev, job ? false : true);
5393 adev->asic_reset_res = r;
5395 /* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */
5396 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||
5397 adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3))
5398 amdgpu_ras_resume(adev);
5400 r = amdgpu_do_asic_reset(device_list_handle, reset_context);
5401 if (r && r == -EAGAIN)
5404 if (!r && gpu_reset_for_dev_remove)
5410 /* Post ASIC reset for all devs .*/
5411 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5413 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5414 struct amdgpu_ring *ring = tmp_adev->rings[i];
5416 if (!ring || !ring->sched.thread)
5419 drm_sched_start(&ring->sched, true);
5422 if (adev->enable_mes && adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))
5423 amdgpu_mes_self_test(tmp_adev);
5425 if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled)
5426 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
5428 if (tmp_adev->asic_reset_res)
5429 r = tmp_adev->asic_reset_res;
5431 tmp_adev->asic_reset_res = 0;
5434 /* bad news, how to tell it to userspace ? */
5435 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
5436 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
5438 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
5439 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
5440 DRM_WARN("smart shift update failed\n");
5445 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5446 /* unlock kfd: SRIOV would do it separately */
5447 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
5448 amdgpu_amdkfd_post_reset(tmp_adev);
5450 /* kfd_post_reset will do nothing if kfd device is not initialized,
5451 * need to bring up kfd here if it's not be initialized before
5453 if (!adev->kfd.init_complete)
5454 amdgpu_amdkfd_device_init(adev);
5456 if (audio_suspended)
5457 amdgpu_device_resume_display_audio(tmp_adev);
5459 amdgpu_device_unset_mp1_state(tmp_adev);
5461 amdgpu_ras_set_error_query_ready(tmp_adev, true);
5465 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5467 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
5470 mutex_unlock(&hive->hive_lock);
5471 amdgpu_put_xgmi_hive(hive);
5475 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
5477 atomic_set(&adev->reset_domain->reset_res, r);
5482 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
5484 * @adev: amdgpu_device pointer
5486 * Fetchs and stores in the driver the PCIE capabilities (gen speed
5487 * and lanes) of the slot the device is in. Handles APUs and
5488 * virtualized environments where PCIE config space may not be available.
5490 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
5492 struct pci_dev *pdev;
5493 enum pci_bus_speed speed_cap, platform_speed_cap;
5494 enum pcie_link_width platform_link_width;
5496 if (amdgpu_pcie_gen_cap)
5497 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
5499 if (amdgpu_pcie_lane_cap)
5500 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
5502 /* covers APUs as well */
5503 if (pci_is_root_bus(adev->pdev->bus) && !amdgpu_passthrough(adev)) {
5504 if (adev->pm.pcie_gen_mask == 0)
5505 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
5506 if (adev->pm.pcie_mlw_mask == 0)
5507 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
5511 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
5514 pcie_bandwidth_available(adev->pdev, NULL,
5515 &platform_speed_cap, &platform_link_width);
5517 if (adev->pm.pcie_gen_mask == 0) {
5520 speed_cap = pcie_get_speed_cap(pdev);
5521 if (speed_cap == PCI_SPEED_UNKNOWN) {
5522 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5523 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5524 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5526 if (speed_cap == PCIE_SPEED_32_0GT)
5527 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5528 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5529 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5530 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5531 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
5532 else if (speed_cap == PCIE_SPEED_16_0GT)
5533 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5534 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5535 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5536 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
5537 else if (speed_cap == PCIE_SPEED_8_0GT)
5538 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5539 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5540 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5541 else if (speed_cap == PCIE_SPEED_5_0GT)
5542 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5543 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
5545 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
5548 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
5549 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5550 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5552 if (platform_speed_cap == PCIE_SPEED_32_0GT)
5553 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5554 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5555 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5556 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5557 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
5558 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
5559 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5560 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5561 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5562 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
5563 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
5564 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5565 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5566 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
5567 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
5568 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5569 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5571 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
5575 if (adev->pm.pcie_mlw_mask == 0) {
5576 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
5577 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
5579 switch (platform_link_width) {
5581 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
5582 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5583 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5584 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5585 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5586 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5587 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5590 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5591 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5592 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5593 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5594 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5595 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5598 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5599 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5600 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5601 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5602 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5605 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5606 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5607 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5608 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5611 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5612 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5613 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5616 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5617 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5620 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
5630 * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
5632 * @adev: amdgpu_device pointer
5633 * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
5635 * Return true if @peer_adev can access (DMA) @adev through the PCIe
5636 * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
5639 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
5640 struct amdgpu_device *peer_adev)
5642 #ifdef CONFIG_HSA_AMD_P2P
5643 uint64_t address_mask = peer_adev->dev->dma_mask ?
5644 ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
5645 resource_size_t aper_limit =
5646 adev->gmc.aper_base + adev->gmc.aper_size - 1;
5648 !adev->gmc.xgmi.connected_to_cpu &&
5649 !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
5651 return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
5652 adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
5653 !(adev->gmc.aper_base & address_mask ||
5654 aper_limit & address_mask));
5660 int amdgpu_device_baco_enter(struct drm_device *dev)
5662 struct amdgpu_device *adev = drm_to_adev(dev);
5663 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5665 if (!amdgpu_device_supports_baco(dev))
5668 if (ras && adev->ras_enabled &&
5669 adev->nbio.funcs->enable_doorbell_interrupt)
5670 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
5672 return amdgpu_dpm_baco_enter(adev);
5675 int amdgpu_device_baco_exit(struct drm_device *dev)
5677 struct amdgpu_device *adev = drm_to_adev(dev);
5678 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5681 if (!amdgpu_device_supports_baco(dev))
5684 ret = amdgpu_dpm_baco_exit(adev);
5688 if (ras && adev->ras_enabled &&
5689 adev->nbio.funcs->enable_doorbell_interrupt)
5690 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
5692 if (amdgpu_passthrough(adev) &&
5693 adev->nbio.funcs->clear_doorbell_interrupt)
5694 adev->nbio.funcs->clear_doorbell_interrupt(adev);
5700 * amdgpu_pci_error_detected - Called when a PCI error is detected.
5701 * @pdev: PCI device struct
5702 * @state: PCI channel state
5704 * Description: Called when a PCI error is detected.
5706 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
5708 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5710 struct drm_device *dev = pci_get_drvdata(pdev);
5711 struct amdgpu_device *adev = drm_to_adev(dev);
5714 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
5716 if (adev->gmc.xgmi.num_physical_nodes > 1) {
5717 DRM_WARN("No support for XGMI hive yet...");
5718 return PCI_ERS_RESULT_DISCONNECT;
5721 adev->pci_channel_state = state;
5724 case pci_channel_io_normal:
5725 return PCI_ERS_RESULT_CAN_RECOVER;
5726 /* Fatal error, prepare for slot reset */
5727 case pci_channel_io_frozen:
5729 * Locking adev->reset_domain->sem will prevent any external access
5730 * to GPU during PCI error recovery
5732 amdgpu_device_lock_reset_domain(adev->reset_domain);
5733 amdgpu_device_set_mp1_state(adev);
5736 * Block any work scheduling as we do for regular GPU reset
5737 * for the duration of the recovery
5739 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5740 struct amdgpu_ring *ring = adev->rings[i];
5742 if (!ring || !ring->sched.thread)
5745 drm_sched_stop(&ring->sched, NULL);
5747 atomic_inc(&adev->gpu_reset_counter);
5748 return PCI_ERS_RESULT_NEED_RESET;
5749 case pci_channel_io_perm_failure:
5750 /* Permanent error, prepare for device removal */
5751 return PCI_ERS_RESULT_DISCONNECT;
5754 return PCI_ERS_RESULT_NEED_RESET;
5758 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
5759 * @pdev: pointer to PCI device
5761 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
5764 DRM_INFO("PCI error: mmio enabled callback!!\n");
5766 /* TODO - dump whatever for debugging purposes */
5768 /* This called only if amdgpu_pci_error_detected returns
5769 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
5770 * works, no need to reset slot.
5773 return PCI_ERS_RESULT_RECOVERED;
5777 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
5778 * @pdev: PCI device struct
5780 * Description: This routine is called by the pci error recovery
5781 * code after the PCI slot has been reset, just before we
5782 * should resume normal operations.
5784 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
5786 struct drm_device *dev = pci_get_drvdata(pdev);
5787 struct amdgpu_device *adev = drm_to_adev(dev);
5789 struct amdgpu_reset_context reset_context;
5791 struct list_head device_list;
5793 DRM_INFO("PCI error: slot reset callback!!\n");
5795 memset(&reset_context, 0, sizeof(reset_context));
5797 INIT_LIST_HEAD(&device_list);
5798 list_add_tail(&adev->reset_list, &device_list);
5800 /* wait for asic to come out of reset */
5803 /* Restore PCI confspace */
5804 amdgpu_device_load_pci_state(pdev);
5806 /* confirm ASIC came out of reset */
5807 for (i = 0; i < adev->usec_timeout; i++) {
5808 memsize = amdgpu_asic_get_config_memsize(adev);
5810 if (memsize != 0xffffffff)
5814 if (memsize == 0xffffffff) {
5819 reset_context.method = AMD_RESET_METHOD_NONE;
5820 reset_context.reset_req_dev = adev;
5821 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
5822 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
5824 adev->no_hw_access = true;
5825 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
5826 adev->no_hw_access = false;
5830 r = amdgpu_do_asic_reset(&device_list, &reset_context);
5834 if (amdgpu_device_cache_pci_state(adev->pdev))
5835 pci_restore_state(adev->pdev);
5837 DRM_INFO("PCIe error recovery succeeded\n");
5839 DRM_ERROR("PCIe error recovery failed, err:%d", r);
5840 amdgpu_device_unset_mp1_state(adev);
5841 amdgpu_device_unlock_reset_domain(adev->reset_domain);
5844 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
5848 * amdgpu_pci_resume() - resume normal ops after PCI reset
5849 * @pdev: pointer to PCI device
5851 * Called when the error recovery driver tells us that its
5852 * OK to resume normal operation.
5854 void amdgpu_pci_resume(struct pci_dev *pdev)
5856 struct drm_device *dev = pci_get_drvdata(pdev);
5857 struct amdgpu_device *adev = drm_to_adev(dev);
5861 DRM_INFO("PCI error: resume callback!!\n");
5863 /* Only continue execution for the case of pci_channel_io_frozen */
5864 if (adev->pci_channel_state != pci_channel_io_frozen)
5867 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5868 struct amdgpu_ring *ring = adev->rings[i];
5870 if (!ring || !ring->sched.thread)
5873 drm_sched_start(&ring->sched, true);
5876 amdgpu_device_unset_mp1_state(adev);
5877 amdgpu_device_unlock_reset_domain(adev->reset_domain);
5880 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
5882 struct drm_device *dev = pci_get_drvdata(pdev);
5883 struct amdgpu_device *adev = drm_to_adev(dev);
5886 r = pci_save_state(pdev);
5888 kfree(adev->pci_state);
5890 adev->pci_state = pci_store_saved_state(pdev);
5892 if (!adev->pci_state) {
5893 DRM_ERROR("Failed to store PCI saved state");
5897 DRM_WARN("Failed to save PCI state, err:%d\n", r);
5904 bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
5906 struct drm_device *dev = pci_get_drvdata(pdev);
5907 struct amdgpu_device *adev = drm_to_adev(dev);
5910 if (!adev->pci_state)
5913 r = pci_load_saved_state(pdev, adev->pci_state);
5916 pci_restore_state(pdev);
5918 DRM_WARN("Failed to load PCI state, err:%d\n", r);
5925 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
5926 struct amdgpu_ring *ring)
5928 #ifdef CONFIG_X86_64
5929 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
5932 if (adev->gmc.xgmi.connected_to_cpu)
5935 if (ring && ring->funcs->emit_hdp_flush)
5936 amdgpu_ring_emit_hdp_flush(ring);
5938 amdgpu_asic_flush_hdp(adev, ring);
5941 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
5942 struct amdgpu_ring *ring)
5944 #ifdef CONFIG_X86_64
5945 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
5948 if (adev->gmc.xgmi.connected_to_cpu)
5951 amdgpu_asic_invalidate_hdp(adev, ring);
5954 int amdgpu_in_reset(struct amdgpu_device *adev)
5956 return atomic_read(&adev->reset_domain->in_gpu_reset);
5960 * amdgpu_device_halt() - bring hardware to some kind of halt state
5962 * @adev: amdgpu_device pointer
5964 * Bring hardware to some kind of halt state so that no one can touch it
5965 * any more. It will help to maintain error context when error occurred.
5966 * Compare to a simple hang, the system will keep stable at least for SSH
5967 * access. Then it should be trivial to inspect the hardware state and
5968 * see what's going on. Implemented as following:
5970 * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc),
5971 * clears all CPU mappings to device, disallows remappings through page faults
5972 * 2. amdgpu_irq_disable_all() disables all interrupts
5973 * 3. amdgpu_fence_driver_hw_fini() signals all HW fences
5974 * 4. set adev->no_hw_access to avoid potential crashes after setp 5
5975 * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings
5976 * 6. pci_disable_device() and pci_wait_for_pending_transaction()
5977 * flush any in flight DMA operations
5979 void amdgpu_device_halt(struct amdgpu_device *adev)
5981 struct pci_dev *pdev = adev->pdev;
5982 struct drm_device *ddev = adev_to_drm(adev);
5984 amdgpu_xcp_dev_unplug(adev);
5985 drm_dev_unplug(ddev);
5987 amdgpu_irq_disable_all(adev);
5989 amdgpu_fence_driver_hw_fini(adev);
5991 adev->no_hw_access = true;
5993 amdgpu_device_unmap_mmio(adev);
5995 pci_disable_device(pdev);
5996 pci_wait_for_pending_transaction(pdev);
5999 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
6002 unsigned long flags, address, data;
6005 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6006 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6008 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6009 WREG32(address, reg * 4);
6010 (void)RREG32(address);
6012 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6016 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
6019 unsigned long flags, address, data;
6021 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6022 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6024 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6025 WREG32(address, reg * 4);
6026 (void)RREG32(address);
6029 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6033 * amdgpu_device_switch_gang - switch to a new gang
6034 * @adev: amdgpu_device pointer
6035 * @gang: the gang to switch to
6037 * Try to switch to a new gang.
6038 * Returns: NULL if we switched to the new gang or a reference to the current
6041 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
6042 struct dma_fence *gang)
6044 struct dma_fence *old = NULL;
6049 old = dma_fence_get_rcu_safe(&adev->gang_submit);
6055 if (!dma_fence_is_signaled(old))
6058 } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit,
6065 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
6067 switch (adev->asic_type) {
6068 #ifdef CONFIG_DRM_AMDGPU_SI
6072 /* chips with no display hardware */
6074 #ifdef CONFIG_DRM_AMDGPU_SI
6080 #ifdef CONFIG_DRM_AMDGPU_CIK
6089 case CHIP_POLARIS10:
6090 case CHIP_POLARIS11:
6091 case CHIP_POLARIS12:
6095 /* chips with display hardware */
6099 if (!adev->ip_versions[DCE_HWIP][0] ||
6100 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
6106 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
6107 uint32_t inst, uint32_t reg_addr, char reg_name[],
6108 uint32_t expected_value, uint32_t mask)
6112 uint32_t tmp_ = RREG32(reg_addr);
6113 uint32_t loop = adev->usec_timeout;
6115 while ((tmp_ & (mask)) != (expected_value)) {
6117 loop = adev->usec_timeout;
6121 tmp_ = RREG32(reg_addr);
6124 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn",
6125 inst, reg_name, (uint32_t)expected_value,
6126 (uint32_t)(tmp_ & (mask)));