2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/kthread.h>
27 #include <linux/pci.h>
28 #include <linux/uaccess.h>
29 #include <linux/pm_runtime.h>
32 #include "amdgpu_pm.h"
33 #include "amdgpu_dm_debugfs.h"
34 #include "amdgpu_ras.h"
35 #include "amdgpu_rap.h"
36 #include "amdgpu_securedisplay.h"
37 #include "amdgpu_fw_attestation.h"
38 #include "amdgpu_umr.h"
40 #include "amdgpu_reset.h"
41 #include "amdgpu_psp_ta.h"
43 #if defined(CONFIG_DEBUG_FS)
46 * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes
48 * @read: True if reading
49 * @f: open file handle
50 * @buf: User buffer to write/read to
51 * @size: Number of bytes to write/read
52 * @pos: Offset to seek to
54 * This debugfs entry has special meaning on the offset being sought.
55 * Various bits have different meanings:
57 * Bit 62: Indicates a GRBM bank switch is needed
58 * Bit 61: Indicates a SRBM bank switch is needed (implies bit 62 is
60 * Bits 24..33: The SE or ME selector if needed
61 * Bits 34..43: The SH (or SA) or PIPE selector if needed
62 * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
64 * Bit 23: Indicates that the PM power gating lock should be held
65 * This is necessary to read registers that might be
66 * unreliable during a power gating transistion.
68 * The lower bits are the BYTE offset of the register to read. This
69 * allows reading multiple registers in a single call and having
70 * the returned size reflect that.
72 static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
73 char __user *buf, size_t size, loff_t *pos)
75 struct amdgpu_device *adev = file_inode(f)->i_private;
78 bool pm_pg_lock, use_bank, use_ring;
79 unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;
81 pm_pg_lock = use_bank = use_ring = false;
82 instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;
84 if (size & 0x3 || *pos & 0x3 ||
85 ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
88 /* are we reading registers for which a PG lock is necessary? */
89 pm_pg_lock = (*pos >> 23) & 1;
91 if (*pos & (1ULL << 62)) {
92 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
93 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
94 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
100 if (instance_bank == 0x3FF)
101 instance_bank = 0xFFFFFFFF;
103 } else if (*pos & (1ULL << 61)) {
105 me = (*pos & GENMASK_ULL(33, 24)) >> 24;
106 pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
107 queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
108 vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
112 use_bank = use_ring = false;
115 *pos &= (1UL << 22) - 1;
117 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
119 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
123 r = amdgpu_virt_enable_access_debugfs(adev);
125 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
131 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {
132 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
133 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
134 amdgpu_virt_disable_access_debugfs(adev);
137 mutex_lock(&adev->grbm_idx_mutex);
138 amdgpu_gfx_select_se_sh(adev, se_bank,
139 sh_bank, instance_bank);
140 } else if (use_ring) {
141 mutex_lock(&adev->srbm_mutex);
142 amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);
146 mutex_lock(&adev->pm.mutex);
152 value = RREG32(*pos >> 2);
153 r = put_user(value, (uint32_t *)buf);
155 r = get_user(value, (uint32_t *)buf);
157 amdgpu_mm_wreg_mmio_rlc(adev, *pos >> 2, value);
172 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
173 mutex_unlock(&adev->grbm_idx_mutex);
174 } else if (use_ring) {
175 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
176 mutex_unlock(&adev->srbm_mutex);
180 mutex_unlock(&adev->pm.mutex);
182 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
183 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
185 amdgpu_virt_disable_access_debugfs(adev);
190 * amdgpu_debugfs_regs_read - Callback for reading MMIO registers
192 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
193 size_t size, loff_t *pos)
195 return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
199 * amdgpu_debugfs_regs_write - Callback for writing MMIO registers
201 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
202 size_t size, loff_t *pos)
204 return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
207 static int amdgpu_debugfs_regs2_open(struct inode *inode, struct file *file)
209 struct amdgpu_debugfs_regs2_data *rd;
211 rd = kzalloc(sizeof *rd, GFP_KERNEL);
214 rd->adev = file_inode(file)->i_private;
215 file->private_data = rd;
216 mutex_init(&rd->lock);
221 static int amdgpu_debugfs_regs2_release(struct inode *inode, struct file *file)
223 struct amdgpu_debugfs_regs2_data *rd = file->private_data;
224 mutex_destroy(&rd->lock);
225 kfree(file->private_data);
229 static ssize_t amdgpu_debugfs_regs2_op(struct file *f, char __user *buf, u32 offset, size_t size, int write_en)
231 struct amdgpu_debugfs_regs2_data *rd = f->private_data;
232 struct amdgpu_device *adev = rd->adev;
237 if (size & 0x3 || offset & 0x3)
240 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
242 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
246 r = amdgpu_virt_enable_access_debugfs(adev);
248 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
252 mutex_lock(&rd->lock);
254 if (rd->id.use_grbm) {
255 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) ||
256 (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) {
257 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
258 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
259 amdgpu_virt_disable_access_debugfs(adev);
260 mutex_unlock(&rd->lock);
263 mutex_lock(&adev->grbm_idx_mutex);
264 amdgpu_gfx_select_se_sh(adev, rd->id.grbm.se,
266 rd->id.grbm.instance);
269 if (rd->id.use_srbm) {
270 mutex_lock(&adev->srbm_mutex);
271 amdgpu_gfx_select_me_pipe_q(adev, rd->id.srbm.me, rd->id.srbm.pipe,
272 rd->id.srbm.queue, rd->id.srbm.vmid);
276 mutex_lock(&adev->pm.mutex);
280 value = RREG32(offset >> 2);
281 r = put_user(value, (uint32_t *)buf);
283 r = get_user(value, (uint32_t *)buf);
285 amdgpu_mm_wreg_mmio_rlc(adev, offset >> 2, value);
297 if (rd->id.use_grbm) {
298 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
299 mutex_unlock(&adev->grbm_idx_mutex);
302 if (rd->id.use_srbm) {
303 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
304 mutex_unlock(&adev->srbm_mutex);
308 mutex_unlock(&adev->pm.mutex);
310 mutex_unlock(&rd->lock);
312 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
313 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
315 amdgpu_virt_disable_access_debugfs(adev);
319 static long amdgpu_debugfs_regs2_ioctl(struct file *f, unsigned int cmd, unsigned long data)
321 struct amdgpu_debugfs_regs2_data *rd = f->private_data;
325 case AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE:
326 mutex_lock(&rd->lock);
327 r = copy_from_user(&rd->id, (struct amdgpu_debugfs_regs2_iocdata *)data, sizeof rd->id);
328 mutex_unlock(&rd->lock);
329 return r ? -EINVAL : 0;
336 static ssize_t amdgpu_debugfs_regs2_read(struct file *f, char __user *buf, size_t size, loff_t *pos)
338 return amdgpu_debugfs_regs2_op(f, buf, *pos, size, 0);
341 static ssize_t amdgpu_debugfs_regs2_write(struct file *f, const char __user *buf, size_t size, loff_t *pos)
343 return amdgpu_debugfs_regs2_op(f, (char __user *)buf, *pos, size, 1);
348 * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register
350 * @f: open file handle
351 * @buf: User buffer to store read data in
352 * @size: Number of bytes to read
353 * @pos: Offset to seek to
355 * The lower bits are the BYTE offset of the register to read. This
356 * allows reading multiple registers in a single call and having
357 * the returned size reflect that.
359 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
360 size_t size, loff_t *pos)
362 struct amdgpu_device *adev = file_inode(f)->i_private;
366 if (size & 0x3 || *pos & 0x3)
369 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
371 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
375 r = amdgpu_virt_enable_access_debugfs(adev);
377 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
384 value = RREG32_PCIE(*pos);
385 r = put_user(value, (uint32_t *)buf);
397 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
398 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
399 amdgpu_virt_disable_access_debugfs(adev);
404 * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register
406 * @f: open file handle
407 * @buf: User buffer to write data from
408 * @size: Number of bytes to write
409 * @pos: Offset to seek to
411 * The lower bits are the BYTE offset of the register to write. This
412 * allows writing multiple registers in a single call and having
413 * the returned size reflect that.
415 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
416 size_t size, loff_t *pos)
418 struct amdgpu_device *adev = file_inode(f)->i_private;
422 if (size & 0x3 || *pos & 0x3)
425 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
427 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
431 r = amdgpu_virt_enable_access_debugfs(adev);
433 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
440 r = get_user(value, (uint32_t *)buf);
444 WREG32_PCIE(*pos, value);
454 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
455 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
456 amdgpu_virt_disable_access_debugfs(adev);
461 * amdgpu_debugfs_regs_didt_read - Read from a DIDT register
463 * @f: open file handle
464 * @buf: User buffer to store read data in
465 * @size: Number of bytes to read
466 * @pos: Offset to seek to
468 * The lower bits are the BYTE offset of the register to read. This
469 * allows reading multiple registers in a single call and having
470 * the returned size reflect that.
472 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
473 size_t size, loff_t *pos)
475 struct amdgpu_device *adev = file_inode(f)->i_private;
479 if (size & 0x3 || *pos & 0x3)
482 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
484 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
488 r = amdgpu_virt_enable_access_debugfs(adev);
490 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
497 value = RREG32_DIDT(*pos >> 2);
498 r = put_user(value, (uint32_t *)buf);
510 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
511 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
512 amdgpu_virt_disable_access_debugfs(adev);
517 * amdgpu_debugfs_regs_didt_write - Write to a DIDT register
519 * @f: open file handle
520 * @buf: User buffer to write data from
521 * @size: Number of bytes to write
522 * @pos: Offset to seek to
524 * The lower bits are the BYTE offset of the register to write. This
525 * allows writing multiple registers in a single call and having
526 * the returned size reflect that.
528 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
529 size_t size, loff_t *pos)
531 struct amdgpu_device *adev = file_inode(f)->i_private;
535 if (size & 0x3 || *pos & 0x3)
538 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
540 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
544 r = amdgpu_virt_enable_access_debugfs(adev);
546 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
553 r = get_user(value, (uint32_t *)buf);
557 WREG32_DIDT(*pos >> 2, value);
567 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
568 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
569 amdgpu_virt_disable_access_debugfs(adev);
574 * amdgpu_debugfs_regs_smc_read - Read from a SMC register
576 * @f: open file handle
577 * @buf: User buffer to store read data in
578 * @size: Number of bytes to read
579 * @pos: Offset to seek to
581 * The lower bits are the BYTE offset of the register to read. This
582 * allows reading multiple registers in a single call and having
583 * the returned size reflect that.
585 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
586 size_t size, loff_t *pos)
588 struct amdgpu_device *adev = file_inode(f)->i_private;
592 if (size & 0x3 || *pos & 0x3)
595 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
597 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
601 r = amdgpu_virt_enable_access_debugfs(adev);
603 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
610 value = RREG32_SMC(*pos);
611 r = put_user(value, (uint32_t *)buf);
623 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
624 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
625 amdgpu_virt_disable_access_debugfs(adev);
630 * amdgpu_debugfs_regs_smc_write - Write to a SMC register
632 * @f: open file handle
633 * @buf: User buffer to write data from
634 * @size: Number of bytes to write
635 * @pos: Offset to seek to
637 * The lower bits are the BYTE offset of the register to write. This
638 * allows writing multiple registers in a single call and having
639 * the returned size reflect that.
641 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
642 size_t size, loff_t *pos)
644 struct amdgpu_device *adev = file_inode(f)->i_private;
648 if (size & 0x3 || *pos & 0x3)
651 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
653 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
657 r = amdgpu_virt_enable_access_debugfs(adev);
659 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
666 r = get_user(value, (uint32_t *)buf);
670 WREG32_SMC(*pos, value);
680 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
681 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
682 amdgpu_virt_disable_access_debugfs(adev);
687 * amdgpu_debugfs_gca_config_read - Read from gfx config data
689 * @f: open file handle
690 * @buf: User buffer to store read data in
691 * @size: Number of bytes to read
692 * @pos: Offset to seek to
694 * This file is used to access configuration data in a somewhat
695 * stable fashion. The format is a series of DWORDs with the first
696 * indicating which revision it is. New content is appended to the
697 * end so that older software can still read the data.
700 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
701 size_t size, loff_t *pos)
703 struct amdgpu_device *adev = file_inode(f)->i_private;
706 uint32_t *config, no_regs = 0;
708 if (size & 0x3 || *pos & 0x3)
711 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
715 /* version, increment each time something is added */
716 config[no_regs++] = 5;
717 config[no_regs++] = adev->gfx.config.max_shader_engines;
718 config[no_regs++] = adev->gfx.config.max_tile_pipes;
719 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
720 config[no_regs++] = adev->gfx.config.max_sh_per_se;
721 config[no_regs++] = adev->gfx.config.max_backends_per_se;
722 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
723 config[no_regs++] = adev->gfx.config.max_gprs;
724 config[no_regs++] = adev->gfx.config.max_gs_threads;
725 config[no_regs++] = adev->gfx.config.max_hw_contexts;
726 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
727 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
728 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
729 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
730 config[no_regs++] = adev->gfx.config.num_tile_pipes;
731 config[no_regs++] = adev->gfx.config.backend_enable_mask;
732 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
733 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
734 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
735 config[no_regs++] = adev->gfx.config.num_gpus;
736 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
737 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
738 config[no_regs++] = adev->gfx.config.gb_addr_config;
739 config[no_regs++] = adev->gfx.config.num_rbs;
742 config[no_regs++] = adev->rev_id;
743 config[no_regs++] = lower_32_bits(adev->pg_flags);
744 config[no_regs++] = lower_32_bits(adev->cg_flags);
747 config[no_regs++] = adev->family;
748 config[no_regs++] = adev->external_rev_id;
751 config[no_regs++] = adev->pdev->device;
752 config[no_regs++] = adev->pdev->revision;
753 config[no_regs++] = adev->pdev->subsystem_device;
754 config[no_regs++] = adev->pdev->subsystem_vendor;
756 /* rev==4 APU flag */
757 config[no_regs++] = adev->flags & AMD_IS_APU ? 1 : 0;
759 /* rev==5 PG/CG flag upper 32bit */
760 config[no_regs++] = upper_32_bits(adev->pg_flags);
761 config[no_regs++] = upper_32_bits(adev->cg_flags);
763 while (size && (*pos < no_regs * 4)) {
766 value = config[*pos >> 2];
767 r = put_user(value, (uint32_t *)buf);
784 * amdgpu_debugfs_sensor_read - Read from the powerplay sensors
786 * @f: open file handle
787 * @buf: User buffer to store read data in
788 * @size: Number of bytes to read
789 * @pos: Offset to seek to
791 * The offset is treated as the BYTE address of one of the sensors
792 * enumerated in amd/include/kgd_pp_interface.h under the
793 * 'amd_pp_sensors' enumeration. For instance to read the UVD VCLK
794 * you would use the offset 3 * 4 = 12.
796 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
797 size_t size, loff_t *pos)
799 struct amdgpu_device *adev = file_inode(f)->i_private;
800 int idx, x, outsize, r, valuesize;
803 if (size & 3 || *pos & 0x3)
806 if (!adev->pm.dpm_enabled)
809 /* convert offset to sensor number */
812 valuesize = sizeof(values);
814 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
816 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
820 r = amdgpu_virt_enable_access_debugfs(adev);
822 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
826 r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
828 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
829 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
832 amdgpu_virt_disable_access_debugfs(adev);
836 if (size > valuesize) {
837 amdgpu_virt_disable_access_debugfs(adev);
845 r = put_user(values[x++], (int32_t *)buf);
852 amdgpu_virt_disable_access_debugfs(adev);
853 return !r ? outsize : r;
856 /** amdgpu_debugfs_wave_read - Read WAVE STATUS data
858 * @f: open file handle
859 * @buf: User buffer to store read data in
860 * @size: Number of bytes to read
861 * @pos: Offset to seek to
863 * The offset being sought changes which wave that the status data
864 * will be returned for. The bits are used as follows:
866 * Bits 0..6: Byte offset into data
867 * Bits 7..14: SE selector
868 * Bits 15..22: SH/SA selector
869 * Bits 23..30: CU/{WGP+SIMD} selector
870 * Bits 31..36: WAVE ID selector
871 * Bits 37..44: SIMD ID selector
873 * The returned data begins with one DWORD of version information
874 * Followed by WAVE STATUS registers relevant to the GFX IP version
875 * being used. See gfx_v8_0_read_wave_data() for an example output.
877 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
878 size_t size, loff_t *pos)
880 struct amdgpu_device *adev = f->f_inode->i_private;
883 uint32_t offset, se, sh, cu, wave, simd, data[32];
885 if (size & 3 || *pos & 3)
889 offset = (*pos & GENMASK_ULL(6, 0));
890 se = (*pos & GENMASK_ULL(14, 7)) >> 7;
891 sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
892 cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
893 wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
894 simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
896 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
898 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
902 r = amdgpu_virt_enable_access_debugfs(adev);
904 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
908 /* switch to the specific se/sh/cu */
909 mutex_lock(&adev->grbm_idx_mutex);
910 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
913 if (adev->gfx.funcs->read_wave_data)
914 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
916 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
917 mutex_unlock(&adev->grbm_idx_mutex);
919 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
920 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
923 amdgpu_virt_disable_access_debugfs(adev);
927 while (size && (offset < x * 4)) {
930 value = data[offset >> 2];
931 r = put_user(value, (uint32_t *)buf);
933 amdgpu_virt_disable_access_debugfs(adev);
943 amdgpu_virt_disable_access_debugfs(adev);
947 /** amdgpu_debugfs_gpr_read - Read wave gprs
949 * @f: open file handle
950 * @buf: User buffer to store read data in
951 * @size: Number of bytes to read
952 * @pos: Offset to seek to
954 * The offset being sought changes which wave that the status data
955 * will be returned for. The bits are used as follows:
957 * Bits 0..11: Byte offset into data
958 * Bits 12..19: SE selector
959 * Bits 20..27: SH/SA selector
960 * Bits 28..35: CU/{WGP+SIMD} selector
961 * Bits 36..43: WAVE ID selector
962 * Bits 37..44: SIMD ID selector
963 * Bits 52..59: Thread selector
964 * Bits 60..61: Bank selector (VGPR=0,SGPR=1)
966 * The return data comes from the SGPR or VGPR register bank for
967 * the selected operational unit.
969 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
970 size_t size, loff_t *pos)
972 struct amdgpu_device *adev = f->f_inode->i_private;
975 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
977 if (size > 4096 || size & 3 || *pos & 3)
981 offset = (*pos & GENMASK_ULL(11, 0)) >> 2;
982 se = (*pos & GENMASK_ULL(19, 12)) >> 12;
983 sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
984 cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
985 wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
986 simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
987 thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
988 bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
990 data = kcalloc(1024, sizeof(*data), GFP_KERNEL);
994 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
998 r = amdgpu_virt_enable_access_debugfs(adev);
1002 /* switch to the specific se/sh/cu */
1003 mutex_lock(&adev->grbm_idx_mutex);
1004 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
1007 if (adev->gfx.funcs->read_wave_vgprs)
1008 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
1010 if (adev->gfx.funcs->read_wave_sgprs)
1011 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
1014 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
1015 mutex_unlock(&adev->grbm_idx_mutex);
1017 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1018 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1023 value = data[result >> 2];
1024 r = put_user(value, (uint32_t *)buf);
1026 amdgpu_virt_disable_access_debugfs(adev);
1036 amdgpu_virt_disable_access_debugfs(adev);
1040 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1046 * amdgpu_debugfs_gfxoff_write - Enable/disable GFXOFF
1048 * @f: open file handle
1049 * @buf: User buffer to write data from
1050 * @size: Number of bytes to write
1051 * @pos: Offset to seek to
1053 * Write a 32-bit zero to disable or a 32-bit non-zero to enable
1055 static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *buf,
1056 size_t size, loff_t *pos)
1058 struct amdgpu_device *adev = file_inode(f)->i_private;
1062 if (size & 0x3 || *pos & 0x3)
1065 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1067 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1074 r = get_user(value, (uint32_t *)buf);
1078 amdgpu_gfx_off_ctrl(adev, value ? true : false);
1088 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1089 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1096 * amdgpu_debugfs_gfxoff_read - read gfxoff status
1098 * @f: open file handle
1099 * @buf: User buffer to store read data in
1100 * @size: Number of bytes to read
1101 * @pos: Offset to seek to
1103 static ssize_t amdgpu_debugfs_gfxoff_read(struct file *f, char __user *buf,
1104 size_t size, loff_t *pos)
1106 struct amdgpu_device *adev = file_inode(f)->i_private;
1110 if (size & 0x3 || *pos & 0x3)
1113 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1115 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1120 u32 value = adev->gfx.gfx_off_state;
1122 r = put_user(value, (u32 *)buf);
1134 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1135 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1140 static ssize_t amdgpu_debugfs_gfxoff_status_read(struct file *f, char __user *buf,
1141 size_t size, loff_t *pos)
1143 struct amdgpu_device *adev = file_inode(f)->i_private;
1147 if (size & 0x3 || *pos & 0x3)
1150 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1152 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1159 r = amdgpu_get_gfx_off_status(adev, &value);
1163 r = put_user(value, (u32 *)buf);
1175 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1176 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1181 static const struct file_operations amdgpu_debugfs_regs2_fops = {
1182 .owner = THIS_MODULE,
1183 .unlocked_ioctl = amdgpu_debugfs_regs2_ioctl,
1184 .read = amdgpu_debugfs_regs2_read,
1185 .write = amdgpu_debugfs_regs2_write,
1186 .open = amdgpu_debugfs_regs2_open,
1187 .release = amdgpu_debugfs_regs2_release,
1188 .llseek = default_llseek
1191 static const struct file_operations amdgpu_debugfs_regs_fops = {
1192 .owner = THIS_MODULE,
1193 .read = amdgpu_debugfs_regs_read,
1194 .write = amdgpu_debugfs_regs_write,
1195 .llseek = default_llseek
1197 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
1198 .owner = THIS_MODULE,
1199 .read = amdgpu_debugfs_regs_didt_read,
1200 .write = amdgpu_debugfs_regs_didt_write,
1201 .llseek = default_llseek
1203 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
1204 .owner = THIS_MODULE,
1205 .read = amdgpu_debugfs_regs_pcie_read,
1206 .write = amdgpu_debugfs_regs_pcie_write,
1207 .llseek = default_llseek
1209 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
1210 .owner = THIS_MODULE,
1211 .read = amdgpu_debugfs_regs_smc_read,
1212 .write = amdgpu_debugfs_regs_smc_write,
1213 .llseek = default_llseek
1216 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
1217 .owner = THIS_MODULE,
1218 .read = amdgpu_debugfs_gca_config_read,
1219 .llseek = default_llseek
1222 static const struct file_operations amdgpu_debugfs_sensors_fops = {
1223 .owner = THIS_MODULE,
1224 .read = amdgpu_debugfs_sensor_read,
1225 .llseek = default_llseek
1228 static const struct file_operations amdgpu_debugfs_wave_fops = {
1229 .owner = THIS_MODULE,
1230 .read = amdgpu_debugfs_wave_read,
1231 .llseek = default_llseek
1233 static const struct file_operations amdgpu_debugfs_gpr_fops = {
1234 .owner = THIS_MODULE,
1235 .read = amdgpu_debugfs_gpr_read,
1236 .llseek = default_llseek
1239 static const struct file_operations amdgpu_debugfs_gfxoff_fops = {
1240 .owner = THIS_MODULE,
1241 .read = amdgpu_debugfs_gfxoff_read,
1242 .write = amdgpu_debugfs_gfxoff_write,
1243 .llseek = default_llseek
1246 static const struct file_operations amdgpu_debugfs_gfxoff_status_fops = {
1247 .owner = THIS_MODULE,
1248 .read = amdgpu_debugfs_gfxoff_status_read,
1249 .llseek = default_llseek
1252 static const struct file_operations *debugfs_regs[] = {
1253 &amdgpu_debugfs_regs_fops,
1254 &amdgpu_debugfs_regs2_fops,
1255 &amdgpu_debugfs_regs_didt_fops,
1256 &amdgpu_debugfs_regs_pcie_fops,
1257 &amdgpu_debugfs_regs_smc_fops,
1258 &amdgpu_debugfs_gca_config_fops,
1259 &amdgpu_debugfs_sensors_fops,
1260 &amdgpu_debugfs_wave_fops,
1261 &amdgpu_debugfs_gpr_fops,
1262 &amdgpu_debugfs_gfxoff_fops,
1263 &amdgpu_debugfs_gfxoff_status_fops,
1266 static const char *debugfs_regs_names[] = {
1272 "amdgpu_gca_config",
1277 "amdgpu_gfxoff_status",
1281 * amdgpu_debugfs_regs_init - Initialize debugfs entries that provide
1284 * @adev: The device to attach the debugfs entries to
1286 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
1288 struct drm_minor *minor = adev_to_drm(adev)->primary;
1289 struct dentry *ent, *root = minor->debugfs_root;
1292 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
1293 ent = debugfs_create_file(debugfs_regs_names[i],
1294 S_IFREG | S_IRUGO, root,
1295 adev, debugfs_regs[i]);
1296 if (!i && !IS_ERR_OR_NULL(ent))
1297 i_size_write(ent->d_inode, adev->rmmio_size);
1303 static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused)
1305 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1306 struct drm_device *dev = adev_to_drm(adev);
1309 r = pm_runtime_get_sync(dev->dev);
1311 pm_runtime_put_autosuspend(dev->dev);
1315 /* Avoid accidently unparking the sched thread during GPU reset */
1316 r = down_write_killable(&adev->reset_domain->sem);
1320 /* hold on the scheduler */
1321 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1322 struct amdgpu_ring *ring = adev->rings[i];
1324 if (!ring || !ring->sched.thread)
1326 kthread_park(ring->sched.thread);
1329 seq_printf(m, "run ib test:\n");
1330 r = amdgpu_ib_ring_tests(adev);
1332 seq_printf(m, "ib ring tests failed (%d).\n", r);
1334 seq_printf(m, "ib ring tests passed.\n");
1336 /* go on the scheduler */
1337 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1338 struct amdgpu_ring *ring = adev->rings[i];
1340 if (!ring || !ring->sched.thread)
1342 kthread_unpark(ring->sched.thread);
1345 up_write(&adev->reset_domain->sem);
1347 pm_runtime_mark_last_busy(dev->dev);
1348 pm_runtime_put_autosuspend(dev->dev);
1353 static int amdgpu_debugfs_evict_vram(void *data, u64 *val)
1355 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1356 struct drm_device *dev = adev_to_drm(adev);
1359 r = pm_runtime_get_sync(dev->dev);
1361 pm_runtime_put_autosuspend(dev->dev);
1365 *val = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
1367 pm_runtime_mark_last_busy(dev->dev);
1368 pm_runtime_put_autosuspend(dev->dev);
1374 static int amdgpu_debugfs_evict_gtt(void *data, u64 *val)
1376 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1377 struct drm_device *dev = adev_to_drm(adev);
1380 r = pm_runtime_get_sync(dev->dev);
1382 pm_runtime_put_autosuspend(dev->dev);
1386 *val = amdgpu_ttm_evict_resources(adev, TTM_PL_TT);
1388 pm_runtime_mark_last_busy(dev->dev);
1389 pm_runtime_put_autosuspend(dev->dev);
1394 static int amdgpu_debugfs_benchmark(void *data, u64 val)
1396 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1397 struct drm_device *dev = adev_to_drm(adev);
1400 r = pm_runtime_get_sync(dev->dev);
1402 pm_runtime_put_autosuspend(dev->dev);
1406 r = amdgpu_benchmark(adev, val);
1408 pm_runtime_mark_last_busy(dev->dev);
1409 pm_runtime_put_autosuspend(dev->dev);
1414 static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused)
1416 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1417 struct drm_device *dev = adev_to_drm(adev);
1418 struct drm_file *file;
1421 r = mutex_lock_interruptible(&dev->filelist_mutex);
1425 list_for_each_entry(file, &dev->filelist, lhead) {
1426 struct amdgpu_fpriv *fpriv = file->driver_priv;
1427 struct amdgpu_vm *vm = &fpriv->vm;
1429 seq_printf(m, "pid:%d\tProcess:%s ----------\n",
1430 vm->task_info.pid, vm->task_info.process_name);
1431 r = amdgpu_bo_reserve(vm->root.bo, true);
1434 amdgpu_debugfs_vm_bo_info(vm, m);
1435 amdgpu_bo_unreserve(vm->root.bo);
1438 mutex_unlock(&dev->filelist_mutex);
1443 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_test_ib);
1444 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_vm_info);
1445 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_vram_fops, amdgpu_debugfs_evict_vram,
1447 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_gtt_fops, amdgpu_debugfs_evict_gtt,
1449 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_benchmark_fops, NULL, amdgpu_debugfs_benchmark,
1452 static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring,
1453 struct dma_fence **fences)
1455 struct amdgpu_fence_driver *drv = &ring->fence_drv;
1456 uint32_t sync_seq, last_seq;
1458 last_seq = atomic_read(&ring->fence_drv.last_seq);
1459 sync_seq = ring->fence_drv.sync_seq;
1461 last_seq &= drv->num_fences_mask;
1462 sync_seq &= drv->num_fences_mask;
1465 struct dma_fence *fence, **ptr;
1468 last_seq &= drv->num_fences_mask;
1469 ptr = &drv->fences[last_seq];
1471 fence = rcu_dereference_protected(*ptr, 1);
1472 RCU_INIT_POINTER(*ptr, NULL);
1477 fences[last_seq] = fence;
1479 } while (last_seq != sync_seq);
1482 static void amdgpu_ib_preempt_signal_fences(struct dma_fence **fences,
1486 struct dma_fence *fence;
1488 for (i = 0; i < length; i++) {
1492 dma_fence_signal(fence);
1493 dma_fence_put(fence);
1497 static void amdgpu_ib_preempt_job_recovery(struct drm_gpu_scheduler *sched)
1499 struct drm_sched_job *s_job;
1500 struct dma_fence *fence;
1502 spin_lock(&sched->job_list_lock);
1503 list_for_each_entry(s_job, &sched->pending_list, list) {
1504 fence = sched->ops->run_job(s_job);
1505 dma_fence_put(fence);
1507 spin_unlock(&sched->job_list_lock);
1510 static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring)
1512 struct amdgpu_job *job;
1513 struct drm_sched_job *s_job, *tmp;
1514 uint32_t preempt_seq;
1515 struct dma_fence *fence, **ptr;
1516 struct amdgpu_fence_driver *drv = &ring->fence_drv;
1517 struct drm_gpu_scheduler *sched = &ring->sched;
1518 bool preempted = true;
1520 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
1523 preempt_seq = le32_to_cpu(*(drv->cpu_addr + 2));
1524 if (preempt_seq <= atomic_read(&drv->last_seq)) {
1529 preempt_seq &= drv->num_fences_mask;
1530 ptr = &drv->fences[preempt_seq];
1531 fence = rcu_dereference_protected(*ptr, 1);
1534 spin_lock(&sched->job_list_lock);
1535 list_for_each_entry_safe(s_job, tmp, &sched->pending_list, list) {
1536 if (dma_fence_is_signaled(&s_job->s_fence->finished)) {
1537 /* remove job from ring_mirror_list */
1538 list_del_init(&s_job->list);
1539 sched->ops->free_job(s_job);
1542 job = to_amdgpu_job(s_job);
1543 if (preempted && (&job->hw_fence) == fence)
1544 /* mark the job as preempted */
1545 job->preemption_status |= AMDGPU_IB_PREEMPTED;
1547 spin_unlock(&sched->job_list_lock);
1550 static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
1552 int r, resched, length;
1553 struct amdgpu_ring *ring;
1554 struct dma_fence **fences = NULL;
1555 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1557 if (val >= AMDGPU_MAX_RINGS)
1560 ring = adev->rings[val];
1562 if (!ring || !ring->funcs->preempt_ib || !ring->sched.thread)
1565 /* the last preemption failed */
1566 if (ring->trail_seq != le32_to_cpu(*ring->trail_fence_cpu_addr))
1569 length = ring->fence_drv.num_fences_mask + 1;
1570 fences = kcalloc(length, sizeof(void *), GFP_KERNEL);
1574 /* Avoid accidently unparking the sched thread during GPU reset */
1575 r = down_read_killable(&adev->reset_domain->sem);
1579 /* stop the scheduler */
1580 kthread_park(ring->sched.thread);
1582 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1584 /* preempt the IB */
1585 r = amdgpu_ring_preempt_ib(ring);
1587 DRM_WARN("failed to preempt ring %d\n", ring->idx);
1591 amdgpu_fence_process(ring);
1593 if (atomic_read(&ring->fence_drv.last_seq) !=
1594 ring->fence_drv.sync_seq) {
1595 DRM_INFO("ring %d was preempted\n", ring->idx);
1597 amdgpu_ib_preempt_mark_partial_job(ring);
1599 /* swap out the old fences */
1600 amdgpu_ib_preempt_fences_swap(ring, fences);
1602 amdgpu_fence_driver_force_completion(ring);
1604 /* resubmit unfinished jobs */
1605 amdgpu_ib_preempt_job_recovery(&ring->sched);
1607 /* wait for jobs finished */
1608 amdgpu_fence_wait_empty(ring);
1610 /* signal the old fences */
1611 amdgpu_ib_preempt_signal_fences(fences, length);
1615 /* restart the scheduler */
1616 kthread_unpark(ring->sched.thread);
1618 up_read(&adev->reset_domain->sem);
1620 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1628 static int amdgpu_debugfs_sclk_set(void *data, u64 val)
1631 uint32_t max_freq, min_freq;
1632 struct amdgpu_device *adev = (struct amdgpu_device *)data;
1634 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1637 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1639 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1643 ret = amdgpu_dpm_get_dpm_freq_range(adev, PP_SCLK, &min_freq, &max_freq);
1644 if (ret == -EOPNOTSUPP) {
1648 if (ret || val > max_freq || val < min_freq) {
1653 ret = amdgpu_dpm_set_soft_freq_range(adev, PP_SCLK, (uint32_t)val, (uint32_t)val);
1658 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1659 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1664 DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
1665 amdgpu_debugfs_ib_preempt, "%llu\n");
1667 DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
1668 amdgpu_debugfs_sclk_set, "%llu\n");
1670 static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,
1671 char __user *buf, size_t size, loff_t *pos)
1673 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1674 char reg_offset[12];
1675 int i, ret, len = 0;
1680 memset(reg_offset, 0, 12);
1681 ret = down_read_killable(&adev->reset_domain->sem);
1685 for (i = 0; i < adev->num_regs; i++) {
1686 sprintf(reg_offset, "0x%x\n", adev->reset_dump_reg_list[i]);
1687 up_read(&adev->reset_domain->sem);
1688 if (copy_to_user(buf + len, reg_offset, strlen(reg_offset)))
1691 len += strlen(reg_offset);
1692 ret = down_read_killable(&adev->reset_domain->sem);
1697 up_read(&adev->reset_domain->sem);
1703 static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
1704 const char __user *buf, size_t size, loff_t *pos)
1706 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1707 char reg_offset[11];
1708 uint32_t *new, *tmp = NULL;
1709 int ret, i = 0, len = 0;
1712 memset(reg_offset, 0, 11);
1713 if (copy_from_user(reg_offset, buf + len,
1714 min(10, ((int)size-len)))) {
1719 new = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
1725 if (sscanf(reg_offset, "%X %n", &tmp[i], &ret) != 1) {
1732 } while (len < size);
1734 new = kmalloc_array(i, sizeof(uint32_t), GFP_KERNEL);
1739 ret = down_write_killable(&adev->reset_domain->sem);
1743 swap(adev->reset_dump_reg_list, tmp);
1744 swap(adev->reset_dump_reg_value, new);
1746 up_write(&adev->reset_domain->sem);
1755 static const struct file_operations amdgpu_reset_dump_register_list = {
1756 .owner = THIS_MODULE,
1757 .read = amdgpu_reset_dump_register_list_read,
1758 .write = amdgpu_reset_dump_register_list_write,
1759 .llseek = default_llseek
1762 int amdgpu_debugfs_init(struct amdgpu_device *adev)
1764 struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
1768 if (!debugfs_initialized())
1771 debugfs_create_x32("amdgpu_smu_debug", 0600, root,
1772 &adev->pm.smu_debug_mask);
1774 ent = debugfs_create_file("amdgpu_preempt_ib", 0600, root, adev,
1777 DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n");
1778 return PTR_ERR(ent);
1781 ent = debugfs_create_file("amdgpu_force_sclk", 0200, root, adev,
1784 DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n");
1785 return PTR_ERR(ent);
1788 /* Register debugfs entries for amdgpu_ttm */
1789 amdgpu_ttm_debugfs_init(adev);
1790 amdgpu_debugfs_pm_init(adev);
1791 amdgpu_debugfs_sa_init(adev);
1792 amdgpu_debugfs_fence_init(adev);
1793 amdgpu_debugfs_gem_init(adev);
1795 r = amdgpu_debugfs_regs_init(adev);
1797 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1799 amdgpu_debugfs_firmware_init(adev);
1800 amdgpu_ta_if_debugfs_init(adev);
1802 #if defined(CONFIG_DRM_AMD_DC)
1803 if (amdgpu_device_has_dc_support(adev))
1804 dtn_debugfs_init(adev);
1807 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1808 struct amdgpu_ring *ring = adev->rings[i];
1813 amdgpu_debugfs_ring_init(adev, ring);
1816 for ( i = 0; i < adev->vcn.num_vcn_inst; i++) {
1817 if (!amdgpu_vcnfw_log)
1820 if (adev->vcn.harvest_config & (1 << i))
1823 amdgpu_debugfs_vcn_fwlog_init(adev, i, &adev->vcn.inst[i]);
1826 amdgpu_ras_debugfs_create_all(adev);
1827 amdgpu_rap_debugfs_init(adev);
1828 amdgpu_securedisplay_debugfs_init(adev);
1829 amdgpu_fw_attestation_debugfs_init(adev);
1831 debugfs_create_file("amdgpu_evict_vram", 0444, root, adev,
1832 &amdgpu_evict_vram_fops);
1833 debugfs_create_file("amdgpu_evict_gtt", 0444, root, adev,
1834 &amdgpu_evict_gtt_fops);
1835 debugfs_create_file("amdgpu_test_ib", 0444, root, adev,
1836 &amdgpu_debugfs_test_ib_fops);
1837 debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
1838 &amdgpu_debugfs_vm_info_fops);
1839 debugfs_create_file("amdgpu_benchmark", 0200, root, adev,
1840 &amdgpu_benchmark_fops);
1841 debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root, adev,
1842 &amdgpu_reset_dump_register_list);
1844 adev->debugfs_vbios_blob.data = adev->bios;
1845 adev->debugfs_vbios_blob.size = adev->bios_size;
1846 debugfs_create_blob("amdgpu_vbios", 0444, root,
1847 &adev->debugfs_vbios_blob);
1849 adev->debugfs_discovery_blob.data = adev->mman.discovery_bin;
1850 adev->debugfs_discovery_blob.size = adev->mman.discovery_tmr_size;
1851 debugfs_create_blob("amdgpu_discovery", 0444, root,
1852 &adev->debugfs_discovery_blob);
1858 int amdgpu_debugfs_init(struct amdgpu_device *adev)
1862 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)