2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/list.h>
25 #include <linux/slab.h>
27 #include <linux/firmware.h>
28 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_ucode.h"
33 struct amdgpu_cgs_device {
34 struct cgs_device base;
35 struct amdgpu_device *adev;
38 #define CGS_FUNC_ADEV \
39 struct amdgpu_device *adev = \
40 ((struct amdgpu_cgs_device *)cgs_device)->adev
43 static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
46 return RREG32(offset);
49 static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset,
53 WREG32(offset, value);
56 static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
57 enum cgs_ind_reg space,
62 case CGS_IND_REG__MMIO:
63 return RREG32_IDX(index);
64 case CGS_IND_REG__PCIE:
65 return RREG32_PCIE(index);
66 case CGS_IND_REG__SMC:
67 return RREG32_SMC(index);
68 case CGS_IND_REG__UVD_CTX:
69 return RREG32_UVD_CTX(index);
70 case CGS_IND_REG__DIDT:
71 return RREG32_DIDT(index);
72 case CGS_IND_REG_GC_CAC:
73 return RREG32_GC_CAC(index);
74 case CGS_IND_REG_SE_CAC:
75 return RREG32_SE_CAC(index);
76 case CGS_IND_REG__AUDIO_ENDPT:
77 DRM_ERROR("audio endpt register access not implemented.\n");
80 WARN(1, "Invalid indirect register space");
84 static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
85 enum cgs_ind_reg space,
86 unsigned index, uint32_t value)
90 case CGS_IND_REG__MMIO:
91 return WREG32_IDX(index, value);
92 case CGS_IND_REG__PCIE:
93 return WREG32_PCIE(index, value);
94 case CGS_IND_REG__SMC:
95 return WREG32_SMC(index, value);
96 case CGS_IND_REG__UVD_CTX:
97 return WREG32_UVD_CTX(index, value);
98 case CGS_IND_REG__DIDT:
99 return WREG32_DIDT(index, value);
100 case CGS_IND_REG_GC_CAC:
101 return WREG32_GC_CAC(index, value);
102 case CGS_IND_REG_SE_CAC:
103 return WREG32_SE_CAC(index, value);
104 case CGS_IND_REG__AUDIO_ENDPT:
105 DRM_ERROR("audio endpt register access not implemented.\n");
108 WARN(1, "Invalid indirect register space");
111 static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
114 enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
117 case CGS_UCODE_ID_SDMA0:
118 result = AMDGPU_UCODE_ID_SDMA0;
120 case CGS_UCODE_ID_SDMA1:
121 result = AMDGPU_UCODE_ID_SDMA1;
123 case CGS_UCODE_ID_CP_CE:
124 result = AMDGPU_UCODE_ID_CP_CE;
126 case CGS_UCODE_ID_CP_PFP:
127 result = AMDGPU_UCODE_ID_CP_PFP;
129 case CGS_UCODE_ID_CP_ME:
130 result = AMDGPU_UCODE_ID_CP_ME;
132 case CGS_UCODE_ID_CP_MEC:
133 case CGS_UCODE_ID_CP_MEC_JT1:
134 result = AMDGPU_UCODE_ID_CP_MEC1;
136 case CGS_UCODE_ID_CP_MEC_JT2:
137 /* for VI. JT2 should be the same as JT1, because:
138 1, MEC2 and MEC1 use exactly same FW.
139 2, JT2 is not pached but JT1 is.
141 if (adev->asic_type >= CHIP_TOPAZ)
142 result = AMDGPU_UCODE_ID_CP_MEC1;
144 result = AMDGPU_UCODE_ID_CP_MEC2;
146 case CGS_UCODE_ID_RLC_G:
147 result = AMDGPU_UCODE_ID_RLC_G;
149 case CGS_UCODE_ID_STORAGE:
150 result = AMDGPU_UCODE_ID_STORAGE;
153 DRM_ERROR("Firmware type not supported\n");
158 static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
159 enum cgs_ucode_id type)
162 uint16_t fw_version = 0;
165 case CGS_UCODE_ID_SDMA0:
166 fw_version = adev->sdma.instance[0].fw_version;
168 case CGS_UCODE_ID_SDMA1:
169 fw_version = adev->sdma.instance[1].fw_version;
171 case CGS_UCODE_ID_CP_CE:
172 fw_version = adev->gfx.ce_fw_version;
174 case CGS_UCODE_ID_CP_PFP:
175 fw_version = adev->gfx.pfp_fw_version;
177 case CGS_UCODE_ID_CP_ME:
178 fw_version = adev->gfx.me_fw_version;
180 case CGS_UCODE_ID_CP_MEC:
181 fw_version = adev->gfx.mec_fw_version;
183 case CGS_UCODE_ID_CP_MEC_JT1:
184 fw_version = adev->gfx.mec_fw_version;
186 case CGS_UCODE_ID_CP_MEC_JT2:
187 fw_version = adev->gfx.mec_fw_version;
189 case CGS_UCODE_ID_RLC_G:
190 fw_version = adev->gfx.rlc_fw_version;
192 case CGS_UCODE_ID_STORAGE:
195 DRM_ERROR("firmware type %d do not have version\n", type);
201 static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
202 enum cgs_ucode_id type,
203 struct cgs_firmware_info *info)
207 if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) {
210 const struct gfx_firmware_header_v1_0 *header;
211 enum AMDGPU_UCODE_ID id;
212 struct amdgpu_firmware_info *ucode;
214 id = fw_type_convert(cgs_device, type);
215 ucode = &adev->firmware.ucode[id];
216 if (ucode->fw == NULL)
219 gpu_addr = ucode->mc_addr;
220 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
221 data_size = le32_to_cpu(header->header.ucode_size_bytes);
223 if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
224 (type == CGS_UCODE_ID_CP_MEC_JT2)) {
225 gpu_addr += ALIGN(le32_to_cpu(header->header.ucode_size_bytes), PAGE_SIZE);
226 data_size = le32_to_cpu(header->jt_size) << 2;
229 info->kptr = ucode->kaddr;
230 info->image_size = data_size;
231 info->mc_addr = gpu_addr;
232 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
234 if (CGS_UCODE_ID_CP_MEC == type)
235 info->image_size = le32_to_cpu(header->jt_offset) << 2;
237 info->fw_version = amdgpu_get_firmware_version(cgs_device, type);
238 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
240 char fw_name[30] = {0};
243 uint32_t ucode_start_address;
245 const struct smc_firmware_header_v1_0 *hdr;
246 const struct common_firmware_header *header;
247 struct amdgpu_firmware_info *ucode = NULL;
250 switch (adev->asic_type) {
252 strcpy(fw_name, "radeon/tahiti_smc.bin");
255 if ((adev->pdev->revision == 0x81) &&
256 ((adev->pdev->device == 0x6810) ||
257 (adev->pdev->device == 0x6811))) {
258 info->is_kicker = true;
259 strcpy(fw_name, "radeon/pitcairn_k_smc.bin");
261 strcpy(fw_name, "radeon/pitcairn_smc.bin");
265 if (((adev->pdev->device == 0x6820) &&
266 ((adev->pdev->revision == 0x81) ||
267 (adev->pdev->revision == 0x83))) ||
268 ((adev->pdev->device == 0x6821) &&
269 ((adev->pdev->revision == 0x83) ||
270 (adev->pdev->revision == 0x87))) ||
271 ((adev->pdev->revision == 0x87) &&
272 ((adev->pdev->device == 0x6823) ||
273 (adev->pdev->device == 0x682b)))) {
274 info->is_kicker = true;
275 strcpy(fw_name, "radeon/verde_k_smc.bin");
277 strcpy(fw_name, "radeon/verde_smc.bin");
281 if (((adev->pdev->revision == 0x81) &&
282 ((adev->pdev->device == 0x6600) ||
283 (adev->pdev->device == 0x6604) ||
284 (adev->pdev->device == 0x6605) ||
285 (adev->pdev->device == 0x6610))) ||
286 ((adev->pdev->revision == 0x83) &&
287 (adev->pdev->device == 0x6610))) {
288 info->is_kicker = true;
289 strcpy(fw_name, "radeon/oland_k_smc.bin");
291 strcpy(fw_name, "radeon/oland_smc.bin");
295 if (((adev->pdev->revision == 0x81) &&
296 (adev->pdev->device == 0x6660)) ||
297 ((adev->pdev->revision == 0x83) &&
298 ((adev->pdev->device == 0x6660) ||
299 (adev->pdev->device == 0x6663) ||
300 (adev->pdev->device == 0x6665) ||
301 (adev->pdev->device == 0x6667)))) {
302 info->is_kicker = true;
303 strcpy(fw_name, "radeon/hainan_k_smc.bin");
304 } else if ((adev->pdev->revision == 0xc3) &&
305 (adev->pdev->device == 0x6665)) {
306 info->is_kicker = true;
307 strcpy(fw_name, "radeon/banks_k_2_smc.bin");
309 strcpy(fw_name, "radeon/hainan_smc.bin");
313 if ((adev->pdev->revision == 0x80) ||
314 (adev->pdev->revision == 0x81) ||
315 (adev->pdev->device == 0x665f)) {
316 info->is_kicker = true;
317 strcpy(fw_name, "amdgpu/bonaire_k_smc.bin");
319 strcpy(fw_name, "amdgpu/bonaire_smc.bin");
323 if (adev->pdev->revision == 0x80) {
324 info->is_kicker = true;
325 strcpy(fw_name, "amdgpu/hawaii_k_smc.bin");
327 strcpy(fw_name, "amdgpu/hawaii_smc.bin");
331 if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
332 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
333 ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87)) ||
334 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD1)) ||
335 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD3))) {
336 info->is_kicker = true;
337 strcpy(fw_name, "amdgpu/topaz_k_smc.bin");
339 strcpy(fw_name, "amdgpu/topaz_smc.bin");
342 if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) ||
343 ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) {
344 info->is_kicker = true;
345 strcpy(fw_name, "amdgpu/tonga_k_smc.bin");
347 strcpy(fw_name, "amdgpu/tonga_smc.bin");
350 strcpy(fw_name, "amdgpu/fiji_smc.bin");
353 if (type == CGS_UCODE_ID_SMU) {
354 if (((adev->pdev->device == 0x67ef) &&
355 ((adev->pdev->revision == 0xe0) ||
356 (adev->pdev->revision == 0xe5))) ||
357 ((adev->pdev->device == 0x67ff) &&
358 ((adev->pdev->revision == 0xcf) ||
359 (adev->pdev->revision == 0xef) ||
360 (adev->pdev->revision == 0xff)))) {
361 info->is_kicker = true;
362 strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");
363 } else if ((adev->pdev->device == 0x67ef) &&
364 (adev->pdev->revision == 0xe2)) {
365 info->is_kicker = true;
366 strcpy(fw_name, "amdgpu/polaris11_k2_smc.bin");
368 strcpy(fw_name, "amdgpu/polaris11_smc.bin");
370 } else if (type == CGS_UCODE_ID_SMU_SK) {
371 strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
375 if (type == CGS_UCODE_ID_SMU) {
376 if (((adev->pdev->device == 0x67df) &&
377 ((adev->pdev->revision == 0xe0) ||
378 (adev->pdev->revision == 0xe3) ||
379 (adev->pdev->revision == 0xe4) ||
380 (adev->pdev->revision == 0xe5) ||
381 (adev->pdev->revision == 0xe7) ||
382 (adev->pdev->revision == 0xef))) ||
383 ((adev->pdev->device == 0x6fdf) &&
384 (adev->pdev->revision == 0xef))) {
385 info->is_kicker = true;
386 strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
387 } else if ((adev->pdev->device == 0x67df) &&
388 ((adev->pdev->revision == 0xe1) ||
389 (adev->pdev->revision == 0xf7))) {
390 info->is_kicker = true;
391 strcpy(fw_name, "amdgpu/polaris10_k2_smc.bin");
393 strcpy(fw_name, "amdgpu/polaris10_smc.bin");
395 } else if (type == CGS_UCODE_ID_SMU_SK) {
396 strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
400 if (((adev->pdev->device == 0x6987) &&
401 ((adev->pdev->revision == 0xc0) ||
402 (adev->pdev->revision == 0xc3))) ||
403 ((adev->pdev->device == 0x6981) &&
404 ((adev->pdev->revision == 0x00) ||
405 (adev->pdev->revision == 0x01) ||
406 (adev->pdev->revision == 0x10)))) {
407 info->is_kicker = true;
408 strcpy(fw_name, "amdgpu/polaris12_k_smc.bin");
410 strcpy(fw_name, "amdgpu/polaris12_smc.bin");
414 strcpy(fw_name, "amdgpu/vegam_smc.bin");
417 if ((adev->pdev->device == 0x687f) &&
418 ((adev->pdev->revision == 0xc0) ||
419 (adev->pdev->revision == 0xc1) ||
420 (adev->pdev->revision == 0xc3)))
421 strcpy(fw_name, "amdgpu/vega10_acg_smc.bin");
423 strcpy(fw_name, "amdgpu/vega10_smc.bin");
426 strcpy(fw_name, "amdgpu/vega12_smc.bin");
429 strcpy(fw_name, "amdgpu/vega20_smc.bin");
432 DRM_ERROR("SMC firmware not supported\n");
436 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
438 DRM_ERROR("Failed to request firmware\n");
442 err = amdgpu_ucode_validate(adev->pm.fw);
444 DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
445 release_firmware(adev->pm.fw);
450 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
451 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
452 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
453 ucode->fw = adev->pm.fw;
454 header = (const struct common_firmware_header *)ucode->fw->data;
455 adev->firmware.fw_size +=
456 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
460 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
461 amdgpu_ucode_print_smc_hdr(&hdr->header);
462 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
463 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
464 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
465 src = (const uint8_t *)(adev->pm.fw->data +
466 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
468 info->version = adev->pm.fw_version;
469 info->image_size = ucode_size;
470 info->ucode_start_address = ucode_start_address;
471 info->kptr = (void *)src;
476 static const struct cgs_ops amdgpu_cgs_ops = {
477 .read_register = amdgpu_cgs_read_register,
478 .write_register = amdgpu_cgs_write_register,
479 .read_ind_register = amdgpu_cgs_read_ind_register,
480 .write_ind_register = amdgpu_cgs_write_ind_register,
481 .get_firmware_info = amdgpu_cgs_get_firmware_info,
484 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
486 struct amdgpu_cgs_device *cgs_device =
487 kmalloc(sizeof(*cgs_device), GFP_KERNEL);
490 DRM_ERROR("Couldn't allocate CGS device structure\n");
494 cgs_device->base.ops = &amdgpu_cgs_ops;
495 cgs_device->adev = adev;
497 return (struct cgs_device *)cgs_device;
500 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)