1 // SPDX-License-Identifier: MIT
3 * Copyright 2014-2018 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/dma-buf.h>
24 #include <linux/list.h>
25 #include <linux/pagemap.h>
26 #include <linux/sched/mm.h>
27 #include <linux/sched/task.h>
28 #include <drm/ttm/ttm_tt.h>
30 #include <drm/drm_exec.h>
32 #include "amdgpu_object.h"
33 #include "amdgpu_gem.h"
34 #include "amdgpu_vm.h"
35 #include "amdgpu_hmm.h"
36 #include "amdgpu_amdkfd.h"
37 #include "amdgpu_dma_buf.h"
38 #include <uapi/linux/kfd_ioctl.h>
39 #include "amdgpu_xgmi.h"
41 #include "kfd_smi_events.h"
43 /* Userptr restore delay, just long enough to allow consecutive VM
44 * changes to accumulate
46 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
49 * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
52 #define VRAM_AVAILABLITY_ALIGN (1 << 21)
54 /* Impose limit on how much memory KFD can use */
56 uint64_t max_system_mem_limit;
57 uint64_t max_ttm_mem_limit;
58 int64_t system_mem_used;
60 spinlock_t mem_limit_lock;
63 static const char * const domain_bit_to_string[] = {
72 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
74 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
76 static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
79 struct kfd_mem_attachment *entry;
81 list_for_each_entry(entry, &mem->attachments, list)
82 if (entry->bo_va->base.vm == avm)
89 * reuse_dmamap() - Check whether adev can share the original
92 * If both adev and bo_adev are in direct mapping or
93 * in the same iommu group, they can share the original BO.
95 * @adev: Device to which can or cannot share the original BO
96 * @bo_adev: Device to which allocated BO belongs to
98 * Return: returns true if adev can share original userptr BO,
101 static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev)
103 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) ||
104 (adev->dev->iommu_group == bo_adev->dev->iommu_group);
107 /* Set memory usage limits. Current, limits are
108 * System (TTM + userptr) memory - 15/16th System RAM
109 * TTM memory - 3/8th System RAM
111 void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
116 if (kfd_mem_limit.max_system_mem_limit)
120 mem = si.freeram - si.freehigh;
123 spin_lock_init(&kfd_mem_limit.mem_limit_lock);
124 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 4);
125 kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT;
126 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
127 (kfd_mem_limit.max_system_mem_limit >> 20),
128 (kfd_mem_limit.max_ttm_mem_limit >> 20));
131 void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
133 kfd_mem_limit.system_mem_used += size;
136 /* Estimate page table size needed to represent a given memory size
138 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
139 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
140 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
141 * for 2MB pages for TLB efficiency. However, small allocations and
142 * fragmented system memory still need some 4KB pages. We choose a
143 * compromise that should work in most cases without reserving too
144 * much memory for page tables unnecessarily (factor 16K, >> 14).
147 #define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM)
150 * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
153 * @adev: Device to which allocated BO belongs to
154 * @size: Size of buffer, in bytes, encapsulated by B0. This should be
155 * equivalent to amdgpu_bo_size(BO)
156 * @alloc_flag: Flag used in allocating a BO as noted above
157 * @xcp_id: xcp_id is used to get xcp from xcp manager, one xcp is
158 * managed as one compute node in driver for app
161 * returns -ENOMEM in case of error, ZERO otherwise
163 int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
164 uint64_t size, u32 alloc_flag, int8_t xcp_id)
166 uint64_t reserved_for_pt =
167 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
168 size_t system_mem_needed, ttm_mem_needed, vram_needed;
170 uint64_t vram_size = 0;
172 system_mem_needed = 0;
175 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
176 system_mem_needed = size;
177 ttm_mem_needed = size;
178 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
180 * Conservatively round up the allocation requirement to 2 MB
181 * to avoid fragmentation caused by 4K allocations in the tail
186 * For GFX 9.4.3, get the VRAM size from XCP structs
188 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
191 vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
192 if (adev->gmc.is_app_apu) {
193 system_mem_needed = size;
194 ttm_mem_needed = size;
196 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
197 system_mem_needed = size;
198 } else if (!(alloc_flag &
199 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
200 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
201 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
205 spin_lock(&kfd_mem_limit.mem_limit_lock);
207 if (kfd_mem_limit.system_mem_used + system_mem_needed >
208 kfd_mem_limit.max_system_mem_limit)
209 pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
211 if ((kfd_mem_limit.system_mem_used + system_mem_needed >
212 kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
213 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
214 kfd_mem_limit.max_ttm_mem_limit) ||
215 (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed >
216 vram_size - reserved_for_pt)) {
221 /* Update memory accounting by decreasing available system
222 * memory, TTM memory and GPU memory as computed above
224 WARN_ONCE(vram_needed && !adev,
225 "adev reference can't be null when vram is used");
226 if (adev && xcp_id >= 0) {
227 adev->kfd.vram_used[xcp_id] += vram_needed;
228 adev->kfd.vram_used_aligned[xcp_id] += adev->gmc.is_app_apu ?
230 ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);
232 kfd_mem_limit.system_mem_used += system_mem_needed;
233 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
236 spin_unlock(&kfd_mem_limit.mem_limit_lock);
240 void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
241 uint64_t size, u32 alloc_flag, int8_t xcp_id)
243 spin_lock(&kfd_mem_limit.mem_limit_lock);
245 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
246 kfd_mem_limit.system_mem_used -= size;
247 kfd_mem_limit.ttm_mem_used -= size;
248 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
250 "adev reference can't be null when alloc mem flags vram is set");
251 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
255 adev->kfd.vram_used[xcp_id] -= size;
256 if (adev->gmc.is_app_apu) {
257 adev->kfd.vram_used_aligned[xcp_id] -= size;
258 kfd_mem_limit.system_mem_used -= size;
259 kfd_mem_limit.ttm_mem_used -= size;
261 adev->kfd.vram_used_aligned[xcp_id] -=
262 ALIGN(size, VRAM_AVAILABLITY_ALIGN);
265 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
266 kfd_mem_limit.system_mem_used -= size;
267 } else if (!(alloc_flag &
268 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
269 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
270 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
273 WARN_ONCE(adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] < 0,
274 "KFD VRAM memory accounting unbalanced for xcp: %d", xcp_id);
275 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
276 "KFD TTM memory accounting unbalanced");
277 WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
278 "KFD system memory accounting unbalanced");
281 spin_unlock(&kfd_mem_limit.mem_limit_lock);
284 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
286 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
287 u32 alloc_flags = bo->kfd_bo->alloc_flags;
288 u64 size = amdgpu_bo_size(bo);
290 amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags,
297 * create_dmamap_sg_bo() - Creates a amdgpu_bo object to reflect information
298 * about USERPTR or DOOREBELL or MMIO BO.
300 * @adev: Device for which dmamap BO is being created
301 * @mem: BO of peer device that is being DMA mapped. Provides parameters
302 * in building the dmamap BO
303 * @bo_out: Output parameter updated with handle of dmamap BO
306 create_dmamap_sg_bo(struct amdgpu_device *adev,
307 struct kgd_mem *mem, struct amdgpu_bo **bo_out)
309 struct drm_gem_object *gem_obj;
313 ret = amdgpu_bo_reserve(mem->bo, false);
317 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)
318 flags |= mem->bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
319 AMDGPU_GEM_CREATE_UNCACHED);
321 ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1,
322 AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags,
323 ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0);
325 amdgpu_bo_unreserve(mem->bo);
328 pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret);
332 *bo_out = gem_to_amdgpu_bo(gem_obj);
333 (*bo_out)->parent = amdgpu_bo_ref(mem->bo);
337 /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
338 * reservation object.
340 * @bo: [IN] Remove eviction fence(s) from this BO
341 * @ef: [IN] This eviction fence is removed if it
342 * is present in the shared list.
344 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
346 static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
347 struct amdgpu_amdkfd_fence *ef)
349 struct dma_fence *replacement;
354 /* TODO: Instead of block before we should use the fence of the page
355 * table update and TLB flush here directly.
357 replacement = dma_fence_get_stub();
358 dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
359 replacement, DMA_RESV_USAGE_BOOKKEEP);
360 dma_fence_put(replacement);
364 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
366 struct amdgpu_bo *root = bo;
367 struct amdgpu_vm_bo_base *vm_bo;
368 struct amdgpu_vm *vm;
369 struct amdkfd_process_info *info;
370 struct amdgpu_amdkfd_fence *ef;
373 /* we can always get vm_bo from root PD bo.*/
385 info = vm->process_info;
386 if (!info || !info->eviction_fence)
389 ef = container_of(dma_fence_get(&info->eviction_fence->base),
390 struct amdgpu_amdkfd_fence, base);
392 BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
393 ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
394 dma_resv_unlock(bo->tbo.base.resv);
396 dma_fence_put(&ef->base);
400 static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
403 struct ttm_operation_ctx ctx = { false, false };
406 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
407 "Called with userptr BO"))
410 amdgpu_bo_placement_from_domain(bo, domain);
412 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
416 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
422 static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
424 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
427 /* vm_validate_pt_pd_bos - Validate page table and directory BOs
429 * Page directories are not updated here because huge page handling
430 * during page table updates can invalidate page directory entries
431 * again. Page directories are only updated after updating page
434 static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
436 struct amdgpu_bo *pd = vm->root.bo;
437 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
440 ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL);
442 pr_err("failed to validate PT BOs\n");
446 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
451 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
453 struct amdgpu_bo *pd = vm->root.bo;
454 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
457 ret = amdgpu_vm_update_pdes(adev, vm, false);
461 return amdgpu_sync_fence(sync, vm->last_update);
464 static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
466 uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE |
467 AMDGPU_VM_MTYPE_DEFAULT;
469 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
470 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
471 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
472 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
474 return amdgpu_gem_va_map_flags(adev, mapping_flags);
478 * create_sg_table() - Create an sg_table for a contiguous DMA addr range
479 * @addr: The starting address to point to
480 * @size: Size of memory area in bytes being pointed to
482 * Allocates an instance of sg_table and initializes it to point to memory
483 * area specified by input parameters. The address used to build is assumed
484 * to be DMA mapped, if needed.
486 * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table
487 * because they are physically contiguous.
489 * Return: Initialized instance of SG Table or NULL
491 static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)
493 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
497 if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
501 sg_dma_address(sg->sgl) = addr;
502 sg->sgl->length = size;
503 #ifdef CONFIG_NEED_SG_DMA_LENGTH
504 sg->sgl->dma_length = size;
510 kfd_mem_dmamap_userptr(struct kgd_mem *mem,
511 struct kfd_mem_attachment *attachment)
513 enum dma_data_direction direction =
514 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
515 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
516 struct ttm_operation_ctx ctx = {.interruptible = true};
517 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
518 struct amdgpu_device *adev = attachment->adev;
519 struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
520 struct ttm_tt *ttm = bo->tbo.ttm;
523 if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
526 ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
527 if (unlikely(!ttm->sg))
530 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */
531 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
533 (u64)ttm->num_pages << PAGE_SHIFT,
538 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
542 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
543 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
550 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
552 pr_err("DMA map userptr failed: %d\n", ret);
553 sg_free_table(ttm->sg);
561 kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
563 struct ttm_operation_ctx ctx = {.interruptible = true};
564 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
567 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
568 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
572 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
573 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
577 * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO
578 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
579 * @attachment: Virtual address attachment of the BO on accessing device
581 * An access request from the device that owns DOORBELL does not require DMA mapping.
582 * This is because the request doesn't go through PCIe root complex i.e. it instead
583 * loops back. The need to DMA map arises only when accessing peer device's DOORBELL
585 * In contrast, all access requests for MMIO need to be DMA mapped without regard to
586 * device ownership. This is because access requests for MMIO go through PCIe root
589 * This is accomplished in two steps:
590 * - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used
591 * in updating requesting device's page table
592 * - Signal TTM to mark memory pointed to by requesting device's BO as GPU
593 * accessible. This allows an update of requesting device's page table
594 * with entries associated with DOOREBELL or MMIO memory
596 * This method is invoked in the following contexts:
597 * - Mapping of DOORBELL or MMIO BO of same or peer device
598 * - Validating an evicted DOOREBELL or MMIO BO on device seeking access
600 * Return: ZERO if successful, NON-ZERO otherwise
603 kfd_mem_dmamap_sg_bo(struct kgd_mem *mem,
604 struct kfd_mem_attachment *attachment)
606 struct ttm_operation_ctx ctx = {.interruptible = true};
607 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
608 struct amdgpu_device *adev = attachment->adev;
609 struct ttm_tt *ttm = bo->tbo.ttm;
610 enum dma_data_direction dir;
615 /* Expect SG Table of dmapmap BO to be NULL */
616 mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
617 if (unlikely(ttm->sg)) {
618 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
622 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
623 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
624 dma_addr = mem->bo->tbo.sg->sgl->dma_address;
625 pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
626 pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
627 dma_addr = dma_map_resource(adev->dev, dma_addr,
628 mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
629 ret = dma_mapping_error(adev->dev, dma_addr);
632 pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
634 ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length);
635 if (unlikely(!ttm->sg)) {
640 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
641 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
648 sg_free_table(ttm->sg);
652 dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length,
653 dir, DMA_ATTR_SKIP_CPU_SYNC);
658 kfd_mem_dmamap_attachment(struct kgd_mem *mem,
659 struct kfd_mem_attachment *attachment)
661 switch (attachment->type) {
662 case KFD_MEM_ATT_SHARED:
664 case KFD_MEM_ATT_USERPTR:
665 return kfd_mem_dmamap_userptr(mem, attachment);
666 case KFD_MEM_ATT_DMABUF:
667 return kfd_mem_dmamap_dmabuf(attachment);
669 return kfd_mem_dmamap_sg_bo(mem, attachment);
677 kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
678 struct kfd_mem_attachment *attachment)
680 enum dma_data_direction direction =
681 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
682 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
683 struct ttm_operation_ctx ctx = {.interruptible = false};
684 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
685 struct amdgpu_device *adev = attachment->adev;
686 struct ttm_tt *ttm = bo->tbo.ttm;
688 if (unlikely(!ttm->sg))
691 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
692 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
694 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
695 sg_free_table(ttm->sg);
701 kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
703 /* This is a no-op. We don't want to trigger eviction fences when
704 * unmapping DMABufs. Therefore the invalidation (moving to system
705 * domain) is done in kfd_mem_dmamap_dmabuf.
710 * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO
711 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
712 * @attachment: Virtual address attachment of the BO on accessing device
714 * The method performs following steps:
715 * - Signal TTM to mark memory pointed to by BO as GPU inaccessible
716 * - Free SG Table that is used to encapsulate DMA mapped memory of
717 * peer device's DOORBELL or MMIO memory
719 * This method is invoked in the following contexts:
720 * UNMapping of DOORBELL or MMIO BO on a device having access to its memory
721 * Eviction of DOOREBELL or MMIO BO on device having access to its memory
726 kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
727 struct kfd_mem_attachment *attachment)
729 struct ttm_operation_ctx ctx = {.interruptible = true};
730 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
731 struct amdgpu_device *adev = attachment->adev;
732 struct ttm_tt *ttm = bo->tbo.ttm;
733 enum dma_data_direction dir;
735 if (unlikely(!ttm->sg)) {
736 pr_err("SG Table of BO is UNEXPECTEDLY NULL");
740 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
741 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
743 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
744 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
745 dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address,
746 ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
747 sg_free_table(ttm->sg);
754 kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
755 struct kfd_mem_attachment *attachment)
757 switch (attachment->type) {
758 case KFD_MEM_ATT_SHARED:
760 case KFD_MEM_ATT_USERPTR:
761 kfd_mem_dmaunmap_userptr(mem, attachment);
763 case KFD_MEM_ATT_DMABUF:
764 kfd_mem_dmaunmap_dmabuf(attachment);
767 kfd_mem_dmaunmap_sg_bo(mem, attachment);
774 static int kfd_mem_export_dmabuf(struct kgd_mem *mem)
777 struct dma_buf *ret = amdgpu_gem_prime_export(
779 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
790 kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
791 struct amdgpu_bo **bo)
793 struct drm_gem_object *gobj;
796 ret = kfd_mem_export_dmabuf(mem);
800 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
802 return PTR_ERR(gobj);
804 *bo = gem_to_amdgpu_bo(gobj);
805 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
810 /* kfd_mem_attach - Add a BO to a VM
812 * Everything that needs to bo done only once when a BO is first added
813 * to a VM. It can later be mapped and unmapped many times without
814 * repeating these steps.
816 * 0. Create BO for DMA mapping, if needed
817 * 1. Allocate and initialize BO VA entry data structure
818 * 2. Add BO to the VM
819 * 3. Determine ASIC-specific PTE flags
820 * 4. Alloc page tables and directories if needed
821 * 4a. Validate new page tables and directories
823 static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
824 struct amdgpu_vm *vm, bool is_aql)
826 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
827 unsigned long bo_size = mem->bo->tbo.base.size;
828 uint64_t va = mem->va;
829 struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
830 struct amdgpu_bo *bo[2] = {NULL, NULL};
831 bool same_hive = false;
835 pr_err("Invalid VA when adding BO to VM\n");
839 /* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices
841 * The access path of MMIO and DOORBELL BOs of is always over PCIe.
842 * In contrast the access path of VRAM BOs depens upon the type of
843 * link that connects the peer device. Access over PCIe is allowed
844 * if peer device has large BAR. In contrast, access over xGMI is
845 * allowed for both small and large BAR configurations of peer device
847 if ((adev != bo_adev && !adev->gmc.is_app_apu) &&
848 ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
849 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
850 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
851 if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM)
852 same_hive = amdgpu_xgmi_same_hive(adev, bo_adev);
853 if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev))
857 for (i = 0; i <= is_aql; i++) {
858 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
859 if (unlikely(!attachment[i])) {
864 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
867 if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
868 (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) ||
870 /* Mappings on the local GPU, or VRAM mappings in the
871 * local hive, or userptr mapping can reuse dma map
872 * address space share the original BO
874 attachment[i]->type = KFD_MEM_ATT_SHARED;
876 drm_gem_object_get(&bo[i]->tbo.base);
878 /* Multiple mappings on the same GPU share the BO */
879 attachment[i]->type = KFD_MEM_ATT_SHARED;
881 drm_gem_object_get(&bo[i]->tbo.base);
882 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
883 /* Create an SG BO to DMA-map userptrs on other GPUs */
884 attachment[i]->type = KFD_MEM_ATT_USERPTR;
885 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
888 /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */
889 } else if (mem->bo->tbo.type == ttm_bo_type_sg) {
890 WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL ||
891 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP),
892 "Handing invalid SG BO in ATTACH request");
893 attachment[i]->type = KFD_MEM_ATT_SG;
894 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
897 /* Enable acces to GTT and VRAM BOs of peer devices */
898 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT ||
899 mem->domain == AMDGPU_GEM_DOMAIN_VRAM) {
900 attachment[i]->type = KFD_MEM_ATT_DMABUF;
901 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
904 pr_debug("Employ DMABUF mechanism to enable peer GPU access\n");
906 WARN_ONCE(true, "Handling invalid ATTACH request");
911 /* Add BO to VM internal data structures */
912 ret = amdgpu_bo_reserve(bo[i], false);
914 pr_debug("Unable to reserve BO during memory attach");
917 attachment[i]->bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
918 amdgpu_bo_unreserve(bo[i]);
919 if (unlikely(!attachment[i]->bo_va)) {
921 pr_err("Failed to add BO object to VM. ret == %d\n",
925 attachment[i]->va = va;
926 attachment[i]->pte_flags = get_pte_flags(adev, mem);
927 attachment[i]->adev = adev;
928 list_add(&attachment[i]->list, &mem->attachments);
936 for (; i >= 0; i--) {
939 if (attachment[i]->bo_va) {
940 amdgpu_bo_reserve(bo[i], true);
941 amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
942 amdgpu_bo_unreserve(bo[i]);
943 list_del(&attachment[i]->list);
946 drm_gem_object_put(&bo[i]->tbo.base);
947 kfree(attachment[i]);
952 static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
954 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
956 pr_debug("\t remove VA 0x%llx in entry %p\n",
957 attachment->va, attachment);
958 amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
959 drm_gem_object_put(&bo->tbo.base);
960 list_del(&attachment->list);
964 static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
965 struct amdkfd_process_info *process_info,
968 mutex_lock(&process_info->lock);
970 list_add_tail(&mem->validate_list,
971 &process_info->userptr_valid_list);
973 list_add_tail(&mem->validate_list, &process_info->kfd_bo_list);
974 mutex_unlock(&process_info->lock);
977 static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
978 struct amdkfd_process_info *process_info)
980 mutex_lock(&process_info->lock);
981 list_del(&mem->validate_list);
982 mutex_unlock(&process_info->lock);
985 /* Initializes user pages. It registers the MMU notifier and validates
986 * the userptr BO in the GTT domain.
988 * The BO must already be on the userptr_valid_list. Otherwise an
989 * eviction and restore may happen that leaves the new BO unmapped
990 * with the user mode queues running.
992 * Takes the process_info->lock to protect against concurrent restore
995 * Returns 0 for success, negative errno for errors.
997 static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
1000 struct amdkfd_process_info *process_info = mem->process_info;
1001 struct amdgpu_bo *bo = mem->bo;
1002 struct ttm_operation_ctx ctx = { true, false };
1003 struct hmm_range *range;
1006 mutex_lock(&process_info->lock);
1008 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
1010 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
1014 ret = amdgpu_hmm_register(bo, user_addr);
1016 pr_err("%s: Failed to register MMU notifier: %d\n",
1023 * During a CRIU restore operation, the userptr buffer objects
1024 * will be validated in the restore_userptr_work worker at a
1025 * later stage when it is scheduled by another ioctl called by
1026 * CRIU master process for the target pid for restore.
1028 mutex_lock(&process_info->notifier_lock);
1030 mutex_unlock(&process_info->notifier_lock);
1031 mutex_unlock(&process_info->lock);
1035 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range);
1037 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
1038 goto unregister_out;
1041 ret = amdgpu_bo_reserve(bo, true);
1043 pr_err("%s: Failed to reserve BO\n", __func__);
1046 amdgpu_bo_placement_from_domain(bo, mem->domain);
1047 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1049 pr_err("%s: failed to validate BO\n", __func__);
1050 amdgpu_bo_unreserve(bo);
1053 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
1056 amdgpu_hmm_unregister(bo);
1058 mutex_unlock(&process_info->lock);
1062 /* Reserving a BO and its page table BOs must happen atomically to
1063 * avoid deadlocks. Some operations update multiple VMs at once. Track
1064 * all the reservation info in a context structure. Optionally a sync
1065 * object can track VM updates.
1067 struct bo_vm_reservation_context {
1068 /* DRM execution context for the reservation */
1069 struct drm_exec exec;
1070 /* Number of VMs reserved */
1072 /* Pointer to sync object */
1073 struct amdgpu_sync *sync;
1077 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */
1078 BO_VM_MAPPED, /* Match VMs where a BO is mapped */
1079 BO_VM_ALL, /* Match all VMs a BO was added to */
1083 * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
1084 * @mem: KFD BO structure.
1085 * @vm: the VM to reserve.
1086 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1088 static int reserve_bo_and_vm(struct kgd_mem *mem,
1089 struct amdgpu_vm *vm,
1090 struct bo_vm_reservation_context *ctx)
1092 struct amdgpu_bo *bo = mem->bo;
1098 ctx->sync = &mem->sync;
1099 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT);
1100 drm_exec_until_all_locked(&ctx->exec) {
1101 ret = amdgpu_vm_lock_pd(vm, &ctx->exec, 2);
1102 drm_exec_retry_on_contention(&ctx->exec);
1106 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1107 drm_exec_retry_on_contention(&ctx->exec);
1114 pr_err("Failed to reserve buffers in ttm.\n");
1115 drm_exec_fini(&ctx->exec);
1120 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
1121 * @mem: KFD BO structure.
1122 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
1123 * is used. Otherwise, a single VM associated with the BO.
1124 * @map_type: the mapping status that will be used to filter the VMs.
1125 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1127 * Returns 0 for success, negative for failure.
1129 static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
1130 struct amdgpu_vm *vm, enum bo_vm_match map_type,
1131 struct bo_vm_reservation_context *ctx)
1133 struct kfd_mem_attachment *entry;
1134 struct amdgpu_bo *bo = mem->bo;
1137 ctx->sync = &mem->sync;
1138 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT);
1139 drm_exec_until_all_locked(&ctx->exec) {
1141 list_for_each_entry(entry, &mem->attachments, list) {
1142 if ((vm && vm != entry->bo_va->base.vm) ||
1143 (entry->is_mapped != map_type
1144 && map_type != BO_VM_ALL))
1147 ret = amdgpu_vm_lock_pd(entry->bo_va->base.vm,
1149 drm_exec_retry_on_contention(&ctx->exec);
1155 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1156 drm_exec_retry_on_contention(&ctx->exec);
1163 pr_err("Failed to reserve buffers in ttm.\n");
1164 drm_exec_fini(&ctx->exec);
1169 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1170 * @ctx: Reservation context to unreserve
1171 * @wait: Optionally wait for a sync object representing pending VM updates
1172 * @intr: Whether the wait is interruptible
1174 * Also frees any resources allocated in
1175 * reserve_bo_and_(cond_)vm(s). Returns the status from
1178 static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1179 bool wait, bool intr)
1184 ret = amdgpu_sync_wait(ctx->sync, intr);
1186 drm_exec_fini(&ctx->exec);
1191 static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
1192 struct kfd_mem_attachment *entry,
1193 struct amdgpu_sync *sync)
1195 struct amdgpu_bo_va *bo_va = entry->bo_va;
1196 struct amdgpu_device *adev = entry->adev;
1197 struct amdgpu_vm *vm = bo_va->base.vm;
1199 amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1201 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1203 amdgpu_sync_fence(sync, bo_va->last_pt_update);
1205 kfd_mem_dmaunmap_attachment(mem, entry);
1208 static int update_gpuvm_pte(struct kgd_mem *mem,
1209 struct kfd_mem_attachment *entry,
1210 struct amdgpu_sync *sync)
1212 struct amdgpu_bo_va *bo_va = entry->bo_va;
1213 struct amdgpu_device *adev = entry->adev;
1216 ret = kfd_mem_dmamap_attachment(mem, entry);
1220 /* Update the page tables */
1221 ret = amdgpu_vm_bo_update(adev, bo_va, false);
1223 pr_err("amdgpu_vm_bo_update failed\n");
1227 return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1230 static int map_bo_to_gpuvm(struct kgd_mem *mem,
1231 struct kfd_mem_attachment *entry,
1232 struct amdgpu_sync *sync,
1237 /* Set virtual address for the allocation */
1238 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1239 amdgpu_bo_size(entry->bo_va->base.bo),
1242 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1250 ret = update_gpuvm_pte(mem, entry, sync);
1252 pr_err("update_gpuvm_pte() failed\n");
1253 goto update_gpuvm_pte_failed;
1258 update_gpuvm_pte_failed:
1259 unmap_bo_from_gpuvm(mem, entry, sync);
1263 static int process_validate_vms(struct amdkfd_process_info *process_info)
1265 struct amdgpu_vm *peer_vm;
1268 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1270 ret = vm_validate_pt_pd_bos(peer_vm);
1278 static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1279 struct amdgpu_sync *sync)
1281 struct amdgpu_vm *peer_vm;
1284 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1286 struct amdgpu_bo *pd = peer_vm->root.bo;
1288 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1289 AMDGPU_SYNC_NE_OWNER,
1290 AMDGPU_FENCE_OWNER_KFD);
1298 static int process_update_pds(struct amdkfd_process_info *process_info,
1299 struct amdgpu_sync *sync)
1301 struct amdgpu_vm *peer_vm;
1304 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1306 ret = vm_update_pds(peer_vm, sync);
1314 static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1315 struct dma_fence **ef)
1317 struct amdkfd_process_info *info = NULL;
1320 if (!*process_info) {
1321 info = kzalloc(sizeof(*info), GFP_KERNEL);
1325 mutex_init(&info->lock);
1326 mutex_init(&info->notifier_lock);
1327 INIT_LIST_HEAD(&info->vm_list_head);
1328 INIT_LIST_HEAD(&info->kfd_bo_list);
1329 INIT_LIST_HEAD(&info->userptr_valid_list);
1330 INIT_LIST_HEAD(&info->userptr_inval_list);
1332 info->eviction_fence =
1333 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1336 if (!info->eviction_fence) {
1337 pr_err("Failed to create eviction fence\n");
1339 goto create_evict_fence_fail;
1342 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1343 INIT_DELAYED_WORK(&info->restore_userptr_work,
1344 amdgpu_amdkfd_restore_userptr_worker);
1346 *process_info = info;
1347 *ef = dma_fence_get(&info->eviction_fence->base);
1350 vm->process_info = *process_info;
1352 /* Validate page directory and attach eviction fence */
1353 ret = amdgpu_bo_reserve(vm->root.bo, true);
1355 goto reserve_pd_fail;
1356 ret = vm_validate_pt_pd_bos(vm);
1358 pr_err("validate_pt_pd_bos() failed\n");
1359 goto validate_pd_fail;
1361 ret = amdgpu_bo_sync_wait(vm->root.bo,
1362 AMDGPU_FENCE_OWNER_KFD, false);
1365 ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
1367 goto reserve_shared_fail;
1368 dma_resv_add_fence(vm->root.bo->tbo.base.resv,
1369 &vm->process_info->eviction_fence->base,
1370 DMA_RESV_USAGE_BOOKKEEP);
1371 amdgpu_bo_unreserve(vm->root.bo);
1373 /* Update process info */
1374 mutex_lock(&vm->process_info->lock);
1375 list_add_tail(&vm->vm_list_node,
1376 &(vm->process_info->vm_list_head));
1377 vm->process_info->n_vms++;
1378 mutex_unlock(&vm->process_info->lock);
1382 reserve_shared_fail:
1385 amdgpu_bo_unreserve(vm->root.bo);
1387 vm->process_info = NULL;
1389 /* Two fence references: one in info and one in *ef */
1390 dma_fence_put(&info->eviction_fence->base);
1393 *process_info = NULL;
1395 create_evict_fence_fail:
1396 mutex_destroy(&info->lock);
1397 mutex_destroy(&info->notifier_lock);
1404 * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria
1405 * @bo: Handle of buffer object being pinned
1406 * @domain: Domain into which BO should be pinned
1408 * - USERPTR BOs are UNPINNABLE and will return error
1409 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1410 * PIN count incremented. It is valid to PIN a BO multiple times
1412 * Return: ZERO if successful in pinning, Non-Zero in case of error.
1414 static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)
1418 ret = amdgpu_bo_reserve(bo, false);
1422 ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1424 pr_err("Error in Pinning BO to domain: %d\n", domain);
1426 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
1427 amdgpu_bo_unreserve(bo);
1433 * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria
1434 * @bo: Handle of buffer object being unpinned
1436 * - Is a illegal request for USERPTR BOs and is ignored
1437 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1438 * PIN count decremented. Calls to UNPIN must balance calls to PIN
1440 static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
1444 ret = amdgpu_bo_reserve(bo, false);
1448 amdgpu_bo_unpin(bo);
1449 amdgpu_bo_unreserve(bo);
1452 int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
1453 struct amdgpu_vm *avm, u32 pasid)
1458 /* Free the original amdgpu allocated pasid,
1459 * will be replaced with kfd allocated pasid.
1462 amdgpu_pasid_free(avm->pasid);
1463 amdgpu_vm_set_pasid(adev, avm, 0);
1466 ret = amdgpu_vm_set_pasid(adev, avm, pasid);
1473 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
1474 struct amdgpu_vm *avm,
1475 void **process_info,
1476 struct dma_fence **ef)
1480 /* Already a compute VM? */
1481 if (avm->process_info)
1484 /* Convert VM into a compute VM */
1485 ret = amdgpu_vm_make_compute(adev, avm);
1489 /* Initialize KFD part of the VM and process info */
1490 ret = init_kfd_vm(avm, process_info, ef);
1494 amdgpu_vm_set_task_info(avm);
1499 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1500 struct amdgpu_vm *vm)
1502 struct amdkfd_process_info *process_info = vm->process_info;
1507 /* Update process info */
1508 mutex_lock(&process_info->lock);
1509 process_info->n_vms--;
1510 list_del(&vm->vm_list_node);
1511 mutex_unlock(&process_info->lock);
1513 vm->process_info = NULL;
1515 /* Release per-process resources when last compute VM is destroyed */
1516 if (!process_info->n_vms) {
1517 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1518 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1519 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1521 dma_fence_put(&process_info->eviction_fence->base);
1522 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1523 put_pid(process_info->pid);
1524 mutex_destroy(&process_info->lock);
1525 mutex_destroy(&process_info->notifier_lock);
1526 kfree(process_info);
1530 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
1533 struct amdgpu_vm *avm;
1535 if (WARN_ON(!adev || !drm_priv))
1538 avm = drm_priv_to_vm(drm_priv);
1540 pr_debug("Releasing process vm %p\n", avm);
1542 /* The original pasid of amdgpu vm has already been
1543 * released during making a amdgpu vm to a compute vm
1544 * The current pasid is managed by kfd and will be
1545 * released on kfd process destroy. Set amdgpu pasid
1546 * to 0 to avoid duplicate release.
1548 amdgpu_vm_release_compute(adev, avm);
1551 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1553 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1554 struct amdgpu_bo *pd = avm->root.bo;
1555 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1557 if (adev->asic_type < CHIP_VEGA10)
1558 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1559 return avm->pd_phys_addr;
1562 void amdgpu_amdkfd_block_mmu_notifications(void *p)
1564 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1566 mutex_lock(&pinfo->lock);
1567 WRITE_ONCE(pinfo->block_mmu_notifications, true);
1568 mutex_unlock(&pinfo->lock);
1571 int amdgpu_amdkfd_criu_resume(void *p)
1574 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1576 mutex_lock(&pinfo->lock);
1577 pr_debug("scheduling work\n");
1578 mutex_lock(&pinfo->notifier_lock);
1579 pinfo->evicted_bos++;
1580 mutex_unlock(&pinfo->notifier_lock);
1581 if (!READ_ONCE(pinfo->block_mmu_notifications)) {
1585 WRITE_ONCE(pinfo->block_mmu_notifications, false);
1586 schedule_delayed_work(&pinfo->restore_userptr_work, 0);
1589 mutex_unlock(&pinfo->lock);
1593 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
1596 uint64_t reserved_for_pt =
1597 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
1599 uint64_t vram_available, system_mem_available, ttm_mem_available;
1601 spin_lock(&kfd_mem_limit.mem_limit_lock);
1602 vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)
1603 - adev->kfd.vram_used_aligned[xcp_id]
1604 - atomic64_read(&adev->vram_pin_size)
1607 if (adev->gmc.is_app_apu) {
1608 system_mem_available = no_system_mem_limit ?
1609 kfd_mem_limit.max_system_mem_limit :
1610 kfd_mem_limit.max_system_mem_limit -
1611 kfd_mem_limit.system_mem_used;
1613 ttm_mem_available = kfd_mem_limit.max_ttm_mem_limit -
1614 kfd_mem_limit.ttm_mem_used;
1616 available = min3(system_mem_available, ttm_mem_available,
1618 available = ALIGN_DOWN(available, PAGE_SIZE);
1620 available = ALIGN_DOWN(vram_available, VRAM_AVAILABLITY_ALIGN);
1623 spin_unlock(&kfd_mem_limit.mem_limit_lock);
1631 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1632 struct amdgpu_device *adev, uint64_t va, uint64_t size,
1633 void *drm_priv, struct kgd_mem **mem,
1634 uint64_t *offset, uint32_t flags, bool criu_resume)
1636 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1637 struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm);
1638 enum ttm_bo_type bo_type = ttm_bo_type_device;
1639 struct sg_table *sg = NULL;
1640 uint64_t user_addr = 0;
1641 struct amdgpu_bo *bo;
1642 struct drm_gem_object *gobj = NULL;
1643 u32 domain, alloc_domain;
1644 uint64_t aligned_size;
1650 * Check on which domain to allocate BO
1652 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1653 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1655 if (adev->gmc.is_app_apu) {
1656 domain = AMDGPU_GEM_DOMAIN_GTT;
1657 alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1660 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1661 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1662 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1664 xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
1666 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1667 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1670 domain = AMDGPU_GEM_DOMAIN_GTT;
1671 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1672 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1674 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1675 if (!offset || !*offset)
1677 user_addr = untagged_addr(*offset);
1678 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1679 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1680 bo_type = ttm_bo_type_sg;
1681 if (size > UINT_MAX)
1683 sg = create_sg_table(*offset, size);
1691 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
1692 alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
1693 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
1694 alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
1696 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1701 INIT_LIST_HEAD(&(*mem)->attachments);
1702 mutex_init(&(*mem)->lock);
1703 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1705 /* Workaround for AQL queue wraparound bug. Map the same
1706 * memory twice. That means we only actually allocate half
1709 if ((*mem)->aql_queue)
1711 aligned_size = PAGE_ALIGN(size);
1713 (*mem)->alloc_flags = flags;
1715 amdgpu_sync_create(&(*mem)->sync);
1717 ret = amdgpu_amdkfd_reserve_mem_limit(adev, aligned_size, flags,
1720 pr_debug("Insufficient memory\n");
1721 goto err_reserve_limit;
1724 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s xcp_id %d\n",
1725 va, (*mem)->aql_queue ? size << 1 : size,
1726 domain_string(alloc_domain), xcp_id);
1728 ret = amdgpu_gem_object_create(adev, aligned_size, 1, alloc_domain, alloc_flags,
1729 bo_type, NULL, &gobj, xcp_id + 1);
1731 pr_debug("Failed to create BO on domain %s. ret %d\n",
1732 domain_string(alloc_domain), ret);
1735 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1737 pr_debug("Failed to allow vma node access. ret %d\n", ret);
1738 goto err_node_allow;
1740 bo = gem_to_amdgpu_bo(gobj);
1741 if (bo_type == ttm_bo_type_sg) {
1743 bo->tbo.ttm->sg = sg;
1748 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1751 (*mem)->domain = domain;
1752 (*mem)->mapped_to_gpu_memory = 0;
1753 (*mem)->process_info = avm->process_info;
1755 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1758 pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
1759 ret = init_user_pages(*mem, user_addr, criu_resume);
1761 goto allocate_init_user_pages_failed;
1762 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1763 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1764 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT);
1766 pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n");
1769 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
1770 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
1774 *offset = amdgpu_bo_mmap_offset(bo);
1778 allocate_init_user_pages_failed:
1780 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1781 drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1783 /* Don't unreserve system mem limit twice */
1784 goto err_reserve_limit;
1786 amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id);
1788 mutex_destroy(&(*mem)->lock);
1790 drm_gem_object_put(gobj);
1801 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1802 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
1805 struct amdkfd_process_info *process_info = mem->process_info;
1806 unsigned long bo_size = mem->bo->tbo.base.size;
1807 bool use_release_notifier = (mem->bo->kfd_bo == mem);
1808 struct kfd_mem_attachment *entry, *tmp;
1809 struct bo_vm_reservation_context ctx;
1810 unsigned int mapped_to_gpu_memory;
1812 bool is_imported = false;
1814 mutex_lock(&mem->lock);
1816 /* Unpin MMIO/DOORBELL BO's that were pinned during allocation */
1817 if (mem->alloc_flags &
1818 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1819 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1820 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo);
1823 mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1824 is_imported = mem->is_imported;
1825 mutex_unlock(&mem->lock);
1826 /* lock is not needed after this, since mem is unused and will
1830 if (mapped_to_gpu_memory > 0) {
1831 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1836 /* Make sure restore workers don't access the BO any more */
1837 mutex_lock(&process_info->lock);
1838 list_del(&mem->validate_list);
1839 mutex_unlock(&process_info->lock);
1841 /* Cleanup user pages and MMU notifiers */
1842 if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
1843 amdgpu_hmm_unregister(mem->bo);
1844 mutex_lock(&process_info->notifier_lock);
1845 amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range);
1846 mutex_unlock(&process_info->notifier_lock);
1849 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1853 /* The eviction fence should be removed by the last unmap.
1854 * TODO: Log an error condition if the bo still has the eviction fence
1857 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1858 process_info->eviction_fence);
1859 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1860 mem->va + bo_size * (1 + mem->aql_queue));
1862 /* Remove from VM internal data structures */
1863 list_for_each_entry_safe(entry, tmp, &mem->attachments, list)
1864 kfd_mem_detach(entry);
1866 ret = unreserve_bo_and_vms(&ctx, false, false);
1868 /* Free the sync object */
1869 amdgpu_sync_free(&mem->sync);
1871 /* If the SG is not NULL, it's one we created for a doorbell or mmio
1872 * remap BO. We need to free it.
1874 if (mem->bo->tbo.sg) {
1875 sg_free_table(mem->bo->tbo.sg);
1876 kfree(mem->bo->tbo.sg);
1879 /* Update the size of the BO being freed if it was allocated from
1880 * VRAM and is not imported. For APP APU VRAM allocations are done
1885 (mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM ||
1886 (adev->gmc.is_app_apu &&
1887 mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT)))
1894 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1896 dma_buf_put(mem->dmabuf);
1897 mutex_destroy(&mem->lock);
1899 /* If this releases the last reference, it will end up calling
1900 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why
1901 * this needs to be the last call here.
1903 drm_gem_object_put(&mem->bo->tbo.base);
1906 * For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(),
1907 * explicitly free it here.
1909 if (!use_release_notifier)
1915 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1916 struct amdgpu_device *adev, struct kgd_mem *mem,
1919 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1921 struct amdgpu_bo *bo;
1923 struct kfd_mem_attachment *entry;
1924 struct bo_vm_reservation_context ctx;
1925 unsigned long bo_size;
1926 bool is_invalid_userptr = false;
1930 pr_err("Invalid BO when mapping memory to GPU\n");
1934 /* Make sure restore is not running concurrently. Since we
1935 * don't map invalid userptr BOs, we rely on the next restore
1936 * worker to do the mapping
1938 mutex_lock(&mem->process_info->lock);
1940 /* Lock notifier lock. If we find an invalid userptr BO, we can be
1941 * sure that the MMU notifier is no longer running
1942 * concurrently and the queues are actually stopped
1944 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1945 mutex_lock(&mem->process_info->notifier_lock);
1946 is_invalid_userptr = !!mem->invalid;
1947 mutex_unlock(&mem->process_info->notifier_lock);
1950 mutex_lock(&mem->lock);
1952 domain = mem->domain;
1953 bo_size = bo->tbo.base.size;
1955 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
1957 mem->va + bo_size * (1 + mem->aql_queue),
1958 avm, domain_string(domain));
1960 if (!kfd_mem_is_attached(avm, mem)) {
1961 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
1966 ret = reserve_bo_and_vm(mem, avm, &ctx);
1970 /* Userptr can be marked as "not invalid", but not actually be
1971 * validated yet (still in the system domain). In that case
1972 * the queues are still stopped and we can leave mapping for
1973 * the next restore worker
1975 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
1976 bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
1977 is_invalid_userptr = true;
1979 ret = vm_validate_pt_pd_bos(avm);
1983 if (mem->mapped_to_gpu_memory == 0 &&
1984 !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1985 /* Validate BO only once. The eviction fence gets added to BO
1986 * the first time it is mapped. Validate will wait for all
1987 * background evictions to complete.
1989 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
1991 pr_debug("Validate failed\n");
1996 list_for_each_entry(entry, &mem->attachments, list) {
1997 if (entry->bo_va->base.vm != avm || entry->is_mapped)
2000 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
2001 entry->va, entry->va + bo_size, entry);
2003 ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
2004 is_invalid_userptr);
2006 pr_err("Failed to map bo to gpuvm\n");
2010 ret = vm_update_pds(avm, ctx.sync);
2012 pr_err("Failed to update page directories\n");
2016 entry->is_mapped = true;
2017 mem->mapped_to_gpu_memory++;
2018 pr_debug("\t INC mapping count %d\n",
2019 mem->mapped_to_gpu_memory);
2022 if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count)
2023 dma_resv_add_fence(bo->tbo.base.resv,
2024 &avm->process_info->eviction_fence->base,
2025 DMA_RESV_USAGE_BOOKKEEP);
2026 ret = unreserve_bo_and_vms(&ctx, false, false);
2031 unreserve_bo_and_vms(&ctx, false, false);
2033 mutex_unlock(&mem->process_info->lock);
2034 mutex_unlock(&mem->lock);
2038 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
2039 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
2041 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2042 struct amdkfd_process_info *process_info = avm->process_info;
2043 unsigned long bo_size = mem->bo->tbo.base.size;
2044 struct kfd_mem_attachment *entry;
2045 struct bo_vm_reservation_context ctx;
2048 mutex_lock(&mem->lock);
2050 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
2053 /* If no VMs were reserved, it means the BO wasn't actually mapped */
2054 if (ctx.n_vms == 0) {
2059 ret = vm_validate_pt_pd_bos(avm);
2063 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
2065 mem->va + bo_size * (1 + mem->aql_queue),
2068 list_for_each_entry(entry, &mem->attachments, list) {
2069 if (entry->bo_va->base.vm != avm || !entry->is_mapped)
2072 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
2073 entry->va, entry->va + bo_size, entry);
2075 unmap_bo_from_gpuvm(mem, entry, ctx.sync);
2076 entry->is_mapped = false;
2078 mem->mapped_to_gpu_memory--;
2079 pr_debug("\t DEC mapping count %d\n",
2080 mem->mapped_to_gpu_memory);
2083 /* If BO is unmapped from all VMs, unfence it. It can be evicted if
2086 if (mem->mapped_to_gpu_memory == 0 &&
2087 !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) &&
2088 !mem->bo->tbo.pin_count)
2089 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
2090 process_info->eviction_fence);
2093 unreserve_bo_and_vms(&ctx, false, false);
2095 mutex_unlock(&mem->lock);
2099 int amdgpu_amdkfd_gpuvm_sync_memory(
2100 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
2102 struct amdgpu_sync sync;
2105 amdgpu_sync_create(&sync);
2107 mutex_lock(&mem->lock);
2108 amdgpu_sync_clone(&mem->sync, &sync);
2109 mutex_unlock(&mem->lock);
2111 ret = amdgpu_sync_wait(&sync, intr);
2112 amdgpu_sync_free(&sync);
2117 * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count
2118 * @adev: Device to which allocated BO belongs
2119 * @bo: Buffer object to be mapped
2121 * Before return, bo reference count is incremented. To release the reference and unpin/
2122 * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
2124 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo)
2128 ret = amdgpu_bo_reserve(bo, true);
2130 pr_err("Failed to reserve bo. ret %d\n", ret);
2131 goto err_reserve_bo_failed;
2134 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2136 pr_err("Failed to pin bo. ret %d\n", ret);
2137 goto err_pin_bo_failed;
2140 ret = amdgpu_ttm_alloc_gart(&bo->tbo);
2142 pr_err("Failed to bind bo to GART. ret %d\n", ret);
2143 goto err_map_bo_gart_failed;
2146 amdgpu_amdkfd_remove_eviction_fence(
2147 bo, bo->vm_bo->vm->process_info->eviction_fence);
2149 amdgpu_bo_unreserve(bo);
2151 bo = amdgpu_bo_ref(bo);
2155 err_map_bo_gart_failed:
2156 amdgpu_bo_unpin(bo);
2158 amdgpu_bo_unreserve(bo);
2159 err_reserve_bo_failed:
2164 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access
2166 * @mem: Buffer object to be mapped for CPU access
2167 * @kptr[out]: pointer in kernel CPU address space
2168 * @size[out]: size of the buffer
2170 * Pins the BO and maps it for kernel CPU access. The eviction fence is removed
2171 * from the BO, since pinned BOs cannot be evicted. The bo must remain on the
2172 * validate_list, so the GPU mapping can be restored after a page table was
2175 * Return: 0 on success, error code on failure
2177 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
2178 void **kptr, uint64_t *size)
2181 struct amdgpu_bo *bo = mem->bo;
2183 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2184 pr_err("userptr can't be mapped to kernel\n");
2188 mutex_lock(&mem->process_info->lock);
2190 ret = amdgpu_bo_reserve(bo, true);
2192 pr_err("Failed to reserve bo. ret %d\n", ret);
2193 goto bo_reserve_failed;
2196 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2198 pr_err("Failed to pin bo. ret %d\n", ret);
2202 ret = amdgpu_bo_kmap(bo, kptr);
2204 pr_err("Failed to map bo to kernel. ret %d\n", ret);
2208 amdgpu_amdkfd_remove_eviction_fence(
2209 bo, mem->process_info->eviction_fence);
2212 *size = amdgpu_bo_size(bo);
2214 amdgpu_bo_unreserve(bo);
2216 mutex_unlock(&mem->process_info->lock);
2220 amdgpu_bo_unpin(bo);
2222 amdgpu_bo_unreserve(bo);
2224 mutex_unlock(&mem->process_info->lock);
2229 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access
2231 * @mem: Buffer object to be unmapped for CPU access
2233 * Removes the kernel CPU mapping and unpins the BO. It does not restore the
2234 * eviction fence, so this function should only be used for cleanup before the
2237 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)
2239 struct amdgpu_bo *bo = mem->bo;
2241 amdgpu_bo_reserve(bo, true);
2242 amdgpu_bo_kunmap(bo);
2243 amdgpu_bo_unpin(bo);
2244 amdgpu_bo_unreserve(bo);
2247 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
2248 struct kfd_vm_fault_info *mem)
2250 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
2251 *mem = *adev->gmc.vm_fault_info;
2252 mb(); /* make sure read happened */
2253 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
2258 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
2259 struct dma_buf *dma_buf,
2260 uint64_t va, void *drm_priv,
2261 struct kgd_mem **mem, uint64_t *size,
2262 uint64_t *mmap_offset)
2264 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2265 struct drm_gem_object *obj;
2266 struct amdgpu_bo *bo;
2269 obj = amdgpu_gem_prime_import(adev_to_drm(adev), dma_buf);
2271 return PTR_ERR(obj);
2273 bo = gem_to_amdgpu_bo(obj);
2274 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
2275 AMDGPU_GEM_DOMAIN_GTT))) {
2276 /* Only VRAM and GTT BOs are supported */
2281 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2287 ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
2292 *size = amdgpu_bo_size(bo);
2295 *mmap_offset = amdgpu_bo_mmap_offset(bo);
2297 INIT_LIST_HEAD(&(*mem)->attachments);
2298 mutex_init(&(*mem)->lock);
2300 (*mem)->alloc_flags =
2301 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2302 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
2303 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
2304 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
2306 get_dma_buf(dma_buf);
2307 (*mem)->dmabuf = dma_buf;
2310 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !adev->gmc.is_app_apu ?
2311 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
2313 (*mem)->mapped_to_gpu_memory = 0;
2314 (*mem)->process_info = avm->process_info;
2315 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
2316 amdgpu_sync_create(&(*mem)->sync);
2317 (*mem)->is_imported = true;
2324 drm_gem_object_put(obj);
2328 int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
2329 struct dma_buf **dma_buf)
2333 mutex_lock(&mem->lock);
2334 ret = kfd_mem_export_dmabuf(mem);
2338 get_dma_buf(mem->dmabuf);
2339 *dma_buf = mem->dmabuf;
2341 mutex_unlock(&mem->lock);
2345 /* Evict a userptr BO by stopping the queues if necessary
2347 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
2348 * cannot do any memory allocations, and cannot take any locks that
2349 * are held elsewhere while allocating memory.
2351 * It doesn't do anything to the BO itself. The real work happens in
2352 * restore, where we get updated page addresses. This function only
2353 * ensures that GPU access to the BO is stopped.
2355 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
2356 unsigned long cur_seq, struct kgd_mem *mem)
2358 struct amdkfd_process_info *process_info = mem->process_info;
2361 /* Do not process MMU notifications during CRIU restore until
2362 * KFD_CRIU_OP_RESUME IOCTL is received
2364 if (READ_ONCE(process_info->block_mmu_notifications))
2367 mutex_lock(&process_info->notifier_lock);
2368 mmu_interval_set_seq(mni, cur_seq);
2371 if (++process_info->evicted_bos == 1) {
2372 /* First eviction, stop the queues */
2373 r = kgd2kfd_quiesce_mm(mni->mm,
2374 KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
2376 pr_err("Failed to quiesce KFD\n");
2377 schedule_delayed_work(&process_info->restore_userptr_work,
2378 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2380 mutex_unlock(&process_info->notifier_lock);
2385 /* Update invalid userptr BOs
2387 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
2388 * userptr_inval_list and updates user pages for all BOs that have
2389 * been invalidated since their last update.
2391 static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
2392 struct mm_struct *mm)
2394 struct kgd_mem *mem, *tmp_mem;
2395 struct amdgpu_bo *bo;
2396 struct ttm_operation_ctx ctx = { false, false };
2400 mutex_lock(&process_info->notifier_lock);
2402 /* Move all invalidated BOs to the userptr_inval_list */
2403 list_for_each_entry_safe(mem, tmp_mem,
2404 &process_info->userptr_valid_list,
2407 list_move_tail(&mem->validate_list,
2408 &process_info->userptr_inval_list);
2410 /* Go through userptr_inval_list and update any invalid user_pages */
2411 list_for_each_entry(mem, &process_info->userptr_inval_list,
2413 invalid = mem->invalid;
2415 /* BO hasn't been invalidated since the last
2416 * revalidation attempt. Keep its page list.
2422 amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range);
2425 /* BO reservations and getting user pages (hmm_range_fault)
2426 * must happen outside the notifier lock
2428 mutex_unlock(&process_info->notifier_lock);
2430 /* Move the BO to system (CPU) domain if necessary to unmap
2431 * and free the SG table
2433 if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) {
2434 if (amdgpu_bo_reserve(bo, true))
2436 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2437 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2438 amdgpu_bo_unreserve(bo);
2440 pr_err("%s: Failed to invalidate userptr BO\n",
2446 /* Get updated user pages */
2447 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
2450 pr_debug("Failed %d to get user pages\n", ret);
2452 /* Return -EFAULT bad address error as success. It will
2453 * fail later with a VM fault if the GPU tries to access
2454 * it. Better than hanging indefinitely with stalled
2457 * Return other error -EBUSY or -ENOMEM to retry restore
2465 mutex_lock(&process_info->notifier_lock);
2467 /* Mark the BO as valid unless it was invalidated
2468 * again concurrently.
2470 if (mem->invalid != invalid) {
2474 /* set mem valid if mem has hmm range associated */
2480 mutex_unlock(&process_info->notifier_lock);
2485 /* Validate invalid userptr BOs
2487 * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables
2488 * with new page addresses and waits for the page table updates to complete.
2490 static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2492 struct ttm_operation_ctx ctx = { false, false };
2493 struct amdgpu_sync sync;
2494 struct drm_exec exec;
2496 struct amdgpu_vm *peer_vm;
2497 struct kgd_mem *mem, *tmp_mem;
2498 struct amdgpu_bo *bo;
2501 amdgpu_sync_create(&sync);
2503 drm_exec_init(&exec, 0);
2504 /* Reserve all BOs and page tables for validation */
2505 drm_exec_until_all_locked(&exec) {
2506 /* Reserve all the page directories */
2507 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2509 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2510 drm_exec_retry_on_contention(&exec);
2515 /* Reserve the userptr_inval_list entries to resv_list */
2516 list_for_each_entry(mem, &process_info->userptr_inval_list,
2518 struct drm_gem_object *gobj;
2520 gobj = &mem->bo->tbo.base;
2521 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2522 drm_exec_retry_on_contention(&exec);
2528 ret = process_validate_vms(process_info);
2532 /* Validate BOs and update GPUVM page tables */
2533 list_for_each_entry_safe(mem, tmp_mem,
2534 &process_info->userptr_inval_list,
2536 struct kfd_mem_attachment *attachment;
2540 /* Validate the BO if we got user pages */
2541 if (bo->tbo.ttm->pages[0]) {
2542 amdgpu_bo_placement_from_domain(bo, mem->domain);
2543 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2545 pr_err("%s: failed to validate BO\n", __func__);
2550 /* Update mapping. If the BO was not validated
2551 * (because we couldn't get user pages), this will
2552 * clear the page table entries, which will result in
2553 * VM faults if the GPU tries to access the invalid
2556 list_for_each_entry(attachment, &mem->attachments, list) {
2557 if (!attachment->is_mapped)
2560 kfd_mem_dmaunmap_attachment(mem, attachment);
2561 ret = update_gpuvm_pte(mem, attachment, &sync);
2563 pr_err("%s: update PTE failed\n", __func__);
2564 /* make sure this gets validated again */
2565 mutex_lock(&process_info->notifier_lock);
2567 mutex_unlock(&process_info->notifier_lock);
2573 /* Update page directories */
2574 ret = process_update_pds(process_info, &sync);
2577 drm_exec_fini(&exec);
2578 amdgpu_sync_wait(&sync, false);
2579 amdgpu_sync_free(&sync);
2584 /* Confirm that all user pages are valid while holding the notifier lock
2586 * Moves valid BOs from the userptr_inval_list back to userptr_val_list.
2588 static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info)
2590 struct kgd_mem *mem, *tmp_mem;
2593 list_for_each_entry_safe(mem, tmp_mem,
2594 &process_info->userptr_inval_list,
2598 /* keep mem without hmm range at userptr_inval_list */
2602 /* Only check mem with hmm range associated */
2603 valid = amdgpu_ttm_tt_get_user_pages_done(
2604 mem->bo->tbo.ttm, mem->range);
2608 WARN(!mem->invalid, "Invalid BO not marked invalid");
2614 WARN(1, "Valid BO is marked invalid");
2619 list_move_tail(&mem->validate_list,
2620 &process_info->userptr_valid_list);
2626 /* Worker callback to restore evicted userptr BOs
2628 * Tries to update and validate all userptr BOs. If successful and no
2629 * concurrent evictions happened, the queues are restarted. Otherwise,
2630 * reschedule for another attempt later.
2632 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2634 struct delayed_work *dwork = to_delayed_work(work);
2635 struct amdkfd_process_info *process_info =
2636 container_of(dwork, struct amdkfd_process_info,
2637 restore_userptr_work);
2638 struct task_struct *usertask;
2639 struct mm_struct *mm;
2640 uint32_t evicted_bos;
2642 mutex_lock(&process_info->notifier_lock);
2643 evicted_bos = process_info->evicted_bos;
2644 mutex_unlock(&process_info->notifier_lock);
2648 /* Reference task and mm in case of concurrent process termination */
2649 usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2652 mm = get_task_mm(usertask);
2654 put_task_struct(usertask);
2658 mutex_lock(&process_info->lock);
2660 if (update_invalid_user_pages(process_info, mm))
2662 /* userptr_inval_list can be empty if all evicted userptr BOs
2663 * have been freed. In that case there is nothing to validate
2664 * and we can just restart the queues.
2666 if (!list_empty(&process_info->userptr_inval_list)) {
2667 if (validate_invalid_user_pages(process_info))
2670 /* Final check for concurrent evicton and atomic update. If
2671 * another eviction happens after successful update, it will
2672 * be a first eviction that calls quiesce_mm. The eviction
2673 * reference counting inside KFD will handle this case.
2675 mutex_lock(&process_info->notifier_lock);
2676 if (process_info->evicted_bos != evicted_bos)
2677 goto unlock_notifier_out;
2679 if (confirm_valid_user_pages_locked(process_info)) {
2680 WARN(1, "User pages unexpectedly invalid");
2681 goto unlock_notifier_out;
2684 process_info->evicted_bos = evicted_bos = 0;
2686 if (kgd2kfd_resume_mm(mm)) {
2687 pr_err("%s: Failed to resume KFD\n", __func__);
2688 /* No recovery from this failure. Probably the CP is
2689 * hanging. No point trying again.
2693 unlock_notifier_out:
2694 mutex_unlock(&process_info->notifier_lock);
2696 mutex_unlock(&process_info->lock);
2698 /* If validation failed, reschedule another attempt */
2700 schedule_delayed_work(&process_info->restore_userptr_work,
2701 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2703 kfd_smi_event_queue_restore_rescheduled(mm);
2706 put_task_struct(usertask);
2709 /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2710 * KFD process identified by process_info
2712 * @process_info: amdkfd_process_info of the KFD process
2714 * After memory eviction, restore thread calls this function. The function
2715 * should be called when the Process is still valid. BO restore involves -
2717 * 1. Release old eviction fence and create new one
2718 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2719 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2720 * BOs that need to be reserved.
2721 * 4. Reserve all the BOs
2722 * 5. Validate of PD and PT BOs.
2723 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2724 * 7. Add fence to all PD and PT BOs.
2725 * 8. Unreserve all BOs
2727 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
2729 struct amdkfd_process_info *process_info = info;
2730 struct amdgpu_vm *peer_vm;
2731 struct kgd_mem *mem;
2732 struct amdgpu_amdkfd_fence *new_fence;
2733 struct list_head duplicate_save;
2734 struct amdgpu_sync sync_obj;
2735 unsigned long failed_size = 0;
2736 unsigned long total_size = 0;
2737 struct drm_exec exec;
2740 INIT_LIST_HEAD(&duplicate_save);
2742 mutex_lock(&process_info->lock);
2744 drm_exec_init(&exec, 0);
2745 drm_exec_until_all_locked(&exec) {
2746 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2748 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2749 drm_exec_retry_on_contention(&exec);
2751 goto ttm_reserve_fail;
2754 /* Reserve all BOs and page tables/directory. Add all BOs from
2755 * kfd_bo_list to ctx.list
2757 list_for_each_entry(mem, &process_info->kfd_bo_list,
2759 struct drm_gem_object *gobj;
2761 gobj = &mem->bo->tbo.base;
2762 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2763 drm_exec_retry_on_contention(&exec);
2765 goto ttm_reserve_fail;
2769 amdgpu_sync_create(&sync_obj);
2771 /* Validate PDs and PTs */
2772 ret = process_validate_vms(process_info);
2774 goto validate_map_fail;
2776 ret = process_sync_pds_resv(process_info, &sync_obj);
2778 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2779 goto validate_map_fail;
2782 /* Validate BOs and map them to GPUVM (update VM page tables). */
2783 list_for_each_entry(mem, &process_info->kfd_bo_list,
2786 struct amdgpu_bo *bo = mem->bo;
2787 uint32_t domain = mem->domain;
2788 struct kfd_mem_attachment *attachment;
2789 struct dma_resv_iter cursor;
2790 struct dma_fence *fence;
2792 total_size += amdgpu_bo_size(bo);
2794 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2796 pr_debug("Memory eviction: Validate BOs failed\n");
2797 failed_size += amdgpu_bo_size(bo);
2798 ret = amdgpu_amdkfd_bo_validate(bo,
2799 AMDGPU_GEM_DOMAIN_GTT, false);
2801 pr_debug("Memory eviction: Try again\n");
2802 goto validate_map_fail;
2805 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
2806 DMA_RESV_USAGE_KERNEL, fence) {
2807 ret = amdgpu_sync_fence(&sync_obj, fence);
2809 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2810 goto validate_map_fail;
2813 list_for_each_entry(attachment, &mem->attachments, list) {
2814 if (!attachment->is_mapped)
2817 if (attachment->bo_va->base.bo->tbo.pin_count)
2820 kfd_mem_dmaunmap_attachment(mem, attachment);
2821 ret = update_gpuvm_pte(mem, attachment, &sync_obj);
2823 pr_debug("Memory eviction: update PTE failed. Try again\n");
2824 goto validate_map_fail;
2830 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2832 /* Update page directories */
2833 ret = process_update_pds(process_info, &sync_obj);
2835 pr_debug("Memory eviction: update PDs failed. Try again\n");
2836 goto validate_map_fail;
2839 /* Wait for validate and PT updates to finish */
2840 amdgpu_sync_wait(&sync_obj, false);
2842 /* Release old eviction fence and create new one, because fence only
2843 * goes from unsignaled to signaled, fence cannot be reused.
2844 * Use context and mm from the old fence.
2846 new_fence = amdgpu_amdkfd_fence_create(
2847 process_info->eviction_fence->base.context,
2848 process_info->eviction_fence->mm,
2851 pr_err("Failed to create eviction fence\n");
2853 goto validate_map_fail;
2855 dma_fence_put(&process_info->eviction_fence->base);
2856 process_info->eviction_fence = new_fence;
2857 *ef = dma_fence_get(&new_fence->base);
2859 /* Attach new eviction fence to all BOs except pinned ones */
2860 list_for_each_entry(mem, &process_info->kfd_bo_list, validate_list) {
2861 if (mem->bo->tbo.pin_count)
2864 dma_resv_add_fence(mem->bo->tbo.base.resv,
2865 &process_info->eviction_fence->base,
2866 DMA_RESV_USAGE_BOOKKEEP);
2868 /* Attach eviction fence to PD / PT BOs */
2869 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2871 struct amdgpu_bo *bo = peer_vm->root.bo;
2873 dma_resv_add_fence(bo->tbo.base.resv,
2874 &process_info->eviction_fence->base,
2875 DMA_RESV_USAGE_BOOKKEEP);
2879 amdgpu_sync_free(&sync_obj);
2881 drm_exec_fini(&exec);
2882 mutex_unlock(&process_info->lock);
2886 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
2888 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2889 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
2895 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2899 mutex_init(&(*mem)->lock);
2900 INIT_LIST_HEAD(&(*mem)->attachments);
2901 (*mem)->bo = amdgpu_bo_ref(gws_bo);
2902 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
2903 (*mem)->process_info = process_info;
2904 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
2905 amdgpu_sync_create(&(*mem)->sync);
2908 /* Validate gws bo the first time it is added to process */
2909 mutex_lock(&(*mem)->process_info->lock);
2910 ret = amdgpu_bo_reserve(gws_bo, false);
2911 if (unlikely(ret)) {
2912 pr_err("Reserve gws bo failed %d\n", ret);
2913 goto bo_reservation_failure;
2916 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
2918 pr_err("GWS BO validate failed %d\n", ret);
2919 goto bo_validation_failure;
2921 /* GWS resource is shared b/t amdgpu and amdkfd
2922 * Add process eviction fence to bo so they can
2925 ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
2927 goto reserve_shared_fail;
2928 dma_resv_add_fence(gws_bo->tbo.base.resv,
2929 &process_info->eviction_fence->base,
2930 DMA_RESV_USAGE_BOOKKEEP);
2931 amdgpu_bo_unreserve(gws_bo);
2932 mutex_unlock(&(*mem)->process_info->lock);
2936 reserve_shared_fail:
2937 bo_validation_failure:
2938 amdgpu_bo_unreserve(gws_bo);
2939 bo_reservation_failure:
2940 mutex_unlock(&(*mem)->process_info->lock);
2941 amdgpu_sync_free(&(*mem)->sync);
2942 remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
2943 amdgpu_bo_unref(&gws_bo);
2944 mutex_destroy(&(*mem)->lock);
2950 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
2953 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2954 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
2955 struct amdgpu_bo *gws_bo = kgd_mem->bo;
2957 /* Remove BO from process's validate list so restore worker won't touch
2960 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
2962 ret = amdgpu_bo_reserve(gws_bo, false);
2963 if (unlikely(ret)) {
2964 pr_err("Reserve gws bo failed %d\n", ret);
2965 //TODO add BO back to validate_list?
2968 amdgpu_amdkfd_remove_eviction_fence(gws_bo,
2969 process_info->eviction_fence);
2970 amdgpu_bo_unreserve(gws_bo);
2971 amdgpu_sync_free(&kgd_mem->sync);
2972 amdgpu_bo_unref(&gws_bo);
2973 mutex_destroy(&kgd_mem->lock);
2978 /* Returns GPU-specific tiling mode information */
2979 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
2980 struct tile_config *config)
2982 config->gb_addr_config = adev->gfx.config.gb_addr_config;
2983 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
2984 config->num_tile_configs =
2985 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2986 config->macro_tile_config_ptr =
2987 adev->gfx.config.macrotile_mode_array;
2988 config->num_macro_tile_configs =
2989 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2991 /* Those values are not set from GFX9 onwards */
2992 config->num_banks = adev->gfx.config.num_banks;
2993 config->num_ranks = adev->gfx.config.num_ranks;
2998 bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem)
3000 struct kfd_mem_attachment *entry;
3002 list_for_each_entry(entry, &mem->attachments, list) {
3003 if (entry->is_mapped && entry->adev == adev)
3009 #if defined(CONFIG_DEBUG_FS)
3011 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data)
3014 spin_lock(&kfd_mem_limit.mem_limit_lock);
3015 seq_printf(m, "System mem used %lldM out of %lluM\n",
3016 (kfd_mem_limit.system_mem_used >> 20),
3017 (kfd_mem_limit.max_system_mem_limit >> 20));
3018 seq_printf(m, "TTM mem used %lldM out of %lluM\n",
3019 (kfd_mem_limit.ttm_mem_used >> 20),
3020 (kfd_mem_limit.max_ttm_mem_limit >> 20));
3021 spin_unlock(&kfd_mem_limit.mem_limit_lock);