1 // SPDX-License-Identifier: MIT
3 * Copyright 2014-2018 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/dma-buf.h>
24 #include <linux/list.h>
25 #include <linux/pagemap.h>
26 #include <linux/sched/mm.h>
27 #include <linux/sched/task.h>
28 #include <drm/ttm/ttm_tt.h>
30 #include <drm/drm_exec.h>
32 #include "amdgpu_object.h"
33 #include "amdgpu_gem.h"
34 #include "amdgpu_vm.h"
35 #include "amdgpu_hmm.h"
36 #include "amdgpu_amdkfd.h"
37 #include "amdgpu_dma_buf.h"
38 #include <uapi/linux/kfd_ioctl.h>
39 #include "amdgpu_xgmi.h"
41 #include "kfd_smi_events.h"
42 #include <drm/ttm/ttm_tt.h>
44 /* Userptr restore delay, just long enough to allow consecutive VM
45 * changes to accumulate
47 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
50 * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
53 #define VRAM_AVAILABLITY_ALIGN (1 << 21)
55 /* Impose limit on how much memory KFD can use */
57 uint64_t max_system_mem_limit;
58 uint64_t max_ttm_mem_limit;
59 int64_t system_mem_used;
61 spinlock_t mem_limit_lock;
64 static const char * const domain_bit_to_string[] = {
73 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
75 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
77 static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
80 struct kfd_mem_attachment *entry;
82 list_for_each_entry(entry, &mem->attachments, list)
83 if (entry->bo_va->base.vm == avm)
90 * reuse_dmamap() - Check whether adev can share the original
93 * If both adev and bo_adev are in direct mapping or
94 * in the same iommu group, they can share the original BO.
96 * @adev: Device to which can or cannot share the original BO
97 * @bo_adev: Device to which allocated BO belongs to
99 * Return: returns true if adev can share original userptr BO,
102 static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev)
104 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) ||
105 (adev->dev->iommu_group == bo_adev->dev->iommu_group);
108 /* Set memory usage limits. Current, limits are
109 * System (TTM + userptr) memory - 15/16th System RAM
110 * TTM memory - 3/8th System RAM
112 void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
117 if (kfd_mem_limit.max_system_mem_limit)
121 mem = si.freeram - si.freehigh;
124 spin_lock_init(&kfd_mem_limit.mem_limit_lock);
125 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 4);
126 kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT;
127 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
128 (kfd_mem_limit.max_system_mem_limit >> 20),
129 (kfd_mem_limit.max_ttm_mem_limit >> 20));
132 void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
134 kfd_mem_limit.system_mem_used += size;
137 /* Estimate page table size needed to represent a given memory size
139 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
140 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
141 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
142 * for 2MB pages for TLB efficiency. However, small allocations and
143 * fragmented system memory still need some 4KB pages. We choose a
144 * compromise that should work in most cases without reserving too
145 * much memory for page tables unnecessarily (factor 16K, >> 14).
148 #define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM)
151 * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
154 * @adev: Device to which allocated BO belongs to
155 * @size: Size of buffer, in bytes, encapsulated by B0. This should be
156 * equivalent to amdgpu_bo_size(BO)
157 * @alloc_flag: Flag used in allocating a BO as noted above
158 * @xcp_id: xcp_id is used to get xcp from xcp manager, one xcp is
159 * managed as one compute node in driver for app
162 * returns -ENOMEM in case of error, ZERO otherwise
164 int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
165 uint64_t size, u32 alloc_flag, int8_t xcp_id)
167 uint64_t reserved_for_pt =
168 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
169 size_t system_mem_needed, ttm_mem_needed, vram_needed;
171 uint64_t vram_size = 0;
173 system_mem_needed = 0;
176 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
177 system_mem_needed = size;
178 ttm_mem_needed = size;
179 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
181 * Conservatively round up the allocation requirement to 2 MB
182 * to avoid fragmentation caused by 4K allocations in the tail
187 * For GFX 9.4.3, get the VRAM size from XCP structs
189 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
192 vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
193 if (adev->gmc.is_app_apu) {
194 system_mem_needed = size;
195 ttm_mem_needed = size;
197 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
198 system_mem_needed = size;
199 } else if (!(alloc_flag &
200 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
201 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
202 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
206 spin_lock(&kfd_mem_limit.mem_limit_lock);
208 if (kfd_mem_limit.system_mem_used + system_mem_needed >
209 kfd_mem_limit.max_system_mem_limit)
210 pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
212 if ((kfd_mem_limit.system_mem_used + system_mem_needed >
213 kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
214 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
215 kfd_mem_limit.max_ttm_mem_limit) ||
216 (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed >
217 vram_size - reserved_for_pt)) {
222 /* Update memory accounting by decreasing available system
223 * memory, TTM memory and GPU memory as computed above
225 WARN_ONCE(vram_needed && !adev,
226 "adev reference can't be null when vram is used");
227 if (adev && xcp_id >= 0) {
228 adev->kfd.vram_used[xcp_id] += vram_needed;
229 adev->kfd.vram_used_aligned[xcp_id] += adev->gmc.is_app_apu ?
231 ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);
233 kfd_mem_limit.system_mem_used += system_mem_needed;
234 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
237 spin_unlock(&kfd_mem_limit.mem_limit_lock);
241 void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
242 uint64_t size, u32 alloc_flag, int8_t xcp_id)
244 spin_lock(&kfd_mem_limit.mem_limit_lock);
246 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
247 kfd_mem_limit.system_mem_used -= size;
248 kfd_mem_limit.ttm_mem_used -= size;
249 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
251 "adev reference can't be null when alloc mem flags vram is set");
252 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
256 adev->kfd.vram_used[xcp_id] -= size;
257 if (adev->gmc.is_app_apu) {
258 adev->kfd.vram_used_aligned[xcp_id] -= size;
259 kfd_mem_limit.system_mem_used -= size;
260 kfd_mem_limit.ttm_mem_used -= size;
262 adev->kfd.vram_used_aligned[xcp_id] -=
263 ALIGN(size, VRAM_AVAILABLITY_ALIGN);
266 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
267 kfd_mem_limit.system_mem_used -= size;
268 } else if (!(alloc_flag &
269 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
270 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
271 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
274 WARN_ONCE(adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] < 0,
275 "KFD VRAM memory accounting unbalanced for xcp: %d", xcp_id);
276 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
277 "KFD TTM memory accounting unbalanced");
278 WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
279 "KFD system memory accounting unbalanced");
282 spin_unlock(&kfd_mem_limit.mem_limit_lock);
285 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
287 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
288 u32 alloc_flags = bo->kfd_bo->alloc_flags;
289 u64 size = amdgpu_bo_size(bo);
291 amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags,
298 * create_dmamap_sg_bo() - Creates a amdgpu_bo object to reflect information
299 * about USERPTR or DOOREBELL or MMIO BO.
301 * @adev: Device for which dmamap BO is being created
302 * @mem: BO of peer device that is being DMA mapped. Provides parameters
303 * in building the dmamap BO
304 * @bo_out: Output parameter updated with handle of dmamap BO
307 create_dmamap_sg_bo(struct amdgpu_device *adev,
308 struct kgd_mem *mem, struct amdgpu_bo **bo_out)
310 struct drm_gem_object *gem_obj;
314 ret = amdgpu_bo_reserve(mem->bo, false);
318 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)
319 flags |= mem->bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
320 AMDGPU_GEM_CREATE_UNCACHED);
322 ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1,
323 AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags,
324 ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0);
326 amdgpu_bo_unreserve(mem->bo);
329 pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret);
333 *bo_out = gem_to_amdgpu_bo(gem_obj);
334 (*bo_out)->parent = amdgpu_bo_ref(mem->bo);
338 /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
339 * reservation object.
341 * @bo: [IN] Remove eviction fence(s) from this BO
342 * @ef: [IN] This eviction fence is removed if it
343 * is present in the shared list.
345 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
347 static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
348 struct amdgpu_amdkfd_fence *ef)
350 struct dma_fence *replacement;
355 /* TODO: Instead of block before we should use the fence of the page
356 * table update and TLB flush here directly.
358 replacement = dma_fence_get_stub();
359 dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
360 replacement, DMA_RESV_USAGE_BOOKKEEP);
361 dma_fence_put(replacement);
365 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
367 struct amdgpu_bo *root = bo;
368 struct amdgpu_vm_bo_base *vm_bo;
369 struct amdgpu_vm *vm;
370 struct amdkfd_process_info *info;
371 struct amdgpu_amdkfd_fence *ef;
374 /* we can always get vm_bo from root PD bo.*/
386 info = vm->process_info;
387 if (!info || !info->eviction_fence)
390 ef = container_of(dma_fence_get(&info->eviction_fence->base),
391 struct amdgpu_amdkfd_fence, base);
393 BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
394 ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
395 dma_resv_unlock(bo->tbo.base.resv);
397 dma_fence_put(&ef->base);
401 static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
404 struct ttm_operation_ctx ctx = { false, false };
407 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
408 "Called with userptr BO"))
411 amdgpu_bo_placement_from_domain(bo, domain);
413 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
417 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
423 static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
425 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
428 /* vm_validate_pt_pd_bos - Validate page table and directory BOs
430 * Page directories are not updated here because huge page handling
431 * during page table updates can invalidate page directory entries
432 * again. Page directories are only updated after updating page
435 static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
437 struct amdgpu_bo *pd = vm->root.bo;
438 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
441 ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL);
443 pr_err("failed to validate PT BOs\n");
447 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
452 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
454 struct amdgpu_bo *pd = vm->root.bo;
455 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
458 ret = amdgpu_vm_update_pdes(adev, vm, false);
462 return amdgpu_sync_fence(sync, vm->last_update);
465 static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
467 uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE |
468 AMDGPU_VM_MTYPE_DEFAULT;
470 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
471 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
472 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
473 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
475 return amdgpu_gem_va_map_flags(adev, mapping_flags);
479 * create_sg_table() - Create an sg_table for a contiguous DMA addr range
480 * @addr: The starting address to point to
481 * @size: Size of memory area in bytes being pointed to
483 * Allocates an instance of sg_table and initializes it to point to memory
484 * area specified by input parameters. The address used to build is assumed
485 * to be DMA mapped, if needed.
487 * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table
488 * because they are physically contiguous.
490 * Return: Initialized instance of SG Table or NULL
492 static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)
494 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
498 if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
502 sg_dma_address(sg->sgl) = addr;
503 sg->sgl->length = size;
504 #ifdef CONFIG_NEED_SG_DMA_LENGTH
505 sg->sgl->dma_length = size;
511 kfd_mem_dmamap_userptr(struct kgd_mem *mem,
512 struct kfd_mem_attachment *attachment)
514 enum dma_data_direction direction =
515 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
516 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
517 struct ttm_operation_ctx ctx = {.interruptible = true};
518 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
519 struct amdgpu_device *adev = attachment->adev;
520 struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
521 struct ttm_tt *ttm = bo->tbo.ttm;
524 if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
527 ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
528 if (unlikely(!ttm->sg))
531 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */
532 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
534 (u64)ttm->num_pages << PAGE_SHIFT,
539 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
543 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
544 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
551 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
553 pr_err("DMA map userptr failed: %d\n", ret);
554 sg_free_table(ttm->sg);
562 kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
564 struct ttm_operation_ctx ctx = {.interruptible = true};
565 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
568 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
569 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
573 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
574 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
578 * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO
579 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
580 * @attachment: Virtual address attachment of the BO on accessing device
582 * An access request from the device that owns DOORBELL does not require DMA mapping.
583 * This is because the request doesn't go through PCIe root complex i.e. it instead
584 * loops back. The need to DMA map arises only when accessing peer device's DOORBELL
586 * In contrast, all access requests for MMIO need to be DMA mapped without regard to
587 * device ownership. This is because access requests for MMIO go through PCIe root
590 * This is accomplished in two steps:
591 * - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used
592 * in updating requesting device's page table
593 * - Signal TTM to mark memory pointed to by requesting device's BO as GPU
594 * accessible. This allows an update of requesting device's page table
595 * with entries associated with DOOREBELL or MMIO memory
597 * This method is invoked in the following contexts:
598 * - Mapping of DOORBELL or MMIO BO of same or peer device
599 * - Validating an evicted DOOREBELL or MMIO BO on device seeking access
601 * Return: ZERO if successful, NON-ZERO otherwise
604 kfd_mem_dmamap_sg_bo(struct kgd_mem *mem,
605 struct kfd_mem_attachment *attachment)
607 struct ttm_operation_ctx ctx = {.interruptible = true};
608 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
609 struct amdgpu_device *adev = attachment->adev;
610 struct ttm_tt *ttm = bo->tbo.ttm;
611 enum dma_data_direction dir;
616 /* Expect SG Table of dmapmap BO to be NULL */
617 mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
618 if (unlikely(ttm->sg)) {
619 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
623 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
624 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
625 dma_addr = mem->bo->tbo.sg->sgl->dma_address;
626 pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
627 pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
628 dma_addr = dma_map_resource(adev->dev, dma_addr,
629 mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
630 ret = dma_mapping_error(adev->dev, dma_addr);
633 pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
635 ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length);
636 if (unlikely(!ttm->sg)) {
641 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
642 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
649 sg_free_table(ttm->sg);
653 dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length,
654 dir, DMA_ATTR_SKIP_CPU_SYNC);
659 kfd_mem_dmamap_attachment(struct kgd_mem *mem,
660 struct kfd_mem_attachment *attachment)
662 switch (attachment->type) {
663 case KFD_MEM_ATT_SHARED:
665 case KFD_MEM_ATT_USERPTR:
666 return kfd_mem_dmamap_userptr(mem, attachment);
667 case KFD_MEM_ATT_DMABUF:
668 return kfd_mem_dmamap_dmabuf(attachment);
670 return kfd_mem_dmamap_sg_bo(mem, attachment);
678 kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
679 struct kfd_mem_attachment *attachment)
681 enum dma_data_direction direction =
682 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
683 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
684 struct ttm_operation_ctx ctx = {.interruptible = false};
685 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
686 struct amdgpu_device *adev = attachment->adev;
687 struct ttm_tt *ttm = bo->tbo.ttm;
689 if (unlikely(!ttm->sg))
692 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
693 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
695 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
696 sg_free_table(ttm->sg);
702 kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
704 /* This is a no-op. We don't want to trigger eviction fences when
705 * unmapping DMABufs. Therefore the invalidation (moving to system
706 * domain) is done in kfd_mem_dmamap_dmabuf.
711 * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO
712 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
713 * @attachment: Virtual address attachment of the BO on accessing device
715 * The method performs following steps:
716 * - Signal TTM to mark memory pointed to by BO as GPU inaccessible
717 * - Free SG Table that is used to encapsulate DMA mapped memory of
718 * peer device's DOORBELL or MMIO memory
720 * This method is invoked in the following contexts:
721 * UNMapping of DOORBELL or MMIO BO on a device having access to its memory
722 * Eviction of DOOREBELL or MMIO BO on device having access to its memory
727 kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
728 struct kfd_mem_attachment *attachment)
730 struct ttm_operation_ctx ctx = {.interruptible = true};
731 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
732 struct amdgpu_device *adev = attachment->adev;
733 struct ttm_tt *ttm = bo->tbo.ttm;
734 enum dma_data_direction dir;
736 if (unlikely(!ttm->sg)) {
737 pr_err("SG Table of BO is UNEXPECTEDLY NULL");
741 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
742 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
744 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
745 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
746 dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address,
747 ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
748 sg_free_table(ttm->sg);
755 kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
756 struct kfd_mem_attachment *attachment)
758 switch (attachment->type) {
759 case KFD_MEM_ATT_SHARED:
761 case KFD_MEM_ATT_USERPTR:
762 kfd_mem_dmaunmap_userptr(mem, attachment);
764 case KFD_MEM_ATT_DMABUF:
765 kfd_mem_dmaunmap_dmabuf(attachment);
768 kfd_mem_dmaunmap_sg_bo(mem, attachment);
775 static int kfd_mem_export_dmabuf(struct kgd_mem *mem)
778 struct dma_buf *ret = amdgpu_gem_prime_export(
780 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
791 kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
792 struct amdgpu_bo **bo)
794 struct drm_gem_object *gobj;
797 ret = kfd_mem_export_dmabuf(mem);
801 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
803 return PTR_ERR(gobj);
805 *bo = gem_to_amdgpu_bo(gobj);
806 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
811 /* kfd_mem_attach - Add a BO to a VM
813 * Everything that needs to bo done only once when a BO is first added
814 * to a VM. It can later be mapped and unmapped many times without
815 * repeating these steps.
817 * 0. Create BO for DMA mapping, if needed
818 * 1. Allocate and initialize BO VA entry data structure
819 * 2. Add BO to the VM
820 * 3. Determine ASIC-specific PTE flags
821 * 4. Alloc page tables and directories if needed
822 * 4a. Validate new page tables and directories
824 static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
825 struct amdgpu_vm *vm, bool is_aql)
827 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
828 unsigned long bo_size = mem->bo->tbo.base.size;
829 uint64_t va = mem->va;
830 struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
831 struct amdgpu_bo *bo[2] = {NULL, NULL};
832 bool same_hive = false;
836 pr_err("Invalid VA when adding BO to VM\n");
840 /* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices
842 * The access path of MMIO and DOORBELL BOs of is always over PCIe.
843 * In contrast the access path of VRAM BOs depens upon the type of
844 * link that connects the peer device. Access over PCIe is allowed
845 * if peer device has large BAR. In contrast, access over xGMI is
846 * allowed for both small and large BAR configurations of peer device
848 if ((adev != bo_adev && !adev->gmc.is_app_apu) &&
849 ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
850 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
851 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
852 if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM)
853 same_hive = amdgpu_xgmi_same_hive(adev, bo_adev);
854 if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev))
858 for (i = 0; i <= is_aql; i++) {
859 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
860 if (unlikely(!attachment[i])) {
865 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
868 if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
869 (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) ||
871 /* Mappings on the local GPU, or VRAM mappings in the
872 * local hive, or userptr mapping can reuse dma map
873 * address space share the original BO
875 attachment[i]->type = KFD_MEM_ATT_SHARED;
877 drm_gem_object_get(&bo[i]->tbo.base);
879 /* Multiple mappings on the same GPU share the BO */
880 attachment[i]->type = KFD_MEM_ATT_SHARED;
882 drm_gem_object_get(&bo[i]->tbo.base);
883 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
884 /* Create an SG BO to DMA-map userptrs on other GPUs */
885 attachment[i]->type = KFD_MEM_ATT_USERPTR;
886 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
889 /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */
890 } else if (mem->bo->tbo.type == ttm_bo_type_sg) {
891 WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL ||
892 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP),
893 "Handing invalid SG BO in ATTACH request");
894 attachment[i]->type = KFD_MEM_ATT_SG;
895 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
898 /* Enable acces to GTT and VRAM BOs of peer devices */
899 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT ||
900 mem->domain == AMDGPU_GEM_DOMAIN_VRAM) {
901 attachment[i]->type = KFD_MEM_ATT_DMABUF;
902 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
905 pr_debug("Employ DMABUF mechanism to enable peer GPU access\n");
907 WARN_ONCE(true, "Handling invalid ATTACH request");
912 /* Add BO to VM internal data structures */
913 ret = amdgpu_bo_reserve(bo[i], false);
915 pr_debug("Unable to reserve BO during memory attach");
918 attachment[i]->bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
919 amdgpu_bo_unreserve(bo[i]);
920 if (unlikely(!attachment[i]->bo_va)) {
922 pr_err("Failed to add BO object to VM. ret == %d\n",
926 attachment[i]->va = va;
927 attachment[i]->pte_flags = get_pte_flags(adev, mem);
928 attachment[i]->adev = adev;
929 list_add(&attachment[i]->list, &mem->attachments);
937 for (; i >= 0; i--) {
940 if (attachment[i]->bo_va) {
941 amdgpu_bo_reserve(bo[i], true);
942 amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
943 amdgpu_bo_unreserve(bo[i]);
944 list_del(&attachment[i]->list);
947 drm_gem_object_put(&bo[i]->tbo.base);
948 kfree(attachment[i]);
953 static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
955 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
957 pr_debug("\t remove VA 0x%llx in entry %p\n",
958 attachment->va, attachment);
959 amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
960 drm_gem_object_put(&bo->tbo.base);
961 list_del(&attachment->list);
965 static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
966 struct amdkfd_process_info *process_info,
969 mutex_lock(&process_info->lock);
971 list_add_tail(&mem->validate_list,
972 &process_info->userptr_valid_list);
974 list_add_tail(&mem->validate_list, &process_info->kfd_bo_list);
975 mutex_unlock(&process_info->lock);
978 static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
979 struct amdkfd_process_info *process_info)
981 mutex_lock(&process_info->lock);
982 list_del(&mem->validate_list);
983 mutex_unlock(&process_info->lock);
986 /* Initializes user pages. It registers the MMU notifier and validates
987 * the userptr BO in the GTT domain.
989 * The BO must already be on the userptr_valid_list. Otherwise an
990 * eviction and restore may happen that leaves the new BO unmapped
991 * with the user mode queues running.
993 * Takes the process_info->lock to protect against concurrent restore
996 * Returns 0 for success, negative errno for errors.
998 static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
1001 struct amdkfd_process_info *process_info = mem->process_info;
1002 struct amdgpu_bo *bo = mem->bo;
1003 struct ttm_operation_ctx ctx = { true, false };
1004 struct hmm_range *range;
1007 mutex_lock(&process_info->lock);
1009 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
1011 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
1015 ret = amdgpu_hmm_register(bo, user_addr);
1017 pr_err("%s: Failed to register MMU notifier: %d\n",
1024 * During a CRIU restore operation, the userptr buffer objects
1025 * will be validated in the restore_userptr_work worker at a
1026 * later stage when it is scheduled by another ioctl called by
1027 * CRIU master process for the target pid for restore.
1029 mutex_lock(&process_info->notifier_lock);
1031 mutex_unlock(&process_info->notifier_lock);
1032 mutex_unlock(&process_info->lock);
1036 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range);
1038 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
1039 goto unregister_out;
1042 ret = amdgpu_bo_reserve(bo, true);
1044 pr_err("%s: Failed to reserve BO\n", __func__);
1047 amdgpu_bo_placement_from_domain(bo, mem->domain);
1048 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1050 pr_err("%s: failed to validate BO\n", __func__);
1051 amdgpu_bo_unreserve(bo);
1054 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
1057 amdgpu_hmm_unregister(bo);
1059 mutex_unlock(&process_info->lock);
1063 /* Reserving a BO and its page table BOs must happen atomically to
1064 * avoid deadlocks. Some operations update multiple VMs at once. Track
1065 * all the reservation info in a context structure. Optionally a sync
1066 * object can track VM updates.
1068 struct bo_vm_reservation_context {
1069 /* DRM execution context for the reservation */
1070 struct drm_exec exec;
1071 /* Number of VMs reserved */
1073 /* Pointer to sync object */
1074 struct amdgpu_sync *sync;
1078 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */
1079 BO_VM_MAPPED, /* Match VMs where a BO is mapped */
1080 BO_VM_ALL, /* Match all VMs a BO was added to */
1084 * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
1085 * @mem: KFD BO structure.
1086 * @vm: the VM to reserve.
1087 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1089 static int reserve_bo_and_vm(struct kgd_mem *mem,
1090 struct amdgpu_vm *vm,
1091 struct bo_vm_reservation_context *ctx)
1093 struct amdgpu_bo *bo = mem->bo;
1099 ctx->sync = &mem->sync;
1100 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT);
1101 drm_exec_until_all_locked(&ctx->exec) {
1102 ret = amdgpu_vm_lock_pd(vm, &ctx->exec, 2);
1103 drm_exec_retry_on_contention(&ctx->exec);
1107 ret = drm_exec_lock_obj(&ctx->exec, &bo->tbo.base);
1108 drm_exec_retry_on_contention(&ctx->exec);
1115 pr_err("Failed to reserve buffers in ttm.\n");
1116 drm_exec_fini(&ctx->exec);
1121 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
1122 * @mem: KFD BO structure.
1123 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
1124 * is used. Otherwise, a single VM associated with the BO.
1125 * @map_type: the mapping status that will be used to filter the VMs.
1126 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1128 * Returns 0 for success, negative for failure.
1130 static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
1131 struct amdgpu_vm *vm, enum bo_vm_match map_type,
1132 struct bo_vm_reservation_context *ctx)
1134 struct kfd_mem_attachment *entry;
1135 struct amdgpu_bo *bo = mem->bo;
1138 ctx->sync = &mem->sync;
1139 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT);
1140 drm_exec_until_all_locked(&ctx->exec) {
1142 list_for_each_entry(entry, &mem->attachments, list) {
1143 if ((vm && vm != entry->bo_va->base.vm) ||
1144 (entry->is_mapped != map_type
1145 && map_type != BO_VM_ALL))
1148 ret = amdgpu_vm_lock_pd(entry->bo_va->base.vm,
1150 drm_exec_retry_on_contention(&ctx->exec);
1156 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1157 drm_exec_retry_on_contention(&ctx->exec);
1164 pr_err("Failed to reserve buffers in ttm.\n");
1165 drm_exec_fini(&ctx->exec);
1170 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1171 * @ctx: Reservation context to unreserve
1172 * @wait: Optionally wait for a sync object representing pending VM updates
1173 * @intr: Whether the wait is interruptible
1175 * Also frees any resources allocated in
1176 * reserve_bo_and_(cond_)vm(s). Returns the status from
1179 static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1180 bool wait, bool intr)
1185 ret = amdgpu_sync_wait(ctx->sync, intr);
1187 drm_exec_fini(&ctx->exec);
1192 static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
1193 struct kfd_mem_attachment *entry,
1194 struct amdgpu_sync *sync)
1196 struct amdgpu_bo_va *bo_va = entry->bo_va;
1197 struct amdgpu_device *adev = entry->adev;
1198 struct amdgpu_vm *vm = bo_va->base.vm;
1200 amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1202 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1204 amdgpu_sync_fence(sync, bo_va->last_pt_update);
1206 kfd_mem_dmaunmap_attachment(mem, entry);
1209 static int update_gpuvm_pte(struct kgd_mem *mem,
1210 struct kfd_mem_attachment *entry,
1211 struct amdgpu_sync *sync)
1213 struct amdgpu_bo_va *bo_va = entry->bo_va;
1214 struct amdgpu_device *adev = entry->adev;
1217 ret = kfd_mem_dmamap_attachment(mem, entry);
1221 /* Update the page tables */
1222 ret = amdgpu_vm_bo_update(adev, bo_va, false);
1224 pr_err("amdgpu_vm_bo_update failed\n");
1228 return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1231 static int map_bo_to_gpuvm(struct kgd_mem *mem,
1232 struct kfd_mem_attachment *entry,
1233 struct amdgpu_sync *sync,
1238 /* Set virtual address for the allocation */
1239 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1240 amdgpu_bo_size(entry->bo_va->base.bo),
1243 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1251 ret = update_gpuvm_pte(mem, entry, sync);
1253 pr_err("update_gpuvm_pte() failed\n");
1254 goto update_gpuvm_pte_failed;
1259 update_gpuvm_pte_failed:
1260 unmap_bo_from_gpuvm(mem, entry, sync);
1264 static int process_validate_vms(struct amdkfd_process_info *process_info)
1266 struct amdgpu_vm *peer_vm;
1269 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1271 ret = vm_validate_pt_pd_bos(peer_vm);
1279 static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1280 struct amdgpu_sync *sync)
1282 struct amdgpu_vm *peer_vm;
1285 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1287 struct amdgpu_bo *pd = peer_vm->root.bo;
1289 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1290 AMDGPU_SYNC_NE_OWNER,
1291 AMDGPU_FENCE_OWNER_KFD);
1299 static int process_update_pds(struct amdkfd_process_info *process_info,
1300 struct amdgpu_sync *sync)
1302 struct amdgpu_vm *peer_vm;
1305 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1307 ret = vm_update_pds(peer_vm, sync);
1315 static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1316 struct dma_fence **ef)
1318 struct amdkfd_process_info *info = NULL;
1321 if (!*process_info) {
1322 info = kzalloc(sizeof(*info), GFP_KERNEL);
1326 mutex_init(&info->lock);
1327 mutex_init(&info->notifier_lock);
1328 INIT_LIST_HEAD(&info->vm_list_head);
1329 INIT_LIST_HEAD(&info->kfd_bo_list);
1330 INIT_LIST_HEAD(&info->userptr_valid_list);
1331 INIT_LIST_HEAD(&info->userptr_inval_list);
1333 info->eviction_fence =
1334 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1337 if (!info->eviction_fence) {
1338 pr_err("Failed to create eviction fence\n");
1340 goto create_evict_fence_fail;
1343 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1344 INIT_DELAYED_WORK(&info->restore_userptr_work,
1345 amdgpu_amdkfd_restore_userptr_worker);
1347 *process_info = info;
1348 *ef = dma_fence_get(&info->eviction_fence->base);
1351 vm->process_info = *process_info;
1353 /* Validate page directory and attach eviction fence */
1354 ret = amdgpu_bo_reserve(vm->root.bo, true);
1356 goto reserve_pd_fail;
1357 ret = vm_validate_pt_pd_bos(vm);
1359 pr_err("validate_pt_pd_bos() failed\n");
1360 goto validate_pd_fail;
1362 ret = amdgpu_bo_sync_wait(vm->root.bo,
1363 AMDGPU_FENCE_OWNER_KFD, false);
1366 ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
1368 goto reserve_shared_fail;
1369 dma_resv_add_fence(vm->root.bo->tbo.base.resv,
1370 &vm->process_info->eviction_fence->base,
1371 DMA_RESV_USAGE_BOOKKEEP);
1372 amdgpu_bo_unreserve(vm->root.bo);
1374 /* Update process info */
1375 mutex_lock(&vm->process_info->lock);
1376 list_add_tail(&vm->vm_list_node,
1377 &(vm->process_info->vm_list_head));
1378 vm->process_info->n_vms++;
1379 mutex_unlock(&vm->process_info->lock);
1383 reserve_shared_fail:
1386 amdgpu_bo_unreserve(vm->root.bo);
1388 vm->process_info = NULL;
1390 /* Two fence references: one in info and one in *ef */
1391 dma_fence_put(&info->eviction_fence->base);
1394 *process_info = NULL;
1396 create_evict_fence_fail:
1397 mutex_destroy(&info->lock);
1398 mutex_destroy(&info->notifier_lock);
1405 * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria
1406 * @bo: Handle of buffer object being pinned
1407 * @domain: Domain into which BO should be pinned
1409 * - USERPTR BOs are UNPINNABLE and will return error
1410 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1411 * PIN count incremented. It is valid to PIN a BO multiple times
1413 * Return: ZERO if successful in pinning, Non-Zero in case of error.
1415 static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)
1419 ret = amdgpu_bo_reserve(bo, false);
1423 ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1425 pr_err("Error in Pinning BO to domain: %d\n", domain);
1427 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
1428 amdgpu_bo_unreserve(bo);
1434 * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria
1435 * @bo: Handle of buffer object being unpinned
1437 * - Is a illegal request for USERPTR BOs and is ignored
1438 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1439 * PIN count decremented. Calls to UNPIN must balance calls to PIN
1441 static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
1445 ret = amdgpu_bo_reserve(bo, false);
1449 amdgpu_bo_unpin(bo);
1450 amdgpu_bo_unreserve(bo);
1453 int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
1454 struct amdgpu_vm *avm, u32 pasid)
1459 /* Free the original amdgpu allocated pasid,
1460 * will be replaced with kfd allocated pasid.
1463 amdgpu_pasid_free(avm->pasid);
1464 amdgpu_vm_set_pasid(adev, avm, 0);
1467 ret = amdgpu_vm_set_pasid(adev, avm, pasid);
1474 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
1475 struct amdgpu_vm *avm,
1476 void **process_info,
1477 struct dma_fence **ef)
1481 /* Already a compute VM? */
1482 if (avm->process_info)
1485 /* Convert VM into a compute VM */
1486 ret = amdgpu_vm_make_compute(adev, avm);
1490 /* Initialize KFD part of the VM and process info */
1491 ret = init_kfd_vm(avm, process_info, ef);
1495 amdgpu_vm_set_task_info(avm);
1500 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1501 struct amdgpu_vm *vm)
1503 struct amdkfd_process_info *process_info = vm->process_info;
1508 /* Update process info */
1509 mutex_lock(&process_info->lock);
1510 process_info->n_vms--;
1511 list_del(&vm->vm_list_node);
1512 mutex_unlock(&process_info->lock);
1514 vm->process_info = NULL;
1516 /* Release per-process resources when last compute VM is destroyed */
1517 if (!process_info->n_vms) {
1518 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1519 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1520 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1522 dma_fence_put(&process_info->eviction_fence->base);
1523 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1524 put_pid(process_info->pid);
1525 mutex_destroy(&process_info->lock);
1526 mutex_destroy(&process_info->notifier_lock);
1527 kfree(process_info);
1531 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
1534 struct amdgpu_vm *avm;
1536 if (WARN_ON(!adev || !drm_priv))
1539 avm = drm_priv_to_vm(drm_priv);
1541 pr_debug("Releasing process vm %p\n", avm);
1543 /* The original pasid of amdgpu vm has already been
1544 * released during making a amdgpu vm to a compute vm
1545 * The current pasid is managed by kfd and will be
1546 * released on kfd process destroy. Set amdgpu pasid
1547 * to 0 to avoid duplicate release.
1549 amdgpu_vm_release_compute(adev, avm);
1552 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1554 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1555 struct amdgpu_bo *pd = avm->root.bo;
1556 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1558 if (adev->asic_type < CHIP_VEGA10)
1559 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1560 return avm->pd_phys_addr;
1563 void amdgpu_amdkfd_block_mmu_notifications(void *p)
1565 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1567 mutex_lock(&pinfo->lock);
1568 WRITE_ONCE(pinfo->block_mmu_notifications, true);
1569 mutex_unlock(&pinfo->lock);
1572 int amdgpu_amdkfd_criu_resume(void *p)
1575 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1577 mutex_lock(&pinfo->lock);
1578 pr_debug("scheduling work\n");
1579 mutex_lock(&pinfo->notifier_lock);
1580 pinfo->evicted_bos++;
1581 mutex_unlock(&pinfo->notifier_lock);
1582 if (!READ_ONCE(pinfo->block_mmu_notifications)) {
1586 WRITE_ONCE(pinfo->block_mmu_notifications, false);
1587 schedule_delayed_work(&pinfo->restore_userptr_work, 0);
1590 mutex_unlock(&pinfo->lock);
1594 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
1597 uint64_t reserved_for_pt =
1598 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
1600 uint64_t vram_available, system_mem_available, ttm_mem_available;
1602 spin_lock(&kfd_mem_limit.mem_limit_lock);
1603 vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)
1604 - adev->kfd.vram_used_aligned[xcp_id]
1605 - atomic64_read(&adev->vram_pin_size)
1608 if (adev->gmc.is_app_apu) {
1609 system_mem_available = no_system_mem_limit ?
1610 kfd_mem_limit.max_system_mem_limit :
1611 kfd_mem_limit.max_system_mem_limit -
1612 kfd_mem_limit.system_mem_used;
1614 ttm_mem_available = kfd_mem_limit.max_ttm_mem_limit -
1615 kfd_mem_limit.ttm_mem_used;
1617 available = min3(system_mem_available, ttm_mem_available,
1619 available = ALIGN_DOWN(available, PAGE_SIZE);
1621 available = ALIGN_DOWN(vram_available, VRAM_AVAILABLITY_ALIGN);
1624 spin_unlock(&kfd_mem_limit.mem_limit_lock);
1632 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1633 struct amdgpu_device *adev, uint64_t va, uint64_t size,
1634 void *drm_priv, struct kgd_mem **mem,
1635 uint64_t *offset, uint32_t flags, bool criu_resume)
1637 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1638 struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm);
1639 enum ttm_bo_type bo_type = ttm_bo_type_device;
1640 struct sg_table *sg = NULL;
1641 uint64_t user_addr = 0;
1642 struct amdgpu_bo *bo;
1643 struct drm_gem_object *gobj = NULL;
1644 u32 domain, alloc_domain;
1645 uint64_t aligned_size;
1651 * Check on which domain to allocate BO
1653 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1654 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1656 if (adev->gmc.is_app_apu) {
1657 domain = AMDGPU_GEM_DOMAIN_GTT;
1658 alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1661 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1662 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1663 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1665 xcp_id = fpriv->xcp_id == ~0 ? 0 : fpriv->xcp_id;
1666 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1667 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1670 domain = AMDGPU_GEM_DOMAIN_GTT;
1671 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1672 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1674 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1675 if (!offset || !*offset)
1677 user_addr = untagged_addr(*offset);
1678 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1679 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1680 bo_type = ttm_bo_type_sg;
1681 if (size > UINT_MAX)
1683 sg = create_sg_table(*offset, size);
1691 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
1692 alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
1693 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
1694 alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
1696 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1701 INIT_LIST_HEAD(&(*mem)->attachments);
1702 mutex_init(&(*mem)->lock);
1703 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1705 /* Workaround for AQL queue wraparound bug. Map the same
1706 * memory twice. That means we only actually allocate half
1709 if ((*mem)->aql_queue)
1711 aligned_size = PAGE_ALIGN(size);
1713 (*mem)->alloc_flags = flags;
1715 amdgpu_sync_create(&(*mem)->sync);
1717 ret = amdgpu_amdkfd_reserve_mem_limit(adev, aligned_size, flags,
1720 pr_debug("Insufficient memory\n");
1721 goto err_reserve_limit;
1724 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s xcp_id %d\n",
1725 va, (*mem)->aql_queue ? size << 1 : size,
1726 domain_string(alloc_domain), xcp_id);
1728 ret = amdgpu_gem_object_create(adev, aligned_size, 1, alloc_domain, alloc_flags,
1729 bo_type, NULL, &gobj, xcp_id + 1);
1731 pr_debug("Failed to create BO on domain %s. ret %d\n",
1732 domain_string(alloc_domain), ret);
1735 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1737 pr_debug("Failed to allow vma node access. ret %d\n", ret);
1738 goto err_node_allow;
1740 bo = gem_to_amdgpu_bo(gobj);
1741 if (bo_type == ttm_bo_type_sg) {
1743 bo->tbo.ttm->sg = sg;
1748 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1751 (*mem)->domain = domain;
1752 (*mem)->mapped_to_gpu_memory = 0;
1753 (*mem)->process_info = avm->process_info;
1755 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1758 pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
1759 ret = init_user_pages(*mem, user_addr, criu_resume);
1761 goto allocate_init_user_pages_failed;
1762 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1763 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1764 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT);
1766 pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n");
1769 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
1770 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
1774 *offset = amdgpu_bo_mmap_offset(bo);
1778 allocate_init_user_pages_failed:
1780 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1781 drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1783 /* Don't unreserve system mem limit twice */
1784 goto err_reserve_limit;
1786 amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id);
1788 mutex_destroy(&(*mem)->lock);
1790 drm_gem_object_put(gobj);
1801 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1802 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
1805 struct amdkfd_process_info *process_info = mem->process_info;
1806 unsigned long bo_size = mem->bo->tbo.base.size;
1807 bool use_release_notifier = (mem->bo->kfd_bo == mem);
1808 struct kfd_mem_attachment *entry, *tmp;
1809 struct bo_vm_reservation_context ctx;
1810 unsigned int mapped_to_gpu_memory;
1812 bool is_imported = false;
1814 mutex_lock(&mem->lock);
1816 /* Unpin MMIO/DOORBELL BO's that were pinned during allocation */
1817 if (mem->alloc_flags &
1818 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1819 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1820 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo);
1823 mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1824 is_imported = mem->is_imported;
1825 mutex_unlock(&mem->lock);
1826 /* lock is not needed after this, since mem is unused and will
1830 if (mapped_to_gpu_memory > 0) {
1831 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1836 /* Make sure restore workers don't access the BO any more */
1837 mutex_lock(&process_info->lock);
1838 list_del(&mem->validate_list);
1839 mutex_unlock(&process_info->lock);
1841 /* Cleanup user pages and MMU notifiers */
1842 if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
1843 amdgpu_hmm_unregister(mem->bo);
1844 mutex_lock(&process_info->notifier_lock);
1845 amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range);
1846 mutex_unlock(&process_info->notifier_lock);
1849 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1853 /* The eviction fence should be removed by the last unmap.
1854 * TODO: Log an error condition if the bo still has the eviction fence
1857 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1858 process_info->eviction_fence);
1859 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1860 mem->va + bo_size * (1 + mem->aql_queue));
1862 /* Remove from VM internal data structures */
1863 list_for_each_entry_safe(entry, tmp, &mem->attachments, list)
1864 kfd_mem_detach(entry);
1866 ret = unreserve_bo_and_vms(&ctx, false, false);
1868 /* Free the sync object */
1869 amdgpu_sync_free(&mem->sync);
1871 /* If the SG is not NULL, it's one we created for a doorbell or mmio
1872 * remap BO. We need to free it.
1874 if (mem->bo->tbo.sg) {
1875 sg_free_table(mem->bo->tbo.sg);
1876 kfree(mem->bo->tbo.sg);
1879 /* Update the size of the BO being freed if it was allocated from
1880 * VRAM and is not imported. For APP APU VRAM allocations are done
1885 (mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM ||
1886 (adev->gmc.is_app_apu &&
1887 mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT)))
1894 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1896 dma_buf_put(mem->dmabuf);
1897 mutex_destroy(&mem->lock);
1899 /* If this releases the last reference, it will end up calling
1900 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why
1901 * this needs to be the last call here.
1903 drm_gem_object_put(&mem->bo->tbo.base);
1906 * For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(),
1907 * explicitly free it here.
1909 if (!use_release_notifier)
1915 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1916 struct amdgpu_device *adev, struct kgd_mem *mem,
1919 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1921 struct amdgpu_bo *bo;
1923 struct kfd_mem_attachment *entry;
1924 struct bo_vm_reservation_context ctx;
1925 unsigned long bo_size;
1926 bool is_invalid_userptr = false;
1930 pr_err("Invalid BO when mapping memory to GPU\n");
1934 /* Make sure restore is not running concurrently. Since we
1935 * don't map invalid userptr BOs, we rely on the next restore
1936 * worker to do the mapping
1938 mutex_lock(&mem->process_info->lock);
1940 /* Lock notifier lock. If we find an invalid userptr BO, we can be
1941 * sure that the MMU notifier is no longer running
1942 * concurrently and the queues are actually stopped
1944 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1945 mutex_lock(&mem->process_info->notifier_lock);
1946 is_invalid_userptr = !!mem->invalid;
1947 mutex_unlock(&mem->process_info->notifier_lock);
1950 mutex_lock(&mem->lock);
1952 domain = mem->domain;
1953 bo_size = bo->tbo.base.size;
1955 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
1957 mem->va + bo_size * (1 + mem->aql_queue),
1958 avm, domain_string(domain));
1960 if (!kfd_mem_is_attached(avm, mem)) {
1961 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
1966 ret = reserve_bo_and_vm(mem, avm, &ctx);
1970 /* Userptr can be marked as "not invalid", but not actually be
1971 * validated yet (still in the system domain). In that case
1972 * the queues are still stopped and we can leave mapping for
1973 * the next restore worker
1975 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
1976 bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
1977 is_invalid_userptr = true;
1979 ret = vm_validate_pt_pd_bos(avm);
1983 if (mem->mapped_to_gpu_memory == 0 &&
1984 !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1985 /* Validate BO only once. The eviction fence gets added to BO
1986 * the first time it is mapped. Validate will wait for all
1987 * background evictions to complete.
1989 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
1991 pr_debug("Validate failed\n");
1996 list_for_each_entry(entry, &mem->attachments, list) {
1997 if (entry->bo_va->base.vm != avm || entry->is_mapped)
2000 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
2001 entry->va, entry->va + bo_size, entry);
2003 ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
2004 is_invalid_userptr);
2006 pr_err("Failed to map bo to gpuvm\n");
2010 ret = vm_update_pds(avm, ctx.sync);
2012 pr_err("Failed to update page directories\n");
2016 entry->is_mapped = true;
2017 mem->mapped_to_gpu_memory++;
2018 pr_debug("\t INC mapping count %d\n",
2019 mem->mapped_to_gpu_memory);
2022 if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count)
2023 dma_resv_add_fence(bo->tbo.base.resv,
2024 &avm->process_info->eviction_fence->base,
2025 DMA_RESV_USAGE_BOOKKEEP);
2026 ret = unreserve_bo_and_vms(&ctx, false, false);
2031 unreserve_bo_and_vms(&ctx, false, false);
2033 mutex_unlock(&mem->process_info->lock);
2034 mutex_unlock(&mem->lock);
2038 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
2039 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
2041 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2042 struct amdkfd_process_info *process_info = avm->process_info;
2043 unsigned long bo_size = mem->bo->tbo.base.size;
2044 struct kfd_mem_attachment *entry;
2045 struct bo_vm_reservation_context ctx;
2048 mutex_lock(&mem->lock);
2050 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
2053 /* If no VMs were reserved, it means the BO wasn't actually mapped */
2054 if (ctx.n_vms == 0) {
2059 ret = vm_validate_pt_pd_bos(avm);
2063 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
2065 mem->va + bo_size * (1 + mem->aql_queue),
2068 list_for_each_entry(entry, &mem->attachments, list) {
2069 if (entry->bo_va->base.vm != avm || !entry->is_mapped)
2072 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
2073 entry->va, entry->va + bo_size, entry);
2075 unmap_bo_from_gpuvm(mem, entry, ctx.sync);
2076 entry->is_mapped = false;
2078 mem->mapped_to_gpu_memory--;
2079 pr_debug("\t DEC mapping count %d\n",
2080 mem->mapped_to_gpu_memory);
2083 /* If BO is unmapped from all VMs, unfence it. It can be evicted if
2086 if (mem->mapped_to_gpu_memory == 0 &&
2087 !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) &&
2088 !mem->bo->tbo.pin_count)
2089 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
2090 process_info->eviction_fence);
2093 unreserve_bo_and_vms(&ctx, false, false);
2095 mutex_unlock(&mem->lock);
2099 int amdgpu_amdkfd_gpuvm_sync_memory(
2100 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
2102 struct amdgpu_sync sync;
2105 amdgpu_sync_create(&sync);
2107 mutex_lock(&mem->lock);
2108 amdgpu_sync_clone(&mem->sync, &sync);
2109 mutex_unlock(&mem->lock);
2111 ret = amdgpu_sync_wait(&sync, intr);
2112 amdgpu_sync_free(&sync);
2117 * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count
2118 * @adev: Device to which allocated BO belongs
2119 * @bo: Buffer object to be mapped
2121 * Before return, bo reference count is incremented. To release the reference and unpin/
2122 * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
2124 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo)
2128 ret = amdgpu_bo_reserve(bo, true);
2130 pr_err("Failed to reserve bo. ret %d\n", ret);
2131 goto err_reserve_bo_failed;
2134 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2136 pr_err("Failed to pin bo. ret %d\n", ret);
2137 goto err_pin_bo_failed;
2140 ret = amdgpu_ttm_alloc_gart(&bo->tbo);
2142 pr_err("Failed to bind bo to GART. ret %d\n", ret);
2143 goto err_map_bo_gart_failed;
2146 amdgpu_amdkfd_remove_eviction_fence(
2147 bo, bo->vm_bo->vm->process_info->eviction_fence);
2149 amdgpu_bo_unreserve(bo);
2151 bo = amdgpu_bo_ref(bo);
2155 err_map_bo_gart_failed:
2156 amdgpu_bo_unpin(bo);
2158 amdgpu_bo_unreserve(bo);
2159 err_reserve_bo_failed:
2164 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access
2166 * @mem: Buffer object to be mapped for CPU access
2167 * @kptr[out]: pointer in kernel CPU address space
2168 * @size[out]: size of the buffer
2170 * Pins the BO and maps it for kernel CPU access. The eviction fence is removed
2171 * from the BO, since pinned BOs cannot be evicted. The bo must remain on the
2172 * validate_list, so the GPU mapping can be restored after a page table was
2175 * Return: 0 on success, error code on failure
2177 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
2178 void **kptr, uint64_t *size)
2181 struct amdgpu_bo *bo = mem->bo;
2183 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2184 pr_err("userptr can't be mapped to kernel\n");
2188 mutex_lock(&mem->process_info->lock);
2190 ret = amdgpu_bo_reserve(bo, true);
2192 pr_err("Failed to reserve bo. ret %d\n", ret);
2193 goto bo_reserve_failed;
2196 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2198 pr_err("Failed to pin bo. ret %d\n", ret);
2202 ret = amdgpu_bo_kmap(bo, kptr);
2204 pr_err("Failed to map bo to kernel. ret %d\n", ret);
2208 amdgpu_amdkfd_remove_eviction_fence(
2209 bo, mem->process_info->eviction_fence);
2212 *size = amdgpu_bo_size(bo);
2214 amdgpu_bo_unreserve(bo);
2216 mutex_unlock(&mem->process_info->lock);
2220 amdgpu_bo_unpin(bo);
2222 amdgpu_bo_unreserve(bo);
2224 mutex_unlock(&mem->process_info->lock);
2229 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access
2231 * @mem: Buffer object to be unmapped for CPU access
2233 * Removes the kernel CPU mapping and unpins the BO. It does not restore the
2234 * eviction fence, so this function should only be used for cleanup before the
2237 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)
2239 struct amdgpu_bo *bo = mem->bo;
2241 amdgpu_bo_reserve(bo, true);
2242 amdgpu_bo_kunmap(bo);
2243 amdgpu_bo_unpin(bo);
2244 amdgpu_bo_unreserve(bo);
2247 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
2248 struct kfd_vm_fault_info *mem)
2250 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
2251 *mem = *adev->gmc.vm_fault_info;
2252 mb(); /* make sure read happened */
2253 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
2258 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev,
2259 struct dma_buf *dma_buf,
2260 uint64_t va, void *drm_priv,
2261 struct kgd_mem **mem, uint64_t *size,
2262 uint64_t *mmap_offset)
2264 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2265 struct drm_gem_object *obj;
2266 struct amdgpu_bo *bo;
2269 obj = amdgpu_gem_prime_import(adev_to_drm(adev), dma_buf);
2271 return PTR_ERR(obj);
2273 bo = gem_to_amdgpu_bo(obj);
2274 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
2275 AMDGPU_GEM_DOMAIN_GTT))) {
2276 /* Only VRAM and GTT BOs are supported */
2281 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2287 ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
2292 *size = amdgpu_bo_size(bo);
2295 *mmap_offset = amdgpu_bo_mmap_offset(bo);
2297 INIT_LIST_HEAD(&(*mem)->attachments);
2298 mutex_init(&(*mem)->lock);
2300 (*mem)->alloc_flags =
2301 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2302 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
2303 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
2304 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
2306 get_dma_buf(dma_buf);
2307 (*mem)->dmabuf = dma_buf;
2310 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !adev->gmc.is_app_apu ?
2311 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
2313 (*mem)->mapped_to_gpu_memory = 0;
2314 (*mem)->process_info = avm->process_info;
2315 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
2316 amdgpu_sync_create(&(*mem)->sync);
2317 (*mem)->is_imported = true;
2324 drm_gem_object_put(obj);
2328 int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
2329 struct dma_buf **dma_buf)
2333 mutex_lock(&mem->lock);
2334 ret = kfd_mem_export_dmabuf(mem);
2338 get_dma_buf(mem->dmabuf);
2339 *dma_buf = mem->dmabuf;
2341 mutex_unlock(&mem->lock);
2345 /* Evict a userptr BO by stopping the queues if necessary
2347 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
2348 * cannot do any memory allocations, and cannot take any locks that
2349 * are held elsewhere while allocating memory.
2351 * It doesn't do anything to the BO itself. The real work happens in
2352 * restore, where we get updated page addresses. This function only
2353 * ensures that GPU access to the BO is stopped.
2355 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
2356 unsigned long cur_seq, struct kgd_mem *mem)
2358 struct amdkfd_process_info *process_info = mem->process_info;
2361 /* Do not process MMU notifications during CRIU restore until
2362 * KFD_CRIU_OP_RESUME IOCTL is received
2364 if (READ_ONCE(process_info->block_mmu_notifications))
2367 mutex_lock(&process_info->notifier_lock);
2368 mmu_interval_set_seq(mni, cur_seq);
2371 if (++process_info->evicted_bos == 1) {
2372 /* First eviction, stop the queues */
2373 r = kgd2kfd_quiesce_mm(mni->mm,
2374 KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
2376 pr_err("Failed to quiesce KFD\n");
2377 schedule_delayed_work(&process_info->restore_userptr_work,
2378 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2380 mutex_unlock(&process_info->notifier_lock);
2385 /* Update invalid userptr BOs
2387 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
2388 * userptr_inval_list and updates user pages for all BOs that have
2389 * been invalidated since their last update.
2391 static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
2392 struct mm_struct *mm)
2394 struct kgd_mem *mem, *tmp_mem;
2395 struct amdgpu_bo *bo;
2396 struct ttm_operation_ctx ctx = { false, false };
2400 mutex_lock(&process_info->notifier_lock);
2402 /* Move all invalidated BOs to the userptr_inval_list */
2403 list_for_each_entry_safe(mem, tmp_mem,
2404 &process_info->userptr_valid_list,
2407 list_move_tail(&mem->validate_list,
2408 &process_info->userptr_inval_list);
2410 /* Go through userptr_inval_list and update any invalid user_pages */
2411 list_for_each_entry(mem, &process_info->userptr_inval_list,
2413 invalid = mem->invalid;
2415 /* BO hasn't been invalidated since the last
2416 * revalidation attempt. Keep its page list.
2422 amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range);
2425 /* BO reservations and getting user pages (hmm_range_fault)
2426 * must happen outside the notifier lock
2428 mutex_unlock(&process_info->notifier_lock);
2430 /* Move the BO to system (CPU) domain if necessary to unmap
2431 * and free the SG table
2433 if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) {
2434 if (amdgpu_bo_reserve(bo, true))
2436 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2437 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2438 amdgpu_bo_unreserve(bo);
2440 pr_err("%s: Failed to invalidate userptr BO\n",
2446 /* Get updated user pages */
2447 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
2450 pr_debug("Failed %d to get user pages\n", ret);
2452 /* Return -EFAULT bad address error as success. It will
2453 * fail later with a VM fault if the GPU tries to access
2454 * it. Better than hanging indefinitely with stalled
2457 * Return other error -EBUSY or -ENOMEM to retry restore
2465 mutex_lock(&process_info->notifier_lock);
2467 /* Mark the BO as valid unless it was invalidated
2468 * again concurrently.
2470 if (mem->invalid != invalid) {
2474 /* set mem valid if mem has hmm range associated */
2480 mutex_unlock(&process_info->notifier_lock);
2485 /* Validate invalid userptr BOs
2487 * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables
2488 * with new page addresses and waits for the page table updates to complete.
2490 static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2492 struct ttm_operation_ctx ctx = { false, false };
2493 struct amdgpu_sync sync;
2494 struct drm_exec exec;
2496 struct amdgpu_vm *peer_vm;
2497 struct kgd_mem *mem, *tmp_mem;
2498 struct amdgpu_bo *bo;
2501 amdgpu_sync_create(&sync);
2503 drm_exec_init(&exec, 0);
2504 /* Reserve all BOs and page tables for validation */
2505 drm_exec_until_all_locked(&exec) {
2506 /* Reserve all the page directories */
2507 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2509 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2510 drm_exec_retry_on_contention(&exec);
2515 /* Reserve the userptr_inval_list entries to resv_list */
2516 list_for_each_entry(mem, &process_info->userptr_inval_list,
2518 struct drm_gem_object *gobj;
2520 gobj = &mem->bo->tbo.base;
2521 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2522 drm_exec_retry_on_contention(&exec);
2528 ret = process_validate_vms(process_info);
2532 /* Validate BOs and update GPUVM page tables */
2533 list_for_each_entry_safe(mem, tmp_mem,
2534 &process_info->userptr_inval_list,
2536 struct kfd_mem_attachment *attachment;
2540 /* Validate the BO if we got user pages */
2541 if (bo->tbo.ttm->pages[0]) {
2542 amdgpu_bo_placement_from_domain(bo, mem->domain);
2543 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2545 pr_err("%s: failed to validate BO\n", __func__);
2550 /* Update mapping. If the BO was not validated
2551 * (because we couldn't get user pages), this will
2552 * clear the page table entries, which will result in
2553 * VM faults if the GPU tries to access the invalid
2556 list_for_each_entry(attachment, &mem->attachments, list) {
2557 if (!attachment->is_mapped)
2560 kfd_mem_dmaunmap_attachment(mem, attachment);
2561 ret = update_gpuvm_pte(mem, attachment, &sync);
2563 pr_err("%s: update PTE failed\n", __func__);
2564 /* make sure this gets validated again */
2565 mutex_lock(&process_info->notifier_lock);
2567 mutex_unlock(&process_info->notifier_lock);
2573 /* Update page directories */
2574 ret = process_update_pds(process_info, &sync);
2577 drm_exec_fini(&exec);
2578 amdgpu_sync_wait(&sync, false);
2579 amdgpu_sync_free(&sync);
2584 /* Confirm that all user pages are valid while holding the notifier lock
2586 * Moves valid BOs from the userptr_inval_list back to userptr_val_list.
2588 static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info)
2590 struct kgd_mem *mem, *tmp_mem;
2593 list_for_each_entry_safe(mem, tmp_mem,
2594 &process_info->userptr_inval_list,
2598 /* keep mem without hmm range at userptr_inval_list */
2602 /* Only check mem with hmm range associated */
2603 valid = amdgpu_ttm_tt_get_user_pages_done(
2604 mem->bo->tbo.ttm, mem->range);
2608 WARN(!mem->invalid, "Invalid BO not marked invalid");
2614 WARN(1, "Valid BO is marked invalid");
2619 list_move_tail(&mem->validate_list,
2620 &process_info->userptr_valid_list);
2626 /* Worker callback to restore evicted userptr BOs
2628 * Tries to update and validate all userptr BOs. If successful and no
2629 * concurrent evictions happened, the queues are restarted. Otherwise,
2630 * reschedule for another attempt later.
2632 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2634 struct delayed_work *dwork = to_delayed_work(work);
2635 struct amdkfd_process_info *process_info =
2636 container_of(dwork, struct amdkfd_process_info,
2637 restore_userptr_work);
2638 struct task_struct *usertask;
2639 struct mm_struct *mm;
2640 uint32_t evicted_bos;
2642 mutex_lock(&process_info->notifier_lock);
2643 evicted_bos = process_info->evicted_bos;
2644 mutex_unlock(&process_info->notifier_lock);
2648 /* Reference task and mm in case of concurrent process termination */
2649 usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2652 mm = get_task_mm(usertask);
2654 put_task_struct(usertask);
2658 mutex_lock(&process_info->lock);
2660 if (update_invalid_user_pages(process_info, mm))
2662 /* userptr_inval_list can be empty if all evicted userptr BOs
2663 * have been freed. In that case there is nothing to validate
2664 * and we can just restart the queues.
2666 if (!list_empty(&process_info->userptr_inval_list)) {
2667 if (validate_invalid_user_pages(process_info))
2670 /* Final check for concurrent evicton and atomic update. If
2671 * another eviction happens after successful update, it will
2672 * be a first eviction that calls quiesce_mm. The eviction
2673 * reference counting inside KFD will handle this case.
2675 mutex_lock(&process_info->notifier_lock);
2676 if (process_info->evicted_bos != evicted_bos)
2677 goto unlock_notifier_out;
2679 if (confirm_valid_user_pages_locked(process_info)) {
2680 WARN(1, "User pages unexpectedly invalid");
2681 goto unlock_notifier_out;
2684 process_info->evicted_bos = evicted_bos = 0;
2686 if (kgd2kfd_resume_mm(mm)) {
2687 pr_err("%s: Failed to resume KFD\n", __func__);
2688 /* No recovery from this failure. Probably the CP is
2689 * hanging. No point trying again.
2693 unlock_notifier_out:
2694 mutex_unlock(&process_info->notifier_lock);
2696 mutex_unlock(&process_info->lock);
2698 /* If validation failed, reschedule another attempt */
2700 schedule_delayed_work(&process_info->restore_userptr_work,
2701 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2703 kfd_smi_event_queue_restore_rescheduled(mm);
2706 put_task_struct(usertask);
2709 /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2710 * KFD process identified by process_info
2712 * @process_info: amdkfd_process_info of the KFD process
2714 * After memory eviction, restore thread calls this function. The function
2715 * should be called when the Process is still valid. BO restore involves -
2717 * 1. Release old eviction fence and create new one
2718 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2719 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2720 * BOs that need to be reserved.
2721 * 4. Reserve all the BOs
2722 * 5. Validate of PD and PT BOs.
2723 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2724 * 7. Add fence to all PD and PT BOs.
2725 * 8. Unreserve all BOs
2727 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
2729 struct amdkfd_process_info *process_info = info;
2730 struct amdgpu_vm *peer_vm;
2731 struct kgd_mem *mem;
2732 struct amdgpu_amdkfd_fence *new_fence;
2733 struct list_head duplicate_save;
2734 struct amdgpu_sync sync_obj;
2735 unsigned long failed_size = 0;
2736 unsigned long total_size = 0;
2737 struct drm_exec exec;
2740 INIT_LIST_HEAD(&duplicate_save);
2742 mutex_lock(&process_info->lock);
2744 drm_exec_init(&exec, 0);
2745 drm_exec_until_all_locked(&exec) {
2746 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2748 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2749 drm_exec_retry_on_contention(&exec);
2751 goto ttm_reserve_fail;
2754 /* Reserve all BOs and page tables/directory. Add all BOs from
2755 * kfd_bo_list to ctx.list
2757 list_for_each_entry(mem, &process_info->kfd_bo_list,
2759 struct drm_gem_object *gobj;
2761 gobj = &mem->bo->tbo.base;
2762 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2763 drm_exec_retry_on_contention(&exec);
2765 goto ttm_reserve_fail;
2769 amdgpu_sync_create(&sync_obj);
2771 /* Validate PDs and PTs */
2772 ret = process_validate_vms(process_info);
2774 goto validate_map_fail;
2776 ret = process_sync_pds_resv(process_info, &sync_obj);
2778 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2779 goto validate_map_fail;
2782 /* Validate BOs and map them to GPUVM (update VM page tables). */
2783 list_for_each_entry(mem, &process_info->kfd_bo_list,
2786 struct amdgpu_bo *bo = mem->bo;
2787 uint32_t domain = mem->domain;
2788 struct kfd_mem_attachment *attachment;
2789 struct dma_resv_iter cursor;
2790 struct dma_fence *fence;
2792 total_size += amdgpu_bo_size(bo);
2794 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2796 pr_debug("Memory eviction: Validate BOs failed\n");
2797 failed_size += amdgpu_bo_size(bo);
2798 ret = amdgpu_amdkfd_bo_validate(bo,
2799 AMDGPU_GEM_DOMAIN_GTT, false);
2801 pr_debug("Memory eviction: Try again\n");
2802 goto validate_map_fail;
2805 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
2806 DMA_RESV_USAGE_KERNEL, fence) {
2807 ret = amdgpu_sync_fence(&sync_obj, fence);
2809 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2810 goto validate_map_fail;
2813 list_for_each_entry(attachment, &mem->attachments, list) {
2814 if (!attachment->is_mapped)
2817 kfd_mem_dmaunmap_attachment(mem, attachment);
2818 ret = update_gpuvm_pte(mem, attachment, &sync_obj);
2820 pr_debug("Memory eviction: update PTE failed. Try again\n");
2821 goto validate_map_fail;
2827 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2829 /* Update page directories */
2830 ret = process_update_pds(process_info, &sync_obj);
2832 pr_debug("Memory eviction: update PDs failed. Try again\n");
2833 goto validate_map_fail;
2836 /* Wait for validate and PT updates to finish */
2837 amdgpu_sync_wait(&sync_obj, false);
2839 /* Release old eviction fence and create new one, because fence only
2840 * goes from unsignaled to signaled, fence cannot be reused.
2841 * Use context and mm from the old fence.
2843 new_fence = amdgpu_amdkfd_fence_create(
2844 process_info->eviction_fence->base.context,
2845 process_info->eviction_fence->mm,
2848 pr_err("Failed to create eviction fence\n");
2850 goto validate_map_fail;
2852 dma_fence_put(&process_info->eviction_fence->base);
2853 process_info->eviction_fence = new_fence;
2854 *ef = dma_fence_get(&new_fence->base);
2856 /* Attach new eviction fence to all BOs except pinned ones */
2857 list_for_each_entry(mem, &process_info->kfd_bo_list, validate_list) {
2858 if (mem->bo->tbo.pin_count)
2861 dma_resv_add_fence(mem->bo->tbo.base.resv,
2862 &process_info->eviction_fence->base,
2863 DMA_RESV_USAGE_BOOKKEEP);
2865 /* Attach eviction fence to PD / PT BOs */
2866 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2868 struct amdgpu_bo *bo = peer_vm->root.bo;
2870 dma_resv_add_fence(bo->tbo.base.resv,
2871 &process_info->eviction_fence->base,
2872 DMA_RESV_USAGE_BOOKKEEP);
2876 amdgpu_sync_free(&sync_obj);
2878 drm_exec_fini(&exec);
2879 mutex_unlock(&process_info->lock);
2883 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
2885 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2886 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
2892 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2896 mutex_init(&(*mem)->lock);
2897 INIT_LIST_HEAD(&(*mem)->attachments);
2898 (*mem)->bo = amdgpu_bo_ref(gws_bo);
2899 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
2900 (*mem)->process_info = process_info;
2901 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
2902 amdgpu_sync_create(&(*mem)->sync);
2905 /* Validate gws bo the first time it is added to process */
2906 mutex_lock(&(*mem)->process_info->lock);
2907 ret = amdgpu_bo_reserve(gws_bo, false);
2908 if (unlikely(ret)) {
2909 pr_err("Reserve gws bo failed %d\n", ret);
2910 goto bo_reservation_failure;
2913 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
2915 pr_err("GWS BO validate failed %d\n", ret);
2916 goto bo_validation_failure;
2918 /* GWS resource is shared b/t amdgpu and amdkfd
2919 * Add process eviction fence to bo so they can
2922 ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
2924 goto reserve_shared_fail;
2925 dma_resv_add_fence(gws_bo->tbo.base.resv,
2926 &process_info->eviction_fence->base,
2927 DMA_RESV_USAGE_BOOKKEEP);
2928 amdgpu_bo_unreserve(gws_bo);
2929 mutex_unlock(&(*mem)->process_info->lock);
2933 reserve_shared_fail:
2934 bo_validation_failure:
2935 amdgpu_bo_unreserve(gws_bo);
2936 bo_reservation_failure:
2937 mutex_unlock(&(*mem)->process_info->lock);
2938 amdgpu_sync_free(&(*mem)->sync);
2939 remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
2940 amdgpu_bo_unref(&gws_bo);
2941 mutex_destroy(&(*mem)->lock);
2947 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
2950 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2951 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
2952 struct amdgpu_bo *gws_bo = kgd_mem->bo;
2954 /* Remove BO from process's validate list so restore worker won't touch
2957 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
2959 ret = amdgpu_bo_reserve(gws_bo, false);
2960 if (unlikely(ret)) {
2961 pr_err("Reserve gws bo failed %d\n", ret);
2962 //TODO add BO back to validate_list?
2965 amdgpu_amdkfd_remove_eviction_fence(gws_bo,
2966 process_info->eviction_fence);
2967 amdgpu_bo_unreserve(gws_bo);
2968 amdgpu_sync_free(&kgd_mem->sync);
2969 amdgpu_bo_unref(&gws_bo);
2970 mutex_destroy(&kgd_mem->lock);
2975 /* Returns GPU-specific tiling mode information */
2976 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
2977 struct tile_config *config)
2979 config->gb_addr_config = adev->gfx.config.gb_addr_config;
2980 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
2981 config->num_tile_configs =
2982 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2983 config->macro_tile_config_ptr =
2984 adev->gfx.config.macrotile_mode_array;
2985 config->num_macro_tile_configs =
2986 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2988 /* Those values are not set from GFX9 onwards */
2989 config->num_banks = adev->gfx.config.num_banks;
2990 config->num_ranks = adev->gfx.config.num_ranks;
2995 bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem)
2997 struct kfd_mem_attachment *entry;
2999 list_for_each_entry(entry, &mem->attachments, list) {
3000 if (entry->is_mapped && entry->adev == adev)
3006 #if defined(CONFIG_DEBUG_FS)
3008 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data)
3011 spin_lock(&kfd_mem_limit.mem_limit_lock);
3012 seq_printf(m, "System mem used %lldM out of %lluM\n",
3013 (kfd_mem_limit.system_mem_used >> 20),
3014 (kfd_mem_limit.max_system_mem_limit >> 20));
3015 seq_printf(m, "TTM mem used %lldM out of %lluM\n",
3016 (kfd_mem_limit.ttm_mem_used >> 20),
3017 (kfd_mem_limit.max_ttm_mem_limit >> 20));
3018 spin_unlock(&kfd_mem_limit.mem_limit_lock);