2 * Copyright (C) 2010, 2012-2013 ARM Limited. All rights reserved.
4 * This program is free software and is provided to you under the terms of the GNU General Public License version 2
5 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
7 * A copy of the licence is included with the program, and can also be obtained from Free Software
8 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
11 #ifndef _MALI200_REGS_H_
12 #define _MALI200_REGS_H_
15 * Enum for management register addresses.
17 enum mali200_mgmt_reg {
18 MALI200_REG_ADDR_MGMT_VERSION = 0x1000,
19 MALI200_REG_ADDR_MGMT_CURRENT_REND_LIST_ADDR = 0x1004,
20 MALI200_REG_ADDR_MGMT_STATUS = 0x1008,
21 MALI200_REG_ADDR_MGMT_CTRL_MGMT = 0x100c,
23 MALI200_REG_ADDR_MGMT_INT_RAWSTAT = 0x1020,
24 MALI200_REG_ADDR_MGMT_INT_CLEAR = 0x1024,
25 MALI200_REG_ADDR_MGMT_INT_MASK = 0x1028,
26 MALI200_REG_ADDR_MGMT_INT_STATUS = 0x102c,
28 MALI200_REG_ADDR_MGMT_WRITE_BOUNDARY_LOW = 0x1044,
30 MALI200_REG_ADDR_MGMT_BUS_ERROR_STATUS = 0x1050,
32 MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE = 0x1080,
33 MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC = 0x1084,
34 MALI200_REG_ADDR_MGMT_PERF_CNT_0_VALUE = 0x108c,
36 MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE = 0x10a0,
37 MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC = 0x10a4,
38 MALI200_REG_ADDR_MGMT_PERF_CNT_1_VALUE = 0x10ac,
40 MALI200_REG_ADDR_MGMT_PERFMON_CONTR = 0x10b0,
41 MALI200_REG_ADDR_MGMT_PERFMON_BASE = 0x10b4,
43 MALI200_REG_SIZEOF_REGISTER_BANK = 0x10f0
47 #define MALI200_REG_VAL_PERF_CNT_ENABLE 1
49 enum mali200_mgmt_ctrl_mgmt {
50 MALI200_REG_VAL_CTRL_MGMT_STOP_BUS = (1<<0),
51 MALI200_REG_VAL_CTRL_MGMT_FLUSH_CACHES = (1<<3),
52 MALI200_REG_VAL_CTRL_MGMT_FORCE_RESET = (1<<5),
53 MALI200_REG_VAL_CTRL_MGMT_START_RENDERING = (1<<6),
54 MALI400PP_REG_VAL_CTRL_MGMT_SOFT_RESET = (1<<7), /* Only valid for Mali-300 and later */
57 enum mali200_mgmt_irq {
58 MALI200_REG_VAL_IRQ_END_OF_FRAME = (1<<0),
59 MALI200_REG_VAL_IRQ_END_OF_TILE = (1<<1),
60 MALI200_REG_VAL_IRQ_HANG = (1<<2),
61 MALI200_REG_VAL_IRQ_FORCE_HANG = (1<<3),
62 MALI200_REG_VAL_IRQ_BUS_ERROR = (1<<4),
63 MALI200_REG_VAL_IRQ_BUS_STOP = (1<<5),
64 MALI200_REG_VAL_IRQ_CNT_0_LIMIT = (1<<6),
65 MALI200_REG_VAL_IRQ_CNT_1_LIMIT = (1<<7),
66 MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR = (1<<8),
67 MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND = (1<<9),
68 MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW = (1<<10),
69 MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW = (1<<11),
70 MALI400PP_REG_VAL_IRQ_RESET_COMPLETED = (1<<12),
73 #define MALI200_REG_VAL_IRQ_MASK_ALL ((enum mali200_mgmt_irq) (\
74 MALI200_REG_VAL_IRQ_END_OF_FRAME |\
75 MALI200_REG_VAL_IRQ_END_OF_TILE |\
76 MALI200_REG_VAL_IRQ_HANG |\
77 MALI200_REG_VAL_IRQ_FORCE_HANG |\
78 MALI200_REG_VAL_IRQ_BUS_ERROR |\
79 MALI200_REG_VAL_IRQ_BUS_STOP |\
80 MALI200_REG_VAL_IRQ_CNT_0_LIMIT |\
81 MALI200_REG_VAL_IRQ_CNT_1_LIMIT |\
82 MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR |\
83 MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND |\
84 MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW |\
85 MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW |\
86 MALI400PP_REG_VAL_IRQ_RESET_COMPLETED))
88 #define MALI200_REG_VAL_IRQ_MASK_USED ((enum mali200_mgmt_irq) (\
89 MALI200_REG_VAL_IRQ_END_OF_FRAME |\
90 MALI200_REG_VAL_IRQ_FORCE_HANG |\
91 MALI200_REG_VAL_IRQ_BUS_ERROR |\
92 MALI200_REG_VAL_IRQ_WRITE_BOUNDARY_ERROR |\
93 MALI400PP_REG_VAL_IRQ_INVALID_PLIST_COMMAND |\
94 MALI400PP_REG_VAL_IRQ_CALL_STACK_UNDERFLOW |\
95 MALI400PP_REG_VAL_IRQ_CALL_STACK_OVERFLOW))
97 #define MALI200_REG_VAL_IRQ_MASK_NONE ((enum mali200_mgmt_irq)(0))
99 enum mali200_mgmt_status {
100 MALI200_REG_VAL_STATUS_RENDERING_ACTIVE = (1<<0),
101 MALI200_REG_VAL_STATUS_BUS_STOPPED = (1<<4),
104 enum mali200_render_unit {
105 MALI200_REG_ADDR_FRAME = 0x0000,
106 MALI200_REG_ADDR_RSW = 0x0004,
107 MALI200_REG_ADDR_STACK = 0x0030,
108 MALI200_REG_ADDR_STACK_SIZE = 0x0034,
109 MALI200_REG_ADDR_ORIGIN_OFFSET_X = 0x0040
112 enum mali200_wb_unit {
113 MALI200_REG_ADDR_WB0 = 0x0100,
114 MALI200_REG_ADDR_WB1 = 0x0200,
115 MALI200_REG_ADDR_WB2 = 0x0300
118 enum mali200_wb_unit_regs {
119 MALI200_REG_ADDR_WB_SOURCE_SELECT = 0x0000,
120 MALI200_REG_ADDR_WB_SOURCE_ADDR = 0x0004,
123 /* This should be in the top 16 bit of the version register of Mali PP */
124 #define MALI200_PP_PRODUCT_ID 0xC807
125 #define MALI300_PP_PRODUCT_ID 0xCE07
126 #define MALI400_PP_PRODUCT_ID 0xCD07
127 #define MALI450_PP_PRODUCT_ID 0xCF07
130 #endif /* _MALI200_REGS_H_ */