2 * Copyright (C) 2012 ARM Limited. All rights reserved.
4 * This program is free software and is provided to you under the terms of the GNU General Public License version 2
5 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
7 * A copy of the licence is included with the program, and can also be obtained from Free Software
8 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
13 * Defines types and interface exposed by the Mali Utgard device driver
16 #ifndef __MALI_UTGARD_H__
17 #define __MALI_UTGARD_H__
19 #include "mali_osk_types.h"
21 #define MALI_GPU_NAME_UTGARD "mali-utgard"
25 #define MALI_GPU_RESOURCES_MALI200(base_addr, gp_irq, pp_irq, mmu_irq) \
26 MALI_GPU_RESOURCE_PP(base_addr + 0x0000, pp_irq) \
27 MALI_GPU_RESOURCE_GP(base_addr + 0x2000, gp_irq) \
28 MALI_GPU_RESOURCE_MMU(base_addr + 0x3000, mmu_irq)
32 #define MALI_GPU_RESOURCES_MALI300(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \
33 MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq)
35 #define MALI_GPU_RESOURCES_MALI300_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \
36 MALI_GPU_RESOURCES_MALI400_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq)
40 #define MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
41 MALI_GPU_RESOURCE_L2(base_addr + 0x1000) \
42 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x0000, gp_irq, base_addr + 0x3000, gp_mmu_irq) \
43 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x8000, pp0_irq, base_addr + 0x4000, pp0_mmu_irq)
45 #define MALI_GPU_RESOURCES_MALI400_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
46 MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
47 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000)
49 #define MALI_GPU_RESOURCES_MALI400_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
50 MALI_GPU_RESOURCE_L2(base_addr + 0x1000) \
51 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x0000, gp_irq, base_addr + 0x3000, gp_mmu_irq) \
52 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x8000, pp0_irq, base_addr + 0x4000, pp0_mmu_irq) \
53 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0xA000, pp1_irq, base_addr + 0x5000, pp1_mmu_irq)
55 #define MALI_GPU_RESOURCES_MALI400_MP2_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
56 MALI_GPU_RESOURCES_MALI400_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
57 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000)
59 #define MALI_GPU_RESOURCES_MALI400_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
60 MALI_GPU_RESOURCE_L2(base_addr + 0x1000) \
61 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x0000, gp_irq, base_addr + 0x3000, gp_mmu_irq) \
62 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x8000, pp0_irq, base_addr + 0x4000, pp0_mmu_irq) \
63 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0xA000, pp1_irq, base_addr + 0x5000, pp1_mmu_irq) \
64 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0xC000, pp2_irq, base_addr + 0x6000, pp2_mmu_irq)
66 #define MALI_GPU_RESOURCES_MALI400_MP3_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
67 MALI_GPU_RESOURCES_MALI400_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
68 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000)
70 #define MALI_GPU_RESOURCES_MALI400_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
71 MALI_GPU_RESOURCE_L2(base_addr + 0x1000) \
72 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x0000, gp_irq, base_addr + 0x3000, gp_mmu_irq) \
73 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x8000, pp0_irq, base_addr + 0x4000, pp0_mmu_irq) \
74 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0xA000, pp1_irq, base_addr + 0x5000, pp1_mmu_irq) \
75 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0xC000, pp2_irq, base_addr + 0x6000, pp2_mmu_irq) \
76 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + 0xE000, pp3_irq, base_addr + 0x7000, pp3_mmu_irq)
78 #define MALI_GPU_RESOURCES_MALI400_MP4_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
79 MALI_GPU_RESOURCES_MALI400_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
80 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000)
83 #define MALI_GPU_RESOURCES_MALI450_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
84 MALI_GPU_RESOURCE_L2(base_addr + 0x10000) \
85 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x00000, gp_irq, base_addr + 0x03000, gp_mmu_irq) \
86 MALI_GPU_RESOURCE_L2(base_addr + 0x01000) \
87 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x08000, pp0_irq, base_addr + 0x04000, pp0_mmu_irq) \
88 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0x0A000, pp1_irq, base_addr + 0x05000, pp1_mmu_irq) \
89 MALI_GPU_RESOURCE_BCAST(base_addr + 0x13000) \
90 MALI_GPU_RESOURCE_DLBU(base_addr + 0x14000) \
91 MALI_GPU_RESOURCE_PP_BCAST(base_addr + 0x16000, pp_bcast_irq) \
92 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + 0x15000) \
93 MALI_GPU_RESOURCE_DMA(base_addr + 0x12000)
95 #define MALI_GPU_RESOURCES_MALI450_MP2_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
96 MALI_GPU_RESOURCES_MALI450_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
97 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000) \
99 #define MALI_GPU_RESOURCES_MALI450_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
100 MALI_GPU_RESOURCE_L2(base_addr + 0x10000) \
101 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x00000, gp_irq, base_addr + 0x03000, gp_mmu_irq) \
102 MALI_GPU_RESOURCE_L2(base_addr + 0x01000) \
103 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x08000, pp0_irq, base_addr + 0x04000, pp0_mmu_irq) \
104 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0x0A000, pp1_irq, base_addr + 0x05000, pp1_mmu_irq) \
105 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0x0C000, pp2_irq, base_addr + 0x06000, pp2_mmu_irq) \
106 MALI_GPU_RESOURCE_BCAST(base_addr + 0x13000) \
107 MALI_GPU_RESOURCE_DLBU(base_addr + 0x14000) \
108 MALI_GPU_RESOURCE_PP_BCAST(base_addr + 0x16000, pp_bcast_irq) \
109 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + 0x15000)
111 #define MALI_GPU_RESOURCES_MALI450_MP3_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
112 MALI_GPU_RESOURCES_MALI450_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \
113 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000) \
115 #define MALI_GPU_RESOURCES_MALI450_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
116 MALI_GPU_RESOURCE_L2(base_addr + 0x10000) \
117 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x00000, gp_irq, base_addr + 0x03000, gp_mmu_irq) \
118 MALI_GPU_RESOURCE_L2(base_addr + 0x01000) \
119 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x08000, pp0_irq, base_addr + 0x04000, pp0_mmu_irq) \
120 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0x0A000, pp1_irq, base_addr + 0x05000, pp1_mmu_irq) \
121 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0x0C000, pp2_irq, base_addr + 0x06000, pp2_mmu_irq) \
122 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + 0x0E000, pp3_irq, base_addr + 0x07000, pp3_mmu_irq) \
123 MALI_GPU_RESOURCE_BCAST(base_addr + 0x13000) \
124 MALI_GPU_RESOURCE_DLBU(base_addr + 0x14000) \
125 MALI_GPU_RESOURCE_PP_BCAST(base_addr + 0x16000, pp_bcast_irq) \
126 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + 0x15000) \
127 MALI_GPU_RESOURCE_DMA(base_addr + 0x12000)
129 #define MALI_GPU_RESOURCES_MALI450_MP4_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
130 MALI_GPU_RESOURCES_MALI450_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
131 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000) \
133 #define MALI_GPU_RESOURCES_MALI450_MP6(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
134 MALI_GPU_RESOURCE_L2(base_addr + 0x10000) \
135 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x00000, gp_irq, base_addr + 0x03000, gp_mmu_irq) \
136 MALI_GPU_RESOURCE_L2(base_addr + 0x01000) \
137 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x08000, pp0_irq, base_addr + 0x04000, pp0_mmu_irq) \
138 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0x0A000, pp1_irq, base_addr + 0x05000, pp1_mmu_irq) \
139 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0x0C000, pp2_irq, base_addr + 0x06000, pp2_mmu_irq) \
140 MALI_GPU_RESOURCE_L2(base_addr + 0x11000) \
141 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + 0x28000, pp3_irq, base_addr + 0x1C000, pp3_mmu_irq) \
142 MALI_GPU_RESOURCE_PP_WITH_MMU(4, base_addr + 0x2A000, pp4_irq, base_addr + 0x1D000, pp4_mmu_irq) \
143 MALI_GPU_RESOURCE_PP_WITH_MMU(5, base_addr + 0x2C000, pp5_irq, base_addr + 0x1E000, pp5_mmu_irq) \
144 MALI_GPU_RESOURCE_BCAST(base_addr + 0x13000) \
145 MALI_GPU_RESOURCE_DLBU(base_addr + 0x14000) \
146 MALI_GPU_RESOURCE_PP_BCAST(base_addr + 0x16000, pp_bcast_irq) \
147 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + 0x15000) \
148 MALI_GPU_RESOURCE_DMA(base_addr + 0x12000)
150 #define MALI_GPU_RESOURCES_MALI450_MP6_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
151 MALI_GPU_RESOURCES_MALI450_MP6(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
152 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000) \
154 #define MALI_GPU_RESOURCES_MALI450_MP8(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
155 MALI_GPU_RESOURCE_L2(base_addr + 0x10000) \
156 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x00000, gp_irq, base_addr + 0x03000, gp_mmu_irq) \
157 MALI_GPU_RESOURCE_L2(base_addr + 0x01000) \
158 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x08000, pp0_irq, base_addr + 0x04000, pp0_mmu_irq) \
159 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0x0A000, pp1_irq, base_addr + 0x05000, pp1_mmu_irq) \
160 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0x0C000, pp2_irq, base_addr + 0x06000, pp2_mmu_irq) \
161 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + 0x0E000, pp3_irq, base_addr + 0x07000, pp3_mmu_irq) \
162 MALI_GPU_RESOURCE_L2(base_addr + 0x11000) \
163 MALI_GPU_RESOURCE_PP_WITH_MMU(4, base_addr + 0x28000, pp4_irq, base_addr + 0x1C000, pp4_mmu_irq) \
164 MALI_GPU_RESOURCE_PP_WITH_MMU(5, base_addr + 0x2A000, pp5_irq, base_addr + 0x1D000, pp5_mmu_irq) \
165 MALI_GPU_RESOURCE_PP_WITH_MMU(6, base_addr + 0x2C000, pp6_irq, base_addr + 0x1E000, pp6_mmu_irq) \
166 MALI_GPU_RESOURCE_PP_WITH_MMU(7, base_addr + 0x2E000, pp7_irq, base_addr + 0x1F000, pp7_mmu_irq) \
167 MALI_GPU_RESOURCE_BCAST(base_addr + 0x13000) \
168 MALI_GPU_RESOURCE_DLBU(base_addr + 0x14000) \
169 MALI_GPU_RESOURCE_PP_BCAST(base_addr + 0x16000, pp_bcast_irq) \
170 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + 0x15000) \
171 MALI_GPU_RESOURCE_DMA(base_addr + 0x12000)
173 #define MALI_GPU_RESOURCES_MALI450_MP8_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
174 MALI_GPU_RESOURCES_MALI450_MP8(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
175 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000) \
177 #define MALI_GPU_RESOURCE_L2(addr) \
180 .flags = IORESOURCE_MEM, \
182 .end = addr + 0x200, \
185 #define MALI_GPU_RESOURCE_GP(gp_addr, gp_irq) \
188 .flags = IORESOURCE_MEM, \
190 .end = gp_addr + 0x100, \
193 .name = "Mali_GP_IRQ", \
194 .flags = IORESOURCE_IRQ, \
199 #define MALI_GPU_RESOURCE_GP_WITH_MMU(gp_addr, gp_irq, gp_mmu_addr, gp_mmu_irq) \
202 .flags = IORESOURCE_MEM, \
204 .end = gp_addr + 0x100, \
207 .name = "Mali_GP_IRQ", \
208 .flags = IORESOURCE_IRQ, \
213 .name = "Mali_GP_MMU", \
214 .flags = IORESOURCE_MEM, \
215 .start = gp_mmu_addr, \
216 .end = gp_mmu_addr + 0x100, \
219 .name = "Mali_GP_MMU_IRQ", \
220 .flags = IORESOURCE_IRQ, \
221 .start = gp_mmu_irq, \
225 #define MALI_GPU_RESOURCE_PP(pp_addr, pp_irq) \
228 .flags = IORESOURCE_MEM, \
230 .end = pp_addr + 0x1100, \
233 .name = "Mali_PP_IRQ", \
234 .flags = IORESOURCE_IRQ, \
239 #define MALI_GPU_RESOURCE_PP_WITH_MMU(id, pp_addr, pp_irq, pp_mmu_addr, pp_mmu_irq) \
241 .name = "Mali_PP" #id, \
242 .flags = IORESOURCE_MEM, \
244 .end = pp_addr + 0x1100, \
247 .name = "Mali_PP" #id "_IRQ", \
248 .flags = IORESOURCE_IRQ, \
253 .name = "Mali_PP" #id "_MMU", \
254 .flags = IORESOURCE_MEM, \
255 .start = pp_mmu_addr, \
256 .end = pp_mmu_addr + 0x100, \
259 .name = "Mali_PP" #id "_MMU_IRQ", \
260 .flags = IORESOURCE_IRQ, \
261 .start = pp_mmu_irq, \
265 #define MALI_GPU_RESOURCE_MMU(mmu_addr, mmu_irq) \
267 .name = "Mali_MMU", \
268 .flags = IORESOURCE_MEM, \
270 .end = mmu_addr + 0x100, \
273 .name = "Mali_MMU_IRQ", \
274 .flags = IORESOURCE_IRQ, \
279 #define MALI_GPU_RESOURCE_PMU(pmu_addr) \
281 .name = "Mali_PMU", \
282 .flags = IORESOURCE_MEM, \
284 .end = pmu_addr + 0x100, \
287 #define MALI_GPU_RESOURCE_DMA(dma_addr) \
289 .name = "Mali_DMA", \
290 .flags = IORESOURCE_MEM, \
292 .end = dma_addr + 0x100, \
295 #define MALI_GPU_RESOURCE_DLBU(dlbu_addr) \
297 .name = "Mali_DLBU", \
298 .flags = IORESOURCE_MEM, \
299 .start = dlbu_addr, \
300 .end = dlbu_addr + 0x100, \
303 #define MALI_GPU_RESOURCE_BCAST(bcast_addr) \
305 .name = "Mali_Broadcast", \
306 .flags = IORESOURCE_MEM, \
307 .start = bcast_addr, \
308 .end = bcast_addr + 0x100, \
311 #define MALI_GPU_RESOURCE_PP_BCAST(pp_addr, pp_irq) \
313 .name = "Mali_PP_Broadcast", \
314 .flags = IORESOURCE_MEM, \
316 .end = pp_addr + 0x1100, \
319 .name = "Mali_PP_Broadcast_IRQ", \
320 .flags = IORESOURCE_IRQ, \
325 #define MALI_GPU_RESOURCE_PP_MMU_BCAST(pp_mmu_bcast_addr) \
327 .name = "Mali_PP_MMU_Broadcast", \
328 .flags = IORESOURCE_MEM, \
329 .start = pp_mmu_bcast_addr, \
330 .end = pp_mmu_bcast_addr + 0x100, \
333 struct mali_gpu_utilization_data {
334 unsigned int utilization_gpu; /* Utilization for GP and all PP cores combined, 0 = no utilization, 256 = full utilization */
335 unsigned int utilization_gp; /* Utilization for GP core only, 0 = no utilization, 256 = full utilization */
336 unsigned int utilization_pp; /* Utilization for all PP cores combined, 0 = no utilization, 256 = full utilization */
337 #if defined(CONFIG_MALI400_POWER_PERFORMANCE_POLICY)
338 unsigned int number_of_window_jobs;
339 unsigned int number_of_window_jobs_under_pressure;
343 struct mali_gpu_device_data {
344 /* Dedicated GPU memory range (physical). */
345 unsigned long dedicated_mem_start;
346 unsigned long dedicated_mem_size;
348 /* Shared GPU memory */
349 unsigned long shared_mem_size;
351 /* Frame buffer memory to be accessible by Mali GPU (physical) */
352 unsigned long fb_start;
353 unsigned long fb_size;
355 /* Max runtime [ms] for jobs */
358 /* Report GPU utilization in this interval (specified in ms) */
359 unsigned long utilization_interval;
361 /* Function that will receive periodic GPU utilization numbers */
362 void (*utilization_callback)(struct mali_gpu_utilization_data *data);
365 * Mali PMU switch delay.
366 * Only needed if the power gates are connected to the PMU in a high fanout
367 * network. This value is the number of Mali clock cycles it takes to
368 * enable the power gates and turn on the power mesh.
369 * This value will have no effect if a daisy chain implementation is used.
371 u32 pmu_switch_delay;
374 /* Mali Dynamic power domain configuration in sequence from 0-11
375 * GP PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7, L2$0 L2$1 L2$2
377 u16 pmu_domain_config[12];
379 /* Fuction that platform callback for freq tunning, needed when POWER_PERFORMANCE_POLICY enabled*/
380 int (*set_freq_callback)(unsigned int mhz);
383 /** @brief MALI GPU power down using MALI in-built PMU
385 * called to power down all cores
387 int mali_pmu_powerdown(void);
390 /** @brief MALI GPU power up using MALI in-built PMU
392 * called to power up all cores
394 int mali_pmu_powerup(void);
397 * Pause the scheduling and power state changes of Mali device driver.
398 * mali_dev_resume() must always be called as soon as possible after this function
399 * in order to resume normal operation of the Mali driver.
401 void mali_dev_pause(void);
404 * Resume scheduling and allow power changes in Mali device driver.
405 * This must always be called after mali_dev_pause().
407 void mali_dev_resume(void);
409 /** @brief Set the desired number of PP cores to use.
411 * The internal Mali PMU will be used, if present, to physically power off the PP cores.
413 * @param num_cores The number of desired cores
414 * @return 0 on success, otherwise error. -EINVAL means an invalid number of cores was specified.
416 int mali_perf_set_num_pp_cores(unsigned int num_cores);