2 * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
4 * This program is free software and is provided to you under the terms of the GNU General Public License version 2
5 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
7 * A copy of the licence is included with the program, and can also be obtained from Free Software
8 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
13 * Mali driver functions for Mali 400 PMU hardware
15 #include "mali_hw_core.h"
18 #include "mali_kernel_common.h"
21 #include "mali_osk_mali.h"
23 u16 mali_pmu_global_domain_config[MALI_MAX_NUMBER_OF_DOMAINS]= {0};
25 static u32 mali_pmu_detect_mask(void);
27 /** @brief MALI inbuilt PMU hardware info and PMU hardware has knowledge of cores power mask
29 struct mali_pmu_core {
30 struct mali_hw_core hw_core;
31 _mali_osk_spinlock_t *lock;
32 u32 registered_cores_mask;
33 u32 active_cores_mask;
37 static struct mali_pmu_core *mali_global_pmu_core = NULL;
39 /** @brief Register layout for hardware PMU
42 PMU_REG_ADDR_MGMT_POWER_UP = 0x00, /*< Power up register */
43 PMU_REG_ADDR_MGMT_POWER_DOWN = 0x04, /*< Power down register */
44 PMU_REG_ADDR_MGMT_STATUS = 0x08, /*< Core sleep status register */
45 PMU_REG_ADDR_MGMT_INT_MASK = 0x0C, /*< Interrupt mask register */
46 PMU_REG_ADDR_MGMT_INT_RAWSTAT = 0x10, /*< Interrupt raw status register */
47 PMU_REG_ADDR_MGMT_INT_CLEAR = 0x18, /*< Interrupt clear register */
48 PMU_REG_ADDR_MGMT_SW_DELAY = 0x1C, /*< Switch delay register */
49 PMU_REGISTER_ADDRESS_SPACE_SIZE = 0x28, /*< Size of register space */
50 } pmu_reg_addr_mgmt_addr;
52 #define PMU_REG_VAL_IRQ 1
54 struct mali_pmu_core *mali_pmu_create(_mali_osk_resource_t *resource)
56 struct mali_pmu_core* pmu;
58 MALI_DEBUG_ASSERT(NULL == mali_global_pmu_core);
59 MALI_DEBUG_PRINT(2, ("Mali PMU: Creating Mali PMU core\n"));
61 pmu = (struct mali_pmu_core *)_mali_osk_malloc(sizeof(struct mali_pmu_core));
63 pmu->lock = _mali_osk_spinlock_init(_MALI_OSK_LOCKFLAG_ORDERED, _MALI_OSK_LOCK_ORDER_PMU);
64 if (NULL != pmu->lock) {
65 pmu->registered_cores_mask = mali_pmu_detect_mask();
66 pmu->active_cores_mask = pmu->registered_cores_mask;
68 if (_MALI_OSK_ERR_OK == mali_hw_core_create(&pmu->hw_core, resource, PMU_REGISTER_ADDRESS_SPACE_SIZE)) {
69 _mali_osk_errcode_t err;
70 struct _mali_osk_device_data data = { 0, };
72 err = _mali_osk_device_data_get(&data);
73 if (_MALI_OSK_ERR_OK == err) {
74 pmu->switch_delay = data.pmu_switch_delay;
75 mali_global_pmu_core = pmu;
78 mali_hw_core_delete(&pmu->hw_core);
80 _mali_osk_spinlock_term(pmu->lock);
88 void mali_pmu_delete(struct mali_pmu_core *pmu)
90 MALI_DEBUG_ASSERT_POINTER(pmu);
91 MALI_DEBUG_ASSERT(pmu == mali_global_pmu_core);
92 MALI_DEBUG_PRINT(2, ("Mali PMU: Deleting Mali PMU core\n"));
94 _mali_osk_spinlock_term(pmu->lock);
95 mali_hw_core_delete(&pmu->hw_core);
97 mali_global_pmu_core = NULL;
100 static void mali_pmu_lock(struct mali_pmu_core *pmu)
102 _mali_osk_spinlock_lock(pmu->lock);
104 static void mali_pmu_unlock(struct mali_pmu_core *pmu)
106 _mali_osk_spinlock_unlock(pmu->lock);
109 static _mali_osk_errcode_t mali_pmu_wait_for_command_finish(struct mali_pmu_core *pmu)
112 u32 timeout = MALI_REG_POLL_COUNT_SLOW;
114 MALI_DEBUG_ASSERT(pmu);
116 /* Wait for the command to complete */
118 rawstat = mali_hw_core_register_read(&pmu->hw_core, PMU_REG_ADDR_MGMT_INT_RAWSTAT);
120 } while (0 == (rawstat & PMU_REG_VAL_IRQ) && 0 < timeout);
122 MALI_DEBUG_ASSERT(0 < timeout);
124 return _MALI_OSK_ERR_TIMEOUT;
127 mali_hw_core_register_write(&pmu->hw_core, PMU_REG_ADDR_MGMT_INT_CLEAR, PMU_REG_VAL_IRQ);
129 return _MALI_OSK_ERR_OK;
132 static _mali_osk_errcode_t mali_pmu_power_up_internal(struct mali_pmu_core *pmu, const u32 mask)
135 _mali_osk_errcode_t err;
136 #if !defined(CONFIG_MALI_PMU_PARALLEL_POWER_UP)
140 MALI_DEBUG_ASSERT_POINTER(pmu);
141 MALI_DEBUG_ASSERT(0 == (mali_hw_core_register_read(&pmu->hw_core, PMU_REG_ADDR_MGMT_INT_RAWSTAT)
144 stat = mali_hw_core_register_read(&pmu->hw_core, PMU_REG_ADDR_MGMT_STATUS);
145 stat &= pmu->registered_cores_mask;
146 if (0 == mask || 0 == (stat & mask)) return _MALI_OSK_ERR_OK;
148 #if defined(CONFIG_MALI_PMU_PARALLEL_POWER_UP)
149 mali_hw_core_register_write(&pmu->hw_core, PMU_REG_ADDR_MGMT_POWER_UP, mask);
151 err = mali_pmu_wait_for_command_finish(pmu);
152 if (_MALI_OSK_ERR_OK != err) {
156 for (current_domain = 1; current_domain <= pmu->registered_cores_mask; current_domain <<= 1) {
157 if (current_domain & mask & stat) {
158 mali_hw_core_register_write(&pmu->hw_core, PMU_REG_ADDR_MGMT_POWER_UP, current_domain);
160 err = mali_pmu_wait_for_command_finish(pmu);
161 if (_MALI_OSK_ERR_OK != err) {
169 /* Get power status of cores */
170 stat = mali_hw_core_register_read(&pmu->hw_core, PMU_REG_ADDR_MGMT_STATUS);
171 stat &= pmu->registered_cores_mask;
173 MALI_DEBUG_ASSERT(0 == (stat & mask));
174 MALI_DEBUG_ASSERT(0 == (stat & pmu->active_cores_mask));
175 #endif /* defined(DEBUG) */
177 return _MALI_OSK_ERR_OK;
180 static _mali_osk_errcode_t mali_pmu_power_down_internal(struct mali_pmu_core *pmu, const u32 mask)
183 _mali_osk_errcode_t err;
185 MALI_DEBUG_ASSERT_POINTER(pmu);
186 MALI_DEBUG_ASSERT(0 == (mali_hw_core_register_read(&pmu->hw_core, PMU_REG_ADDR_MGMT_INT_RAWSTAT)
189 stat = mali_hw_core_register_read(&pmu->hw_core, PMU_REG_ADDR_MGMT_STATUS);
190 stat &= pmu->registered_cores_mask;
192 if (0 == mask || 0 == ((~stat) & mask)) return _MALI_OSK_ERR_OK;
194 mali_hw_core_register_write(&pmu->hw_core, PMU_REG_ADDR_MGMT_POWER_DOWN, mask);
196 /* Do not wait for interrupt on Mali-300/400 if all domains are powered off
197 * by our power down command, because the HW will simply not generate an
198 * interrupt in this case.*/
199 if (mali_is_mali450() || pmu->registered_cores_mask != (mask | stat)) {
200 err = mali_pmu_wait_for_command_finish(pmu);
201 if (_MALI_OSK_ERR_OK != err) {
205 mali_hw_core_register_write(&pmu->hw_core, PMU_REG_ADDR_MGMT_INT_CLEAR, PMU_REG_VAL_IRQ);
208 /* Get power status of cores */
209 stat = mali_hw_core_register_read(&pmu->hw_core, PMU_REG_ADDR_MGMT_STATUS);
210 stat &= pmu->registered_cores_mask;
212 MALI_DEBUG_ASSERT(mask == (stat & mask));
215 return _MALI_OSK_ERR_OK;
218 _mali_osk_errcode_t mali_pmu_reset(struct mali_pmu_core *pmu)
220 _mali_osk_errcode_t err;
221 u32 cores_off_mask, cores_on_mask, stat;
225 /* Setup the desired defaults */
226 mali_hw_core_register_write_relaxed(&pmu->hw_core, PMU_REG_ADDR_MGMT_INT_MASK, 0);
227 mali_hw_core_register_write_relaxed(&pmu->hw_core, PMU_REG_ADDR_MGMT_SW_DELAY, pmu->switch_delay);
229 /* Get power status of cores */
230 stat = mali_hw_core_register_read(&pmu->hw_core, PMU_REG_ADDR_MGMT_STATUS);
232 cores_off_mask = pmu->registered_cores_mask & ~(stat | pmu->active_cores_mask);
233 cores_on_mask = pmu->registered_cores_mask & (stat & pmu->active_cores_mask);
235 if (0 != cores_off_mask) {
236 err = mali_pmu_power_down_internal(pmu, cores_off_mask);
237 if (_MALI_OSK_ERR_OK != err) return err;
240 if (0 != cores_on_mask) {
241 err = mali_pmu_power_up_internal(pmu, cores_on_mask);
242 if (_MALI_OSK_ERR_OK != err) return err;
247 stat = mali_hw_core_register_read(&pmu->hw_core, PMU_REG_ADDR_MGMT_STATUS);
248 stat &= pmu->registered_cores_mask;
250 MALI_DEBUG_ASSERT(stat == (pmu->registered_cores_mask & ~pmu->active_cores_mask));
252 #endif /* defined(DEBUG) */
254 mali_pmu_unlock(pmu);
256 return _MALI_OSK_ERR_OK;
259 _mali_osk_errcode_t mali_pmu_power_down(struct mali_pmu_core *pmu, u32 mask)
261 _mali_osk_errcode_t err;
263 MALI_DEBUG_ASSERT_POINTER(pmu);
264 MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0 );
266 /* Make sure we have a valid power domain mask */
267 if (mask > pmu->registered_cores_mask) {
268 return _MALI_OSK_ERR_INVALID_ARGS;
273 MALI_DEBUG_PRINT(4, ("Mali PMU: Power down (0x%08X)\n", mask));
275 pmu->active_cores_mask &= ~mask;
277 _mali_osk_pm_dev_ref_add_no_power_on();
278 if (!mali_pm_is_power_on()) {
279 /* Don't touch hardware if all of Mali is powered off. */
280 _mali_osk_pm_dev_ref_dec_no_power_on();
281 mali_pmu_unlock(pmu);
283 MALI_DEBUG_PRINT(4, ("Mali PMU: Skipping power down (0x%08X) since Mali is off\n", mask));
285 return _MALI_OSK_ERR_BUSY;
288 err = mali_pmu_power_down_internal(pmu, mask);
290 _mali_osk_pm_dev_ref_dec_no_power_on();
291 mali_pmu_unlock(pmu);
296 _mali_osk_errcode_t mali_pmu_power_up(struct mali_pmu_core *pmu, u32 mask)
298 _mali_osk_errcode_t err;
300 MALI_DEBUG_ASSERT_POINTER(pmu);
301 MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0 );
303 /* Make sure we have a valid power domain mask */
304 if (mask & ~pmu->registered_cores_mask) {
305 return _MALI_OSK_ERR_INVALID_ARGS;
310 MALI_DEBUG_PRINT(4, ("Mali PMU: Power up (0x%08X)\n", mask));
312 pmu->active_cores_mask |= mask;
314 _mali_osk_pm_dev_ref_add_no_power_on();
315 if (!mali_pm_is_power_on()) {
316 /* Don't touch hardware if all of Mali is powered off. */
317 _mali_osk_pm_dev_ref_dec_no_power_on();
318 mali_pmu_unlock(pmu);
320 MALI_DEBUG_PRINT(4, ("Mali PMU: Skipping power up (0x%08X) since Mali is off\n", mask));
322 return _MALI_OSK_ERR_BUSY;
325 err = mali_pmu_power_up_internal(pmu, mask);
327 _mali_osk_pm_dev_ref_dec_no_power_on();
328 mali_pmu_unlock(pmu);
333 _mali_osk_errcode_t mali_pmu_power_down_all(struct mali_pmu_core *pmu)
335 _mali_osk_errcode_t err;
337 MALI_DEBUG_ASSERT_POINTER(pmu);
338 MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0);
342 /* Setup the desired defaults in case we were called before mali_pmu_reset() */
343 mali_hw_core_register_write_relaxed(&pmu->hw_core, PMU_REG_ADDR_MGMT_INT_MASK, 0);
344 mali_hw_core_register_write_relaxed(&pmu->hw_core, PMU_REG_ADDR_MGMT_SW_DELAY, pmu->switch_delay);
346 err = mali_pmu_power_down_internal(pmu, pmu->registered_cores_mask);
348 mali_pmu_unlock(pmu);
353 _mali_osk_errcode_t mali_pmu_power_up_all(struct mali_pmu_core *pmu)
355 _mali_osk_errcode_t err;
357 MALI_DEBUG_ASSERT_POINTER(pmu);
358 MALI_DEBUG_ASSERT(pmu->registered_cores_mask != 0);
362 /* Setup the desired defaults in case we were called before mali_pmu_reset() */
363 mali_hw_core_register_write_relaxed(&pmu->hw_core, PMU_REG_ADDR_MGMT_INT_MASK, 0);
364 mali_hw_core_register_write_relaxed(&pmu->hw_core, PMU_REG_ADDR_MGMT_SW_DELAY, pmu->switch_delay);
366 err = mali_pmu_power_up_internal(pmu, pmu->active_cores_mask);
368 mali_pmu_unlock(pmu);
372 struct mali_pmu_core *mali_pmu_get_global_pmu_core(void)
374 return mali_global_pmu_core;
377 static u32 mali_pmu_detect_mask(void)
379 int dynamic_config_pp = 0;
380 int dynamic_config_l2 = 0;
384 /* Check if PM domain compatible with actually pp core and l2 cache and collection info about domain */
385 mask = mali_pmu_get_domain_mask(MALI_GP_DOMAIN_INDEX);
387 for (i = MALI_PP0_DOMAIN_INDEX; i <= MALI_PP7_DOMAIN_INDEX; i++) {
388 mask |= mali_pmu_get_domain_mask(i);
390 if (0x0 != mali_pmu_get_domain_mask(i)) {
395 for (i = MALI_L20_DOMAIN_INDEX; i <= MALI_L22_DOMAIN_INDEX; i++) {
396 mask |= mali_pmu_get_domain_mask(i);
398 if (0x0 != mali_pmu_get_domain_mask(i)) {
403 MALI_DEBUG_PRINT(2, ("Mali PMU: mask 0x%x, pp_core %d, l2_core %d \n", mask, dynamic_config_pp, dynamic_config_l2));