2 * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
4 * This program is free software and is provided to you under the terms of the GNU General Public License version 2
5 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
7 * A copy of the licence is included with the program, and can also be obtained from Free Software
8 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
11 #ifndef __MALI_KERNEL_L2_CACHE_H__
12 #define __MALI_KERNEL_L2_CACHE_H__
15 #include "mali_hw_core.h"
17 #define MALI_MAX_NUMBER_OF_L2_CACHE_CORES 3
18 /* Maximum 1 GP and 4 PP for an L2 cache core (Mali-400 Quad-core) */
19 #define MALI_MAX_NUMBER_OF_GROUPS_PER_L2_CACHE 5
22 struct mali_pm_domain;
24 /* Flags describing state of the L2 */
25 typedef enum mali_l2_power_status {
26 MALI_L2_NORMAL, /**< L2 is in normal state and operational */
27 MALI_L2_PAUSE, /**< L2 may not be accessed and may be powered off */
28 } mali_l2_power_status;
31 * Definition of the L2 cache core struct
32 * Used to track a L2 cache unit in the system.
33 * Contains information about the mapping of the registers
35 struct mali_l2_cache_core {
36 struct mali_hw_core hw_core; /**< Common for all HW cores */
37 u32 core_id; /**< Unique core ID */
38 #ifdef MALI_UPPER_HALF_SCHEDULING
39 _mali_osk_spinlock_irq_t *command_lock; /**< Serialize all L2 cache commands */
40 _mali_osk_spinlock_irq_t *counter_lock; /**< Synchronize L2 cache counter access */
42 _mali_osk_spinlock_t *command_lock;
43 _mali_osk_spinlock_t *counter_lock;
45 u32 counter_src0; /**< Performance counter 0, MALI_HW_CORE_NO_COUNTER for disabled */
46 u32 counter_src1; /**< Performance counter 1, MALI_HW_CORE_NO_COUNTER for disabled */
47 u32 last_invalidated_id;
48 struct mali_pm_domain *pm_domain;
49 mali_l2_power_status mali_l2_status; /**< Indicate whether the L2 is paused or not */
52 _mali_osk_errcode_t mali_l2_cache_initialize(void);
53 void mali_l2_cache_terminate(void);
55 * L2 pause is just a status that the L2 can't be accessed temporarily.
57 void mali_l2_cache_pause_all(mali_bool pause);
58 struct mali_l2_cache_core *mali_l2_cache_create(_mali_osk_resource_t * resource);
59 void mali_l2_cache_delete(struct mali_l2_cache_core *cache);
61 MALI_STATIC_INLINE void mali_l2_cache_set_pm_domain(struct mali_l2_cache_core *cache, struct mali_pm_domain *domain)
63 cache->pm_domain = domain;
66 u32 mali_l2_cache_get_id(struct mali_l2_cache_core *cache);
68 void mali_l2_cache_core_set_counter_src0(struct mali_l2_cache_core *cache, u32 counter);
69 void mali_l2_cache_core_set_counter_src1(struct mali_l2_cache_core *cache, u32 counter);
70 u32 mali_l2_cache_core_get_counter_src0(struct mali_l2_cache_core *cache);
71 u32 mali_l2_cache_core_get_counter_src1(struct mali_l2_cache_core *cache);
72 void mali_l2_cache_core_get_counter_values(struct mali_l2_cache_core *cache, u32 *src0, u32 *value0, u32 *src1, u32 *value1);
73 struct mali_l2_cache_core *mali_l2_cache_core_get_glob_l2_core(u32 index);
74 u32 mali_l2_cache_core_get_glob_num_l2_cores(void);
76 void mali_l2_cache_reset(struct mali_l2_cache_core *cache);
77 void mali_l2_cache_reset_all(void);
79 struct mali_group *mali_l2_cache_get_group(struct mali_l2_cache_core *cache, u32 index);
81 void mali_l2_cache_invalidate(struct mali_l2_cache_core *cache);
82 mali_bool mali_l2_cache_invalidate_conditional(struct mali_l2_cache_core *cache, u32 id);
83 void mali_l2_cache_invalidate_all(void);
84 void mali_l2_cache_invalidate_all_pages(u32 *pages, u32 num_pages);
86 mali_bool mali_l2_cache_lock_power_state(struct mali_l2_cache_core *cache);
87 void mali_l2_cache_unlock_power_state(struct mali_l2_cache_core *cache);
89 #endif /* __MALI_KERNEL_L2_CACHE_H__ */