2 * Copyright (C) 2011-2012 ARM Limited. All rights reserved.
4 * This program is free software and is provided to you under the terms of the GNU General Public License version 2
5 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
7 * A copy of the licence is included with the program, and can also be obtained from Free Software
8 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
13 * Defines types and interface exposed by the Mali Utgard device driver
16 #ifndef __MALI_UTGARD_H__
17 #define __MALI_UTGARD_H__
19 #define MALI_GPU_NAME_UTGARD "mali-utgard"
23 #define MALI_GPU_RESOURCES_MALI200(base_addr, gp_irq, pp_irq, mmu_irq) \
24 MALI_GPU_RESOURCE_PP(base_addr + 0x0000, pp_irq) \
25 MALI_GPU_RESOURCE_GP(base_addr + 0x2000, gp_irq) \
26 MALI_GPU_RESOURCE_MMU(base_addr + 0x3000, mmu_irq)
30 #define MALI_GPU_RESOURCES_MALI300(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \
31 MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq)
33 #define MALI_GPU_RESOURCES_MALI300_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \
34 MALI_GPU_RESOURCES_MALI400_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq)
38 #define MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
39 MALI_GPU_RESOURCE_L2(base_addr + 0x1000) \
40 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x0000, gp_irq, base_addr + 0x3000, gp_mmu_irq) \
41 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x8000, pp0_irq, base_addr + 0x4000, pp0_mmu_irq)
43 #define MALI_GPU_RESOURCES_MALI400_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
44 MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \
45 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000)
47 #define MALI_GPU_RESOURCES_MALI400_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
48 MALI_GPU_RESOURCE_L2(base_addr + 0x1000) \
49 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x0000, gp_irq, base_addr + 0x3000, gp_mmu_irq) \
50 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x8000, pp0_irq, base_addr + 0x4000, pp0_mmu_irq) \
51 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0xA000, pp1_irq, base_addr + 0x5000, pp1_mmu_irq)
53 #define MALI_GPU_RESOURCES_MALI400_MP2_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
54 MALI_GPU_RESOURCES_MALI400_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \
55 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000)
57 #define MALI_GPU_RESOURCES_MALI400_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
58 MALI_GPU_RESOURCE_L2(base_addr + 0x1000) \
59 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x0000, gp_irq, base_addr + 0x3000, gp_mmu_irq) \
60 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x8000, pp0_irq, base_addr + 0x4000, pp0_mmu_irq) \
61 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0xA000, pp1_irq, base_addr + 0x5000, pp1_mmu_irq) \
62 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0xC000, pp2_irq, base_addr + 0x6000, pp2_mmu_irq)
64 #define MALI_GPU_RESOURCES_MALI400_MP3_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
65 MALI_GPU_RESOURCES_MALI400_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \
66 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000)
68 #define MALI_GPU_RESOURCES_MALI400_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
69 MALI_GPU_RESOURCE_L2(base_addr + 0x1000) \
70 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x0000, gp_irq, base_addr + 0x3000, gp_mmu_irq) \
71 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x8000, pp0_irq, base_addr + 0x4000, pp0_mmu_irq) \
72 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0xA000, pp1_irq, base_addr + 0x5000, pp1_mmu_irq) \
73 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0xC000, pp2_irq, base_addr + 0x6000, pp2_mmu_irq) \
74 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + 0xE000, pp3_irq, base_addr + 0x7000, pp3_mmu_irq)
76 #define MALI_GPU_RESOURCES_MALI400_MP4_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
77 MALI_GPU_RESOURCES_MALI400_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \
78 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000)
81 #define MALI_GPU_RESOURCES_MALI450_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
82 MALI_GPU_RESOURCE_L2(base_addr + 0x10000) \
83 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x00000, gp_irq, base_addr + 0x03000, gp_mmu_irq) \
84 MALI_GPU_RESOURCE_L2(base_addr + 0x01000) \
85 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x08000, pp0_irq, base_addr + 0x04000, pp0_mmu_irq) \
86 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0x0A000, pp1_irq, base_addr + 0x05000, pp1_mmu_irq) \
87 MALI_GPU_RESOURCE_BCAST(base_addr + 0x13000) \
88 MALI_GPU_RESOURCE_DLBU(base_addr + 0x14000) \
89 MALI_GPU_RESOURCE_PP_BCAST(base_addr + 0x16000, pp_bcast_irq) \
90 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + 0x15000)
92 #define MALI_GPU_RESOURCES_MALI450_MP2_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
93 MALI_GPU_RESOURCES_MALI450_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \
94 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000) \
96 #define MALI_GPU_RESOURCES_MALI450_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
97 MALI_GPU_RESOURCE_L2(base_addr + 0x10000) \
98 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x00000, gp_irq, base_addr + 0x03000, gp_mmu_irq) \
99 MALI_GPU_RESOURCE_L2(base_addr + 0x01000) \
100 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x08000, pp0_irq, base_addr + 0x04000, pp0_mmu_irq) \
101 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0x0A000, pp1_irq, base_addr + 0x05000, pp1_mmu_irq) \
102 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0x0C000, pp2_irq, base_addr + 0x06000, pp2_mmu_irq) \
103 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + 0x0E000, pp3_irq, base_addr + 0x07000, pp3_mmu_irq) \
104 MALI_GPU_RESOURCE_BCAST(base_addr + 0x13000) \
105 MALI_GPU_RESOURCE_DLBU(base_addr + 0x14000) \
106 MALI_GPU_RESOURCE_PP_BCAST(base_addr + 0x16000, pp_bcast_irq) \
107 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + 0x15000)
109 #define MALI_GPU_RESOURCES_MALI450_MP4_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
110 MALI_GPU_RESOURCES_MALI450_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \
111 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000) \
113 #define MALI_GPU_RESOURCES_MALI450_MP6(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
114 MALI_GPU_RESOURCE_L2(base_addr + 0x10000) \
115 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x00000, gp_irq, base_addr + 0x03000, gp_mmu_irq) \
116 MALI_GPU_RESOURCE_L2(base_addr + 0x01000) \
117 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x08000, pp0_irq, base_addr + 0x04000, pp0_mmu_irq) \
118 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0x0A000, pp1_irq, base_addr + 0x05000, pp1_mmu_irq) \
119 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0x0C000, pp2_irq, base_addr + 0x06000, pp2_mmu_irq) \
120 MALI_GPU_RESOURCE_L2(base_addr + 0x11000) \
121 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + 0x28000, pp3_irq, base_addr + 0x1C000, pp3_mmu_irq) \
122 MALI_GPU_RESOURCE_PP_WITH_MMU(4, base_addr + 0x2A000, pp4_irq, base_addr + 0x1D000, pp4_mmu_irq) \
123 MALI_GPU_RESOURCE_PP_WITH_MMU(5, base_addr + 0x2C000, pp5_irq, base_addr + 0x1E000, pp5_mmu_irq) \
124 MALI_GPU_RESOURCE_BCAST(base_addr + 0x13000) \
125 MALI_GPU_RESOURCE_DLBU(base_addr + 0x14000) \
126 MALI_GPU_RESOURCE_PP_BCAST(base_addr + 0x16000, pp_bcast_irq) \
127 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + 0x15000)
129 #define MALI_GPU_RESOURCES_MALI450_MP6_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
130 MALI_GPU_RESOURCES_MALI450_MP6(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \
131 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000) \
133 #define MALI_GPU_RESOURCES_MALI450_MP8(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
134 MALI_GPU_RESOURCE_L2(base_addr + 0x10000) \
135 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + 0x00000, gp_irq, base_addr + 0x03000, gp_mmu_irq) \
136 MALI_GPU_RESOURCE_L2(base_addr + 0x01000) \
137 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + 0x08000, pp0_irq, base_addr + 0x04000, pp0_mmu_irq) \
138 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + 0x0A000, pp1_irq, base_addr + 0x05000, pp1_mmu_irq) \
139 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + 0x0C000, pp2_irq, base_addr + 0x06000, pp2_mmu_irq) \
140 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + 0x0E000, pp3_irq, base_addr + 0x07000, pp3_mmu_irq) \
141 MALI_GPU_RESOURCE_L2(base_addr + 0x11000) \
142 MALI_GPU_RESOURCE_PP_WITH_MMU(4, base_addr + 0x28000, pp4_irq, base_addr + 0x1C000, pp4_mmu_irq) \
143 MALI_GPU_RESOURCE_PP_WITH_MMU(5, base_addr + 0x2A000, pp5_irq, base_addr + 0x1D000, pp5_mmu_irq) \
144 MALI_GPU_RESOURCE_PP_WITH_MMU(6, base_addr + 0x2C000, pp6_irq, base_addr + 0x1E000, pp6_mmu_irq) \
145 MALI_GPU_RESOURCE_PP_WITH_MMU(7, base_addr + 0x2E000, pp7_irq, base_addr + 0x1F000, pp7_mmu_irq) \
146 MALI_GPU_RESOURCE_BCAST(base_addr + 0x13000) \
147 MALI_GPU_RESOURCE_DLBU(base_addr + 0x14000) \
148 MALI_GPU_RESOURCE_PP_BCAST(base_addr + 0x16000, pp_bcast_irq) \
149 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + 0x15000)
151 #define MALI_GPU_RESOURCES_MALI450_MP8_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
152 MALI_GPU_RESOURCES_MALI450_MP8(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \
153 MALI_GPU_RESOURCE_PMU(base_addr + 0x2000) \
155 #define MALI_GPU_RESOURCE_L2(addr) \
158 .flags = IORESOURCE_MEM, \
160 .end = addr + 0x200, \
163 #define MALI_GPU_RESOURCE_GP(gp_addr, gp_irq) \
166 .flags = IORESOURCE_MEM, \
168 .end = gp_addr + 0x100, \
171 .name = "Mali_GP_IRQ", \
172 .flags = IORESOURCE_IRQ, \
177 #define MALI_GPU_RESOURCE_GP_WITH_MMU(gp_addr, gp_irq, gp_mmu_addr, gp_mmu_irq) \
180 .flags = IORESOURCE_MEM, \
182 .end = gp_addr + 0x100, \
185 .name = "Mali_GP_IRQ", \
186 .flags = IORESOURCE_IRQ, \
191 .name = "Mali_GP_MMU", \
192 .flags = IORESOURCE_MEM, \
193 .start = gp_mmu_addr, \
194 .end = gp_mmu_addr + 0x100, \
197 .name = "Mali_GP_MMU_IRQ", \
198 .flags = IORESOURCE_IRQ, \
199 .start = gp_mmu_irq, \
203 #define MALI_GPU_RESOURCE_PP(pp_addr, pp_irq) \
206 .flags = IORESOURCE_MEM, \
208 .end = pp_addr + 0x1100, \
211 .name = "Mali_PP_IRQ", \
212 .flags = IORESOURCE_IRQ, \
217 #define MALI_GPU_RESOURCE_PP_WITH_MMU(id, pp_addr, pp_irq, pp_mmu_addr, pp_mmu_irq) \
219 .name = "Mali_PP" #id, \
220 .flags = IORESOURCE_MEM, \
222 .end = pp_addr + 0x1100, \
225 .name = "Mali_PP" #id "_IRQ", \
226 .flags = IORESOURCE_IRQ, \
231 .name = "Mali_PP" #id "_MMU", \
232 .flags = IORESOURCE_MEM, \
233 .start = pp_mmu_addr, \
234 .end = pp_mmu_addr + 0x100, \
237 .name = "Mali_PP" #id "_MMU_IRQ", \
238 .flags = IORESOURCE_IRQ, \
239 .start = pp_mmu_irq, \
243 #define MALI_GPU_RESOURCE_MMU(mmu_addr, mmu_irq) \
245 .name = "Mali_MMU", \
246 .flags = IORESOURCE_MEM, \
248 .end = mmu_addr + 0x100, \
251 .name = "Mali_MMU_IRQ", \
252 .flags = IORESOURCE_IRQ, \
257 #define MALI_GPU_RESOURCE_PMU(pmu_addr) \
259 .name = "Mali_PMU", \
260 .flags = IORESOURCE_MEM, \
262 .end = pmu_addr + 0x100, \
265 #define MALI_GPU_RESOURCE_DLBU(dlbu_addr) \
267 .name = "Mali_DLBU", \
268 .flags = IORESOURCE_MEM, \
269 .start = dlbu_addr, \
270 .end = dlbu_addr + 0x100, \
273 #define MALI_GPU_RESOURCE_BCAST(bcast_addr) \
275 .name = "Mali_Broadcast", \
276 .flags = IORESOURCE_MEM, \
277 .start = bcast_addr, \
278 .end = bcast_addr + 0x100, \
281 #define MALI_GPU_RESOURCE_PP_BCAST(pp_addr, pp_irq) \
283 .name = "Mali_PP_Broadcast", \
284 .flags = IORESOURCE_MEM, \
286 .end = pp_addr + 0x1100, \
289 .name = "Mali_PP_Broadcast_IRQ", \
290 .flags = IORESOURCE_IRQ, \
295 #define MALI_GPU_RESOURCE_PP_MMU_BCAST(pp_mmu_bcast_addr) \
297 .name = "Mali_PP_MMU_Broadcast", \
298 .flags = IORESOURCE_MEM, \
299 .start = pp_mmu_bcast_addr, \
300 .end = pp_mmu_bcast_addr + 0x100, \
303 struct mali_gpu_device_data
305 /* Dedicated GPU memory range (physical). */
306 unsigned long dedicated_mem_start;
307 unsigned long dedicated_mem_size;
309 /* Shared GPU memory */
310 unsigned long shared_mem_size;
312 /* Frame buffer memory to be accessible by Mali GPU (physical) */
313 unsigned long fb_start;
314 unsigned long fb_size;
316 /* Report GPU utilization in this interval (specified in ms) */
317 unsigned long utilization_interval;
319 /* Function that will receive periodic GPU utilization numbers */
320 void (*utilization_handler)(unsigned int);
323 /** @brief MALI GPU power down using MALI in-built PMU
325 * called to power down all cores
327 int mali_pmu_powerdown(void);
330 /** @brief MALI GPU power up using MALI in-built PMU
332 * called to power up all cores
334 int mali_pmu_powerup(void);