1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2013 - 2018 Xilinx, Michal Simek
10 #include <linux/list.h>
14 #include <dt-bindings/gpio/gpio.h>
16 #define XILINX_GPIO_MAX_BANK 2
24 struct xilinx_gpio_plat {
25 struct gpio_regs *regs;
26 int bank_max[XILINX_GPIO_MAX_BANK];
27 int bank_input[XILINX_GPIO_MAX_BANK];
28 int bank_output[XILINX_GPIO_MAX_BANK];
29 u32 dout_default[XILINX_GPIO_MAX_BANK];
32 struct xilinx_gpio_privdata {
33 u32 output_val[XILINX_GPIO_MAX_BANK];
36 static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
37 u32 *bank_pin_num, struct udevice *dev)
39 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
41 /* the first gpio is 0 not 1 */
44 for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) {
45 max_pins = plat->bank_max[bank];
46 if (pin_num < max_pins) {
47 debug("%s: found at bank 0x%x pin 0x%x\n", __func__,
50 *bank_pin_num = pin_num;
59 static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
62 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
63 struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
67 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
71 val = priv->output_val[bank];
73 debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
74 __func__, (ulong)plat->regs, value, offset, bank, pin, val);
77 val = val | (1 << pin);
79 val = val & ~(1 << pin);
81 writel(val, &plat->regs->gpiodata + bank * 2);
83 priv->output_val[bank] = val;
88 static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
90 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
91 struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
95 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
99 debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
100 (ulong)plat->regs, offset, bank, pin);
102 if (plat->bank_output[bank]) {
103 debug("%s: Read saved output value\n", __func__);
104 val = priv->output_val[bank];
106 debug("%s: Read input value from reg\n", __func__);
107 val = readl(&plat->regs->gpiodata + bank * 2);
110 val = !!(val & (1 << pin));
115 static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
117 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
121 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
125 /* Check if all pins are inputs */
126 if (plat->bank_input[bank])
129 /* Check if all pins are outputs */
130 if (plat->bank_output[bank])
133 /* FIXME test on dual */
134 val = readl(&plat->regs->gpiodir + bank * 2);
135 val = !(val & (1 << pin));
137 /* input is 1 in reg but GPIOF_INPUT is 0 */
138 /* output is 0 in reg but GPIOF_OUTPUT is 1 */
143 static int xilinx_gpio_direction_output(struct udevice *dev, unsigned offset,
146 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
150 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
154 /* can't change it if all is input by default */
155 if (plat->bank_input[bank])
158 xilinx_gpio_set_value(dev, offset, value);
160 if (!plat->bank_output[bank]) {
161 val = readl(&plat->regs->gpiodir + bank * 2);
162 val = val & ~(1 << pin);
163 writel(val, &plat->regs->gpiodir + bank * 2);
169 static int xilinx_gpio_direction_input(struct udevice *dev, unsigned offset)
171 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
175 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
180 if (plat->bank_input[bank])
183 /* can't change it if all is output by default */
184 if (plat->bank_output[bank])
187 val = readl(&plat->regs->gpiodir + bank * 2);
188 val = val | (1 << pin);
189 writel(val, &plat->regs->gpiodir + bank * 2);
194 static int xilinx_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
195 struct ofnode_phandle_args *args)
197 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
199 desc->offset = args->args[0];
201 debug("%s: argc: %x, [0]: %x, [1]: %x, [2]: %x\n", __func__,
202 args->args_count, args->args[0], args->args[1], args->args[2]);
205 * The second cell is channel offset:
206 * 0 is first channel, 8 is second channel
208 * U-Boot driver just combine channels together that's why simply
209 * add amount of pins in second channel if present.
212 if (!plat->bank_max[1]) {
213 printf("%s: %s has no second channel\n",
214 __func__, dev->name);
218 desc->offset += plat->bank_max[0];
221 /* The third cell is optional */
222 if (args->args_count > 2)
223 desc->flags = (args->args[2] &
224 GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);
226 debug("%s: offset %x, flags %lx\n",
227 __func__, desc->offset, desc->flags);
231 static const struct dm_gpio_ops xilinx_gpio_ops = {
232 .direction_input = xilinx_gpio_direction_input,
233 .direction_output = xilinx_gpio_direction_output,
234 .get_value = xilinx_gpio_get_value,
235 .set_value = xilinx_gpio_set_value,
236 .get_function = xilinx_gpio_get_function,
237 .xlate = xilinx_gpio_xlate,
240 static int xilinx_gpio_probe(struct udevice *dev)
242 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
243 struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
244 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
245 const void *label_ptr;
247 label_ptr = dev_read_prop(dev, "label", NULL);
249 uc_priv->bank_name = strdup(label_ptr);
250 if (!uc_priv->bank_name)
253 uc_priv->bank_name = dev->name;
256 uc_priv->gpio_count = plat->bank_max[0] + plat->bank_max[1];
258 priv->output_val[0] = plat->dout_default[0];
260 if (plat->bank_max[1])
261 priv->output_val[1] = plat->dout_default[1];
266 static int xilinx_gpio_of_to_plat(struct udevice *dev)
268 struct xilinx_gpio_plat *plat = dev_get_plat(dev);
271 plat->regs = dev_read_addr_ptr(dev);
273 plat->bank_max[0] = dev_read_u32_default(dev, "xlnx,gpio-width", 0);
274 plat->bank_input[0] = dev_read_u32_default(dev, "xlnx,all-inputs", 0);
275 plat->bank_output[0] = dev_read_u32_default(dev, "xlnx,all-outputs", 0);
276 plat->dout_default[0] = dev_read_u32_default(dev, "xlnx,dout-default",
279 is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
281 plat->bank_max[1] = dev_read_u32_default(dev,
282 "xlnx,gpio2-width", 0);
283 plat->bank_input[1] = dev_read_u32_default(dev,
284 "xlnx,all-inputs-2", 0);
285 plat->bank_output[1] = dev_read_u32_default(dev,
286 "xlnx,all-outputs-2", 0);
287 plat->dout_default[1] = dev_read_u32_default(dev,
288 "xlnx,dout-default-2", 0);
294 static const struct udevice_id xilinx_gpio_ids[] = {
295 { .compatible = "xlnx,xps-gpio-1.00.a",},
299 U_BOOT_DRIVER(xilinx_gpio) = {
302 .ops = &xilinx_gpio_ops,
303 .of_match = xilinx_gpio_ids,
304 .of_to_plat = xilinx_gpio_of_to_plat,
305 .probe = xilinx_gpio_probe,
306 .plat_auto = sizeof(struct xilinx_gpio_plat),
307 .priv_auto = sizeof(struct xilinx_gpio_privdata),