1 // SPDX-License-Identifier: GPL-2.0+
3 * NVIDIA Tegra20 GPIO handling.
4 * (C) Copyright 2010-2012,2015
5 * NVIDIA Corporation <www.nvidia.com>
9 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
10 * Tom Warren (twarren@nvidia.com)
20 #include <asm/bitops.h>
21 #include <asm/arch/tegra.h>
23 #include <dm/device-internal.h>
24 #include <dt-bindings/gpio/gpio.h>
26 static const int CONFIG_SFIO = 0;
27 static const int CONFIG_GPIO = 1;
28 static const int DIRECTION_INPUT = 0;
29 static const int DIRECTION_OUTPUT = 1;
31 struct tegra_gpio_platdata {
32 struct gpio_ctlr_bank *bank;
33 const char *port_name; /* Name of port, e.g. "B" */
34 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
37 /* Information about each port at run-time */
38 struct tegra_port_info {
39 struct gpio_ctlr_bank *bank;
40 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
43 /* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
44 static int get_config(unsigned gpio)
46 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
47 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
51 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
52 type = (u >> GPIO_BIT(gpio)) & 1;
54 debug("get_config: port = %d, bit = %d is %s\n",
55 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
57 return type ? CONFIG_GPIO : CONFIG_SFIO;
60 /* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
61 static void set_config(unsigned gpio, int type)
63 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
64 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
67 debug("set_config: port = %d, bit = %d, %s\n",
68 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
70 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
71 if (type != CONFIG_SFIO)
72 u |= 1 << GPIO_BIT(gpio);
74 u &= ~(1 << GPIO_BIT(gpio));
75 writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
78 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
79 static int get_direction(unsigned gpio)
81 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
82 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
86 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
87 dir = (u >> GPIO_BIT(gpio)) & 1;
89 debug("get_direction: port = %d, bit = %d, %s\n",
90 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
92 return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT;
95 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
96 static void set_direction(unsigned gpio, int output)
98 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
99 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
102 debug("set_direction: port = %d, bit = %d, %s\n",
103 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
105 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
106 if (output != DIRECTION_INPUT)
107 u |= 1 << GPIO_BIT(gpio);
109 u &= ~(1 << GPIO_BIT(gpio));
110 writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
113 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
114 static void set_level(unsigned gpio, int high)
116 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
117 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
120 debug("set_level: port = %d, bit %d == %d\n",
121 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
123 u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
125 u |= 1 << GPIO_BIT(gpio);
127 u &= ~(1 << GPIO_BIT(gpio));
128 writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
132 * Generic_GPIO primitives.
135 /* set GPIO pin 'gpio' as an input */
136 static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
138 struct tegra_port_info *state = dev_get_priv(dev);
140 /* Configure GPIO direction as input. */
141 set_direction(state->base_gpio + offset, DIRECTION_INPUT);
143 /* Enable the pin as a GPIO */
144 set_config(state->base_gpio + offset, 1);
149 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
150 static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
153 struct tegra_port_info *state = dev_get_priv(dev);
154 int gpio = state->base_gpio + offset;
156 /* Configure GPIO output value. */
157 set_level(gpio, value);
159 /* Configure GPIO direction as output. */
160 set_direction(gpio, DIRECTION_OUTPUT);
162 /* Enable the pin as a GPIO */
163 set_config(state->base_gpio + offset, 1);
168 /* read GPIO IN value of pin 'gpio' */
169 static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
171 struct tegra_port_info *state = dev_get_priv(dev);
172 int gpio = state->base_gpio + offset;
175 debug("%s: pin = %d (port %d:bit %d)\n", __func__,
176 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
178 if (get_direction(gpio) == DIRECTION_INPUT)
179 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
181 val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]);
183 return (val >> GPIO_BIT(gpio)) & 1;
186 /* write GPIO OUT value to pin 'gpio' */
187 static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
189 struct tegra_port_info *state = dev_get_priv(dev);
190 int gpio = state->base_gpio + offset;
192 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
193 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
195 /* Configure GPIO output value. */
196 set_level(gpio, value);
201 void gpio_config_table(const struct tegra_gpio_config *config, int len)
205 for (i = 0; i < len; i++) {
206 switch (config[i].init) {
207 case TEGRA_GPIO_INIT_IN:
208 set_direction(config[i].gpio, DIRECTION_INPUT);
210 case TEGRA_GPIO_INIT_OUT0:
211 set_level(config[i].gpio, 0);
212 set_direction(config[i].gpio, DIRECTION_OUTPUT);
214 case TEGRA_GPIO_INIT_OUT1:
215 set_level(config[i].gpio, 1);
216 set_direction(config[i].gpio, DIRECTION_OUTPUT);
219 set_config(config[i].gpio, CONFIG_GPIO);
223 static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
225 struct tegra_port_info *state = dev_get_priv(dev);
226 int gpio = state->base_gpio + offset;
228 if (!get_config(gpio))
230 else if (get_direction(gpio))
236 static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
237 struct ofnode_phandle_args *args)
241 gpio = args->args[0];
242 port = gpio / TEGRA_GPIOS_PER_PORT;
243 ret = device_get_child(dev, port, &desc->dev);
246 desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
247 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
252 static const struct dm_gpio_ops gpio_tegra_ops = {
253 .direction_input = tegra_gpio_direction_input,
254 .direction_output = tegra_gpio_direction_output,
255 .get_value = tegra_gpio_get_value,
256 .set_value = tegra_gpio_set_value,
257 .get_function = tegra_gpio_get_function,
258 .xlate = tegra_gpio_xlate,
262 * Returns the name of a GPIO port
264 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
266 * @base_port: Base port number (0, 1..n-1)
267 * @return allocated string containing the name
269 static char *gpio_port_name(int base_port)
276 *s++ = 'A' + (base_port % 26);
285 static const struct udevice_id tegra_gpio_ids[] = {
286 { .compatible = "nvidia,tegra30-gpio" },
287 { .compatible = "nvidia,tegra20-gpio" },
291 static int gpio_tegra_probe(struct udevice *dev)
293 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
294 struct tegra_port_info *priv = dev->priv;
295 struct tegra_gpio_platdata *plat = dev->platdata;
297 /* Only child devices have ports */
301 priv->bank = plat->bank;
302 priv->base_gpio = plat->base_gpio;
304 uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
305 uc_priv->bank_name = plat->port_name;
311 * We have a top-level GPIO device with no actual GPIOs. It has a child
312 * device for each Tegra port.
314 static int gpio_tegra_bind(struct udevice *parent)
316 struct tegra_gpio_platdata *plat = parent->platdata;
317 struct gpio_ctlr *ctlr;
322 /* If this is a child device, there is nothing to do here */
326 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
327 #ifdef CONFIG_SPL_BUILD
328 ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
329 bank_count = TEGRA_GPIO_BANKS;
335 * This driver does not make use of interrupts, other than to figure
336 * out the number of GPIO banks
338 len = dev_read_size(parent, "interrupts");
341 bank_count = len / 3 / sizeof(u32);
342 ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
343 if ((ulong)ctlr == FDT_ADDR_T_NONE)
347 for (bank = 0; bank < bank_count; bank++) {
350 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
351 struct tegra_gpio_platdata *plat;
355 plat = calloc(1, sizeof(*plat));
358 plat->bank = &ctlr->gpio_bank[bank];
359 base_port = bank * TEGRA_PORTS_PER_BANK + port;
360 plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
361 plat->port_name = gpio_port_name(base_port);
363 ret = device_bind(parent, parent->driver,
364 plat->port_name, plat, ofnode_null(),
368 dev_set_of_offset(dev, dev_of_offset(parent));
375 U_BOOT_DRIVER(gpio_tegra) = {
376 .name = "gpio_tegra",
378 .of_match = tegra_gpio_ids,
379 .bind = gpio_tegra_bind,
380 .probe = gpio_tegra_probe,
381 .priv_auto_alloc_size = sizeof(struct tegra_port_info),
382 .ops = &gpio_tegra_ops,