2 * NVIDIA Tegra20 GPIO handling.
3 * (C) Copyright 2010-2012
4 * NVIDIA Corporation <www.nvidia.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
11 * Tom Warren (twarren@nvidia.com)
20 #include <asm/bitops.h>
21 #include <asm/arch/tegra.h>
23 #include <dm/device-internal.h>
25 DECLARE_GLOBAL_DATA_PTR;
34 struct tegra_gpio_platdata {
35 struct gpio_ctlr_bank *bank;
36 const char *port_name; /* Name of port, e.g. "B" */
37 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
40 /* Information about each port at run-time */
41 struct tegra_port_info {
42 char label[TEGRA_GPIOS_PER_PORT][GPIO_NAME_SIZE];
43 struct gpio_ctlr_bank *bank;
44 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
47 /* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */
48 static int get_config(unsigned gpio)
50 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
51 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
55 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
56 type = (u >> GPIO_BIT(gpio)) & 1;
58 debug("get_config: port = %d, bit = %d is %s\n",
59 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
64 /* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */
65 static void set_config(unsigned gpio, int type)
67 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
68 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
71 debug("set_config: port = %d, bit = %d, %s\n",
72 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
74 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
76 u |= 1 << GPIO_BIT(gpio);
78 u &= ~(1 << GPIO_BIT(gpio));
79 writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
82 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
83 static int get_direction(unsigned gpio)
85 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
86 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
90 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
91 dir = (u >> GPIO_BIT(gpio)) & 1;
93 debug("get_direction: port = %d, bit = %d, %s\n",
94 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
99 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
100 static void set_direction(unsigned gpio, int output)
102 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
103 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
106 debug("set_direction: port = %d, bit = %d, %s\n",
107 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
109 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
111 u |= 1 << GPIO_BIT(gpio);
113 u &= ~(1 << GPIO_BIT(gpio));
114 writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
117 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
118 static void set_level(unsigned gpio, int high)
120 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
121 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
124 debug("set_level: port = %d, bit %d == %d\n",
125 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
127 u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
129 u |= 1 << GPIO_BIT(gpio);
131 u &= ~(1 << GPIO_BIT(gpio));
132 writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
135 static int check_reserved(struct udevice *dev, unsigned offset,
138 struct tegra_port_info *state = dev_get_priv(dev);
139 struct gpio_dev_priv *uc_priv = dev->uclass_priv;
141 if (!*state->label[offset]) {
142 printf("tegra_gpio: %s: error: gpio %s%d not reserved\n",
143 func, uc_priv->bank_name, offset);
150 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
151 int tegra_spl_gpio_direction_output(int gpio, int value)
153 /* Configure as a GPIO */
156 /* Configure GPIO output value. */
157 set_level(gpio, value);
159 /* Configure GPIO direction as output. */
160 set_direction(gpio, 1);
166 * Generic_GPIO primitives.
169 static int tegra_gpio_request(struct udevice *dev, unsigned offset,
172 struct tegra_port_info *state = dev_get_priv(dev);
174 if (*state->label[offset])
177 strncpy(state->label[offset], label, GPIO_NAME_SIZE);
178 state->label[offset][GPIO_NAME_SIZE - 1] = '\0';
180 /* Configure as a GPIO */
181 set_config(state->base_gpio + offset, 1);
186 static int tegra_gpio_free(struct udevice *dev, unsigned offset)
188 struct tegra_port_info *state = dev_get_priv(dev);
191 ret = check_reserved(dev, offset, __func__);
194 state->label[offset][0] = '\0';
199 /* read GPIO OUT value of pin 'gpio' */
200 static int tegra_gpio_get_output_value(unsigned gpio)
202 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
203 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
206 debug("gpio_get_output_value: pin = %d (port %d:bit %d)\n",
207 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
209 val = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
211 return (val >> GPIO_BIT(gpio)) & 1;
215 /* set GPIO pin 'gpio' as an input */
216 static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
218 struct tegra_port_info *state = dev_get_priv(dev);
221 ret = check_reserved(dev, offset, __func__);
225 /* Configure GPIO direction as input. */
226 set_direction(state->base_gpio + offset, 0);
231 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
232 static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
235 struct tegra_port_info *state = dev_get_priv(dev);
236 int gpio = state->base_gpio + offset;
239 ret = check_reserved(dev, offset, __func__);
243 /* Configure GPIO output value. */
244 set_level(gpio, value);
246 /* Configure GPIO direction as output. */
247 set_direction(gpio, 1);
252 /* read GPIO IN value of pin 'gpio' */
253 static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
255 struct tegra_port_info *state = dev_get_priv(dev);
256 int gpio = state->base_gpio + offset;
260 ret = check_reserved(dev, offset, __func__);
264 debug("%s: pin = %d (port %d:bit %d)\n", __func__,
265 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
267 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
269 return (val >> GPIO_BIT(gpio)) & 1;
272 /* write GPIO OUT value to pin 'gpio' */
273 static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
275 struct tegra_port_info *state = dev_get_priv(dev);
276 int gpio = state->base_gpio + offset;
279 ret = check_reserved(dev, offset, __func__);
283 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
284 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
286 /* Configure GPIO output value. */
287 set_level(gpio, value);
292 void gpio_config_table(const struct tegra_gpio_config *config, int len)
296 for (i = 0; i < len; i++) {
297 switch (config[i].init) {
298 case TEGRA_GPIO_INIT_IN:
299 gpio_direction_input(config[i].gpio);
301 case TEGRA_GPIO_INIT_OUT0:
302 gpio_direction_output(config[i].gpio, 0);
304 case TEGRA_GPIO_INIT_OUT1:
305 gpio_direction_output(config[i].gpio, 1);
308 set_config(config[i].gpio, 1);
312 static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
314 struct tegra_port_info *state = dev_get_priv(dev);
315 int gpio = state->base_gpio + offset;
317 if (!*state->label[offset])
319 if (!get_config(gpio))
321 else if (get_direction(gpio))
327 static int tegra_gpio_get_state(struct udevice *dev, unsigned int offset,
328 char *buf, int bufsize)
330 struct gpio_dev_priv *uc_priv = dev->uclass_priv;
331 struct tegra_port_info *state = dev_get_priv(dev);
332 int gpio = state->base_gpio + offset;
338 label = state->label[offset];
339 is_gpio = get_config(gpio); /* GPIO, not SFPIO */
340 size = snprintf(buf, bufsize, "%s%d: ",
341 uc_priv->bank_name ? uc_priv->bank_name : "", offset);
345 is_output = get_direction(gpio);
347 snprintf(buf, bufsize, "%s: %d [%c]%s%s",
348 is_output ? "out" : " in",
350 tegra_gpio_get_output_value(gpio) :
351 tegra_gpio_get_value(dev, offset),
356 snprintf(buf, bufsize, "sfpio");
362 static const struct dm_gpio_ops gpio_tegra_ops = {
363 .request = tegra_gpio_request,
364 .free = tegra_gpio_free,
365 .direction_input = tegra_gpio_direction_input,
366 .direction_output = tegra_gpio_direction_output,
367 .get_value = tegra_gpio_get_value,
368 .set_value = tegra_gpio_set_value,
369 .get_function = tegra_gpio_get_function,
370 .get_state = tegra_gpio_get_state,
374 * Returns the name of a GPIO port
376 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
378 * @base_port: Base port number (0, 1..n-1)
379 * @return allocated string containing the name
381 static char *gpio_port_name(int base_port)
388 *s++ = 'A' + (base_port % 26);
397 static const struct udevice_id tegra_gpio_ids[] = {
398 { .compatible = "nvidia,tegra30-gpio" },
399 { .compatible = "nvidia,tegra20-gpio" },
403 static int gpio_tegra_probe(struct udevice *dev)
405 struct gpio_dev_priv *uc_priv = dev->uclass_priv;
406 struct tegra_port_info *priv = dev->priv;
407 struct tegra_gpio_platdata *plat = dev->platdata;
409 /* Only child devices have ports */
413 priv->bank = plat->bank;
414 priv->base_gpio = plat->base_gpio;
416 uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
417 uc_priv->bank_name = plat->port_name;
423 * We have a top-level GPIO device with no actual GPIOs. It has a child
424 * device for each Tegra port.
426 static int gpio_tegra_bind(struct udevice *parent)
428 struct tegra_gpio_platdata *plat = parent->platdata;
429 struct gpio_ctlr *ctlr;
435 /* If this is a child device, there is nothing to do here */
440 * This driver does not make use of interrupts, other than to figure
441 * out the number of GPIO banks
443 if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len))
445 bank_count = len / 3 / sizeof(u32);
446 ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob,
447 parent->of_offset, "reg");
448 for (bank = 0; bank < bank_count; bank++) {
451 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
452 struct tegra_gpio_platdata *plat;
456 plat = calloc(1, sizeof(*plat));
459 plat->bank = &ctlr->gpio_bank[bank];
460 base_port = bank * TEGRA_PORTS_PER_BANK + port;
461 plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
462 plat->port_name = gpio_port_name(base_port);
464 ret = device_bind(parent, parent->driver,
465 plat->port_name, plat, -1, &dev);
468 dev->of_offset = parent->of_offset;
475 U_BOOT_DRIVER(gpio_tegra) = {
476 .name = "gpio_tegra",
478 .of_match = tegra_gpio_ids,
479 .bind = gpio_tegra_bind,
480 .probe = gpio_tegra_probe,
481 .priv_auto_alloc_size = sizeof(struct tegra_port_info),
482 .ops = &gpio_tegra_ops,