2 * NVIDIA Tegra20 GPIO handling.
3 * (C) Copyright 2010-2012
4 * NVIDIA Corporation <www.nvidia.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
11 * Tom Warren (twarren@nvidia.com)
20 #include <asm/bitops.h>
21 #include <asm/arch/tegra.h>
23 #include <dm/device-internal.h>
24 #include <dt-bindings/gpio/gpio.h>
26 DECLARE_GLOBAL_DATA_PTR;
35 struct tegra_gpio_platdata {
36 struct gpio_ctlr_bank *bank;
37 const char *port_name; /* Name of port, e.g. "B" */
38 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
41 /* Information about each port at run-time */
42 struct tegra_port_info {
43 struct gpio_ctlr_bank *bank;
44 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
47 /* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */
48 static int get_config(unsigned gpio)
50 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
51 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
55 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
56 type = (u >> GPIO_BIT(gpio)) & 1;
58 debug("get_config: port = %d, bit = %d is %s\n",
59 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
64 /* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */
65 static void set_config(unsigned gpio, int type)
67 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
68 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
71 debug("set_config: port = %d, bit = %d, %s\n",
72 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
74 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
76 u |= 1 << GPIO_BIT(gpio);
78 u &= ~(1 << GPIO_BIT(gpio));
79 writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
82 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
83 static int get_direction(unsigned gpio)
85 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
86 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
90 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
91 dir = (u >> GPIO_BIT(gpio)) & 1;
93 debug("get_direction: port = %d, bit = %d, %s\n",
94 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
99 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
100 static void set_direction(unsigned gpio, int output)
102 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
103 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
106 debug("set_direction: port = %d, bit = %d, %s\n",
107 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
109 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
111 u |= 1 << GPIO_BIT(gpio);
113 u &= ~(1 << GPIO_BIT(gpio));
114 writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
117 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
118 static void set_level(unsigned gpio, int high)
120 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
121 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
124 debug("set_level: port = %d, bit %d == %d\n",
125 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
127 u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
129 u |= 1 << GPIO_BIT(gpio);
131 u &= ~(1 << GPIO_BIT(gpio));
132 writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
136 * Generic_GPIO primitives.
139 /* set GPIO pin 'gpio' as an input */
140 static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
142 struct tegra_port_info *state = dev_get_priv(dev);
144 /* Configure GPIO direction as input. */
145 set_direction(state->base_gpio + offset, 0);
147 /* Enable the pin as a GPIO */
148 set_config(state->base_gpio + offset, 1);
153 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
154 static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
157 struct tegra_port_info *state = dev_get_priv(dev);
158 int gpio = state->base_gpio + offset;
160 /* Configure GPIO output value. */
161 set_level(gpio, value);
163 /* Configure GPIO direction as output. */
164 set_direction(gpio, 1);
166 /* Enable the pin as a GPIO */
167 set_config(state->base_gpio + offset, 1);
172 /* read GPIO IN value of pin 'gpio' */
173 static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
175 struct tegra_port_info *state = dev_get_priv(dev);
176 int gpio = state->base_gpio + offset;
179 debug("%s: pin = %d (port %d:bit %d)\n", __func__,
180 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
182 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
184 return (val >> GPIO_BIT(gpio)) & 1;
187 /* write GPIO OUT value to pin 'gpio' */
188 static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
190 struct tegra_port_info *state = dev_get_priv(dev);
191 int gpio = state->base_gpio + offset;
193 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
194 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
196 /* Configure GPIO output value. */
197 set_level(gpio, value);
202 void gpio_config_table(const struct tegra_gpio_config *config, int len)
206 for (i = 0; i < len; i++) {
207 switch (config[i].init) {
208 case TEGRA_GPIO_INIT_IN:
209 set_direction(config[i].gpio, 0);
211 case TEGRA_GPIO_INIT_OUT0:
212 set_level(config[i].gpio, 0);
213 set_direction(config[i].gpio, 1);
215 case TEGRA_GPIO_INIT_OUT1:
216 set_level(config[i].gpio, 1);
217 set_direction(config[i].gpio, 1);
220 set_config(config[i].gpio, 1);
224 static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
226 struct tegra_port_info *state = dev_get_priv(dev);
227 int gpio = state->base_gpio + offset;
229 if (!get_config(gpio))
231 else if (get_direction(gpio))
237 static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
238 struct fdtdec_phandle_args *args)
242 gpio = args->args[0];
243 port = gpio / TEGRA_GPIOS_PER_PORT;
244 ret = device_get_child(dev, port, &desc->dev);
247 desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
248 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
253 static const struct dm_gpio_ops gpio_tegra_ops = {
254 .direction_input = tegra_gpio_direction_input,
255 .direction_output = tegra_gpio_direction_output,
256 .get_value = tegra_gpio_get_value,
257 .set_value = tegra_gpio_set_value,
258 .get_function = tegra_gpio_get_function,
259 .xlate = tegra_gpio_xlate,
263 * Returns the name of a GPIO port
265 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
267 * @base_port: Base port number (0, 1..n-1)
268 * @return allocated string containing the name
270 static char *gpio_port_name(int base_port)
277 *s++ = 'A' + (base_port % 26);
286 static const struct udevice_id tegra_gpio_ids[] = {
287 { .compatible = "nvidia,tegra30-gpio" },
288 { .compatible = "nvidia,tegra20-gpio" },
292 static int gpio_tegra_probe(struct udevice *dev)
294 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
295 struct tegra_port_info *priv = dev->priv;
296 struct tegra_gpio_platdata *plat = dev->platdata;
298 /* Only child devices have ports */
302 priv->bank = plat->bank;
303 priv->base_gpio = plat->base_gpio;
305 uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
306 uc_priv->bank_name = plat->port_name;
312 * We have a top-level GPIO device with no actual GPIOs. It has a child
313 * device for each Tegra port.
315 static int gpio_tegra_bind(struct udevice *parent)
317 struct tegra_gpio_platdata *plat = parent->platdata;
318 struct gpio_ctlr *ctlr;
323 /* If this is a child device, there is nothing to do here */
327 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
328 #ifdef CONFIG_SPL_BUILD
329 ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
330 bank_count = TEGRA_GPIO_BANKS;
336 * This driver does not make use of interrupts, other than to figure
337 * out the number of GPIO banks
339 if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len))
341 bank_count = len / 3 / sizeof(u32);
342 ctlr = (struct gpio_ctlr *)dev_get_addr(parent);
345 for (bank = 0; bank < bank_count; bank++) {
348 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
349 struct tegra_gpio_platdata *plat;
353 plat = calloc(1, sizeof(*plat));
356 plat->bank = &ctlr->gpio_bank[bank];
357 base_port = bank * TEGRA_PORTS_PER_BANK + port;
358 plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
359 plat->port_name = gpio_port_name(base_port);
361 ret = device_bind(parent, parent->driver,
362 plat->port_name, plat, -1, &dev);
365 dev->of_offset = parent->of_offset;
372 U_BOOT_DRIVER(gpio_tegra) = {
373 .name = "gpio_tegra",
375 .of_match = tegra_gpio_ids,
376 .bind = gpio_tegra_bind,
377 .probe = gpio_tegra_probe,
378 .priv_auto_alloc_size = sizeof(struct tegra_port_info),
379 .ops = &gpio_tegra_ops,
380 .flags = DM_FLAG_PRE_RELOC,