3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
6 * Kamil Lulko, <kamil.lulko@gmail.com>
8 * Copyright 2015 ATS Advanced Telematics Systems GmbH
9 * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/errno.h>
17 #include <asm/arch/stm32.h>
18 #include <asm/arch/gpio.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #if defined(CONFIG_STM32F4)
23 #define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000)
24 #define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400)
25 #define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800)
26 #define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00)
27 #define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000)
28 #define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400)
29 #define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800)
30 #define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00)
31 #define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000)
33 static const unsigned long io_base[] = {
34 STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
35 STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
36 STM32_GPIOG_BASE, STM32_GPIOH_BASE, STM32_GPIOI_BASE
39 struct stm32_gpio_regs {
40 u32 moder; /* GPIO port mode */
41 u32 otyper; /* GPIO port output type */
42 u32 ospeedr; /* GPIO port output speed */
43 u32 pupdr; /* GPIO port pull-up/pull-down */
44 u32 idr; /* GPIO port input data */
45 u32 odr; /* GPIO port output data */
46 u32 bsrr; /* GPIO port bit set/reset */
47 u32 lckr; /* GPIO port configuration lock */
48 u32 afr[2]; /* GPIO alternate function */
51 #define CHECK_DSC(x) (!x || x->port > 8 || x->pin > 15)
52 #define CHECK_CTL(x) (!x || x->af > 15 || x->mode > 3 || x->otype > 1 || \
53 x->pupd > 2 || x->speed > 3)
55 int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
56 const struct stm32_gpio_ctl *ctl)
58 struct stm32_gpio_regs *gpio_regs;
71 gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
73 setbits_le32(&STM32_RCC->ahb1enr, 1 << dsc->port);
75 i = (dsc->pin & 0x07) * 4;
76 clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i);
80 clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i);
81 clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i);
82 clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i);
83 clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i);
89 #elif defined(CONFIG_STM32F1)
90 #define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800)
91 #define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00)
92 #define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000)
93 #define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400)
94 #define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800)
95 #define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00)
96 #define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000)
98 static const unsigned long io_base[] = {
99 STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
100 STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
104 #define STM32_GPIO_CR_MODE_MASK 0x3
105 #define STM32_GPIO_CR_MODE_SHIFT(p) (p * 4)
106 #define STM32_GPIO_CR_CNF_MASK 0x3
107 #define STM32_GPIO_CR_CNF_SHIFT(p) (p * 4 + 2)
109 struct stm32_gpio_regs {
110 u32 crl; /* GPIO port configuration low */
111 u32 crh; /* GPIO port configuration high */
112 u32 idr; /* GPIO port input data */
113 u32 odr; /* GPIO port output data */
114 u32 bsrr; /* GPIO port bit set/reset */
115 u32 brr; /* GPIO port bit reset */
116 u32 lckr; /* GPIO port configuration lock */
119 #define CHECK_DSC(x) (!x || x->port > 6 || x->pin > 15)
120 #define CHECK_CTL(x) (!x || x->mode > 3 || x->icnf > 3 || x->ocnf > 3 || \
123 int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
124 const struct stm32_gpio_ctl *ctl)
126 struct stm32_gpio_regs *gpio_regs;
131 if (CHECK_DSC(dsc)) {
135 if (CHECK_CTL(ctl)) {
142 gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
144 /* Enable clock for GPIO port */
145 setbits_le32(&STM32_RCC->apb2enr, 0x04 << dsc->port);
148 cr = &gpio_regs->crl;
151 cr = &gpio_regs->crh;
155 clrbits_le32(cr, 0x3 << STM32_GPIO_CR_MODE_SHIFT(crp));
156 setbits_le32(cr, ctl->mode << STM32_GPIO_CR_MODE_SHIFT(crp));
158 clrbits_le32(cr, 0x3 << STM32_GPIO_CR_CNF_SHIFT(crp));
159 /* Inputs set the optional pull up / pull down */
160 if (ctl->mode == STM32_GPIO_MODE_IN) {
161 setbits_le32(cr, ctl->icnf << STM32_GPIO_CR_CNF_SHIFT(crp));
162 clrbits_le32(&gpio_regs->odr, 0x1 << p);
163 setbits_le32(&gpio_regs->odr, ctl->pupd << p);
165 setbits_le32(cr, ctl->ocnf << STM32_GPIO_CR_CNF_SHIFT(crp));
173 #error STM32 family not supported
176 int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
178 struct stm32_gpio_regs *gpio_regs;
181 if (CHECK_DSC(dsc)) {
186 gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
189 writel(1 << dsc->pin, &gpio_regs->bsrr);
191 writel(1 << (dsc->pin + 16), &gpio_regs->bsrr);
198 int stm32_gpin_get(const struct stm32_gpio_dsc *dsc)
200 struct stm32_gpio_regs *gpio_regs;
203 if (CHECK_DSC(dsc)) {
208 gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
209 rv = readl(&gpio_regs->idr) & (1 << dsc->pin);
214 /* Common GPIO API */
216 int gpio_request(unsigned gpio, const char *label)
221 int gpio_free(unsigned gpio)
226 int gpio_direction_input(unsigned gpio)
228 struct stm32_gpio_dsc dsc;
229 struct stm32_gpio_ctl ctl;
231 dsc.port = stm32_gpio_to_port(gpio);
232 dsc.pin = stm32_gpio_to_pin(gpio);
233 #if defined(CONFIG_STM32F4)
234 ctl.af = STM32_GPIO_AF0;
235 ctl.mode = STM32_GPIO_MODE_IN;
236 ctl.otype = STM32_GPIO_OTYPE_PP;
237 ctl.pupd = STM32_GPIO_PUPD_NO;
238 ctl.speed = STM32_GPIO_SPEED_50M;
239 #elif defined(CONFIG_STM32F1)
240 ctl.mode = STM32_GPIO_MODE_IN;
241 ctl.icnf = STM32_GPIO_ICNF_IN_FLT;
242 ctl.ocnf = STM32_GPIO_OCNF_GP_PP; /* ignored for input */
243 ctl.pupd = STM32_GPIO_PUPD_UP; /* ignored for floating */
245 #error STM32 family not supported
248 return stm32_gpio_config(&dsc, &ctl);
251 int gpio_direction_output(unsigned gpio, int value)
253 struct stm32_gpio_dsc dsc;
254 struct stm32_gpio_ctl ctl;
257 dsc.port = stm32_gpio_to_port(gpio);
258 dsc.pin = stm32_gpio_to_pin(gpio);
259 #if defined(CONFIG_STM32F4)
260 ctl.af = STM32_GPIO_AF0;
261 ctl.mode = STM32_GPIO_MODE_OUT;
262 ctl.pupd = STM32_GPIO_PUPD_NO;
263 ctl.speed = STM32_GPIO_SPEED_50M;
264 #elif defined(CONFIG_STM32F1)
265 ctl.mode = STM32_GPIO_MODE_OUT_50M;
266 ctl.ocnf = STM32_GPIO_OCNF_GP_PP;
267 ctl.icnf = STM32_GPIO_ICNF_IN_FLT; /* ignored for output */
268 ctl.pupd = STM32_GPIO_PUPD_UP; /* ignored for output */
270 #error STM32 family not supported
273 res = stm32_gpio_config(&dsc, &ctl);
276 res = stm32_gpout_set(&dsc, value);
281 int gpio_get_value(unsigned gpio)
283 struct stm32_gpio_dsc dsc;
285 dsc.port = stm32_gpio_to_port(gpio);
286 dsc.pin = stm32_gpio_to_pin(gpio);
288 return stm32_gpin_get(&dsc);
291 int gpio_set_value(unsigned gpio, int value)
293 struct stm32_gpio_dsc dsc;
295 dsc.port = stm32_gpio_to_port(gpio);
296 dsc.pin = stm32_gpio_to_pin(gpio);
298 return stm32_gpout_set(&dsc, value);