1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
7 #define LOG_CATEGORY UCLASS_GPIO
14 #include <asm/arch/stm32.h>
17 #include <dm/device_compat.h>
18 #include <linux/bitops.h>
19 #include <linux/errno.h>
22 #include "stm32_gpio_priv.h"
24 #define STM32_GPIOS_PER_BANK 16
26 #define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
27 #define MODE_BITS_MASK 3
28 #define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
30 #define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
33 #define OTYPE_BITS(gpio_pin) (gpio_pin)
36 static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
43 bits_index = MODE_BITS(idx);
44 mask = MODE_BITS_MASK << bits_index;
46 clrsetbits_le32(®s->moder, mask, mode << bits_index);
49 static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
51 return (readl(®s->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
54 static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
56 enum stm32_gpio_otype otype)
60 bits = OTYPE_BITS(idx);
61 clrsetbits_le32(®s->otyper, OTYPE_MSK << bits, otype << bits);
64 static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
67 return (readl(®s->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
70 static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
72 enum stm32_gpio_pupd pupd)
76 bits = PUPD_BITS(idx);
77 clrsetbits_le32(®s->pupdr, PUPD_MASK << bits, pupd << bits);
80 static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
83 return (readl(®s->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
86 static bool stm32_gpio_is_mapped(struct udevice *dev, int offset)
88 struct stm32_gpio_priv *priv = dev_get_priv(dev);
90 return !!(priv->gpio_range & BIT(offset));
93 static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
95 struct stm32_gpio_priv *priv = dev_get_priv(dev);
96 struct stm32_gpio_regs *regs = priv->regs;
98 if (!stm32_gpio_is_mapped(dev, offset))
101 stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_IN);
106 static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
109 struct stm32_gpio_priv *priv = dev_get_priv(dev);
110 struct stm32_gpio_regs *regs = priv->regs;
112 if (!stm32_gpio_is_mapped(dev, offset))
115 stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_OUT);
117 writel(BSRR_BIT(offset, value), ®s->bsrr);
122 static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
124 struct stm32_gpio_priv *priv = dev_get_priv(dev);
125 struct stm32_gpio_regs *regs = priv->regs;
127 if (!stm32_gpio_is_mapped(dev, offset))
130 return readl(®s->idr) & BIT(offset) ? 1 : 0;
133 static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
135 struct stm32_gpio_priv *priv = dev_get_priv(dev);
136 struct stm32_gpio_regs *regs = priv->regs;
138 if (!stm32_gpio_is_mapped(dev, offset))
141 writel(BSRR_BIT(offset, value), ®s->bsrr);
146 static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
148 struct stm32_gpio_priv *priv = dev_get_priv(dev);
149 struct stm32_gpio_regs *regs = priv->regs;
154 if (!stm32_gpio_is_mapped(dev, offset))
155 return GPIOF_UNKNOWN;
157 bits_index = MODE_BITS(offset);
158 mask = MODE_BITS_MASK << bits_index;
160 mode = (readl(®s->moder) & mask) >> bits_index;
161 if (mode == STM32_GPIO_MODE_OUT)
163 if (mode == STM32_GPIO_MODE_IN)
165 if (mode == STM32_GPIO_MODE_AN)
171 static int stm32_gpio_set_flags(struct udevice *dev, unsigned int offset,
174 struct stm32_gpio_priv *priv = dev_get_priv(dev);
175 struct stm32_gpio_regs *regs = priv->regs;
177 if (!stm32_gpio_is_mapped(dev, offset))
180 if (flags & GPIOD_IS_OUT) {
181 bool value = flags & GPIOD_IS_OUT_ACTIVE;
183 if (flags & GPIOD_OPEN_DRAIN)
184 stm32_gpio_set_otype(regs, offset, STM32_GPIO_OTYPE_OD);
186 stm32_gpio_set_otype(regs, offset, STM32_GPIO_OTYPE_PP);
188 stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_OUT);
189 writel(BSRR_BIT(offset, value), ®s->bsrr);
191 } else if (flags & GPIOD_IS_IN) {
192 stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_IN);
194 if (flags & GPIOD_PULL_UP)
195 stm32_gpio_set_pupd(regs, offset, STM32_GPIO_PUPD_UP);
196 else if (flags & GPIOD_PULL_DOWN)
197 stm32_gpio_set_pupd(regs, offset, STM32_GPIO_PUPD_DOWN);
202 static int stm32_gpio_get_flags(struct udevice *dev, unsigned int offset,
205 struct stm32_gpio_priv *priv = dev_get_priv(dev);
206 struct stm32_gpio_regs *regs = priv->regs;
209 if (!stm32_gpio_is_mapped(dev, offset))
212 switch (stm32_gpio_get_moder(regs, offset)) {
213 case STM32_GPIO_MODE_OUT:
214 dir_flags |= GPIOD_IS_OUT;
215 if (stm32_gpio_get_otype(regs, offset) == STM32_GPIO_OTYPE_OD)
216 dir_flags |= GPIOD_OPEN_DRAIN;
217 if (readl(®s->idr) & BIT(offset))
218 dir_flags |= GPIOD_IS_OUT_ACTIVE;
220 case STM32_GPIO_MODE_IN:
221 dir_flags |= GPIOD_IS_IN;
226 switch (stm32_gpio_get_pupd(regs, offset)) {
227 case STM32_GPIO_PUPD_UP:
228 dir_flags |= GPIOD_PULL_UP;
230 case STM32_GPIO_PUPD_DOWN:
231 dir_flags |= GPIOD_PULL_DOWN;
241 static const struct dm_gpio_ops gpio_stm32_ops = {
242 .direction_input = stm32_gpio_direction_input,
243 .direction_output = stm32_gpio_direction_output,
244 .get_value = stm32_gpio_get_value,
245 .set_value = stm32_gpio_set_value,
246 .get_function = stm32_gpio_get_function,
247 .set_flags = stm32_gpio_set_flags,
248 .get_flags = stm32_gpio_get_flags,
251 static int gpio_stm32_probe(struct udevice *dev)
253 struct stm32_gpio_priv *priv = dev_get_priv(dev);
254 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
255 struct ofnode_phandle_args args;
261 addr = dev_read_addr(dev);
262 if (addr == FDT_ADDR_T_NONE)
265 priv->regs = (struct stm32_gpio_regs *)addr;
267 name = dev_read_string(dev, "st,bank-name");
270 uc_priv->bank_name = name;
273 ret = dev_read_phandle_with_args(dev, "gpio-ranges",
276 if (!ret && args.args_count < 3)
279 uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
281 priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
283 while (ret != -ENOENT) {
284 priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
287 ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
289 if (!ret && args.args_count < 3)
293 dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
294 (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
297 ret = clk_get_by_index(dev, 0, &clk);
301 ret = clk_enable(&clk);
304 dev_err(dev, "failed to enable clock\n");
307 dev_dbg(dev, "clock enabled\n");
312 U_BOOT_DRIVER(gpio_stm32) = {
313 .name = "gpio_stm32",
315 .probe = gpio_stm32_probe,
316 .ops = &gpio_stm32_ops,
317 .flags = DM_UC_FLAG_SEQ_ALIAS,
318 .priv_auto = sizeof(struct stm32_gpio_priv),