1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
11 #include <asm/arch/gpio.h>
12 #include <asm/arch/stm32.h>
15 #include <dm/device_compat.h>
16 #include <linux/errno.h>
19 #define MODE_BITS(gpio_pin) (gpio_pin * 2)
20 #define MODE_BITS_MASK 3
21 #define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16))
23 #ifndef CONFIG_SPL_BUILD
25 * convert gpio offset to gpio index taking into account gpio holes
28 int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
30 struct stm32_gpio_priv *priv = dev_get_priv(dev);
34 for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
35 if (priv->gpio_range & BIT(i)) {
41 /* shouldn't happen */
45 static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
47 struct stm32_gpio_priv *priv = dev_get_priv(dev);
48 struct stm32_gpio_regs *regs = priv->regs;
53 idx = stm32_offset_to_index(dev, offset);
57 bits_index = MODE_BITS(idx);
58 mask = MODE_BITS_MASK << bits_index;
60 clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_IN << bits_index);
65 static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
68 struct stm32_gpio_priv *priv = dev_get_priv(dev);
69 struct stm32_gpio_regs *regs = priv->regs;
74 idx = stm32_offset_to_index(dev, offset);
78 bits_index = MODE_BITS(idx);
79 mask = MODE_BITS_MASK << bits_index;
81 clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
83 writel(BSRR_BIT(idx, value), ®s->bsrr);
88 static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
90 struct stm32_gpio_priv *priv = dev_get_priv(dev);
91 struct stm32_gpio_regs *regs = priv->regs;
94 idx = stm32_offset_to_index(dev, offset);
98 return readl(®s->idr) & BIT(idx) ? 1 : 0;
101 static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
103 struct stm32_gpio_priv *priv = dev_get_priv(dev);
104 struct stm32_gpio_regs *regs = priv->regs;
107 idx = stm32_offset_to_index(dev, offset);
111 writel(BSRR_BIT(idx, value), ®s->bsrr);
116 static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
118 struct stm32_gpio_priv *priv = dev_get_priv(dev);
119 struct stm32_gpio_regs *regs = priv->regs;
125 idx = stm32_offset_to_index(dev, offset);
129 bits_index = MODE_BITS(idx);
130 mask = MODE_BITS_MASK << bits_index;
132 mode = (readl(®s->moder) & mask) >> bits_index;
133 if (mode == STM32_GPIO_MODE_OUT)
135 if (mode == STM32_GPIO_MODE_IN)
137 if (mode == STM32_GPIO_MODE_AN)
143 static const struct dm_gpio_ops gpio_stm32_ops = {
144 .direction_input = stm32_gpio_direction_input,
145 .direction_output = stm32_gpio_direction_output,
146 .get_value = stm32_gpio_get_value,
147 .set_value = stm32_gpio_set_value,
148 .get_function = stm32_gpio_get_function,
152 static int gpio_stm32_probe(struct udevice *dev)
154 struct stm32_gpio_priv *priv = dev_get_priv(dev);
159 addr = dev_read_addr(dev);
160 if (addr == FDT_ADDR_T_NONE)
163 priv->regs = (struct stm32_gpio_regs *)addr;
165 #ifndef CONFIG_SPL_BUILD
166 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
167 struct ofnode_phandle_args args;
171 name = dev_read_string(dev, "st,bank-name");
174 uc_priv->bank_name = name;
177 ret = dev_read_phandle_with_args(dev, "gpio-ranges",
180 if (ret == -ENOENT) {
181 uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
182 priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
185 while (ret != -ENOENT) {
186 priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
189 uc_priv->gpio_count += args.args[2];
191 ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
195 dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
196 (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
199 ret = clk_get_by_index(dev, 0, &clk);
203 ret = clk_enable(&clk);
206 dev_err(dev, "failed to enable clock\n");
209 debug("clock enabled for device %s\n", dev->name);
214 U_BOOT_DRIVER(gpio_stm32) = {
215 .name = "gpio_stm32",
217 .probe = gpio_stm32_probe,
218 #ifndef CONFIG_SPL_BUILD
219 .ops = &gpio_stm32_ops,
221 .flags = DM_UC_FLAG_SEQ_ALIAS,
222 .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),