1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
7 #define LOG_CATEGORY UCLASS_GPIO
14 #include <asm/arch/gpio.h>
15 #include <asm/arch/stm32.h>
18 #include <dm/device_compat.h>
19 #include <linux/bitops.h>
20 #include <linux/errno.h>
23 #define STM32_GPIOS_PER_BANK 16
25 #define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
26 #define MODE_BITS_MASK 3
27 #define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
29 #define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
32 #define OTYPE_BITS(gpio_pin) (gpio_pin)
35 static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
42 bits_index = MODE_BITS(idx);
43 mask = MODE_BITS_MASK << bits_index;
45 clrsetbits_le32(®s->moder, mask, mode << bits_index);
48 static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
50 return (readl(®s->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
53 static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
55 enum stm32_gpio_otype otype)
59 bits = OTYPE_BITS(idx);
60 clrsetbits_le32(®s->otyper, OTYPE_MSK << bits, otype << bits);
63 static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
66 return (readl(®s->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
69 static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
71 enum stm32_gpio_pupd pupd)
75 bits = PUPD_BITS(idx);
76 clrsetbits_le32(®s->pupdr, PUPD_MASK << bits, pupd << bits);
79 static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
82 return (readl(®s->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
86 * convert gpio offset to gpio index taking into account gpio holes
89 int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
91 struct stm32_gpio_priv *priv = dev_get_priv(dev);
95 for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
96 if (priv->gpio_range & BIT(i)) {
102 /* shouldn't happen */
106 static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
108 struct stm32_gpio_priv *priv = dev_get_priv(dev);
109 struct stm32_gpio_regs *regs = priv->regs;
112 idx = stm32_offset_to_index(dev, offset);
116 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
121 static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
124 struct stm32_gpio_priv *priv = dev_get_priv(dev);
125 struct stm32_gpio_regs *regs = priv->regs;
128 idx = stm32_offset_to_index(dev, offset);
132 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
134 writel(BSRR_BIT(idx, value), ®s->bsrr);
139 static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
141 struct stm32_gpio_priv *priv = dev_get_priv(dev);
142 struct stm32_gpio_regs *regs = priv->regs;
145 idx = stm32_offset_to_index(dev, offset);
149 return readl(®s->idr) & BIT(idx) ? 1 : 0;
152 static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
154 struct stm32_gpio_priv *priv = dev_get_priv(dev);
155 struct stm32_gpio_regs *regs = priv->regs;
158 idx = stm32_offset_to_index(dev, offset);
162 writel(BSRR_BIT(idx, value), ®s->bsrr);
167 static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
169 struct stm32_gpio_priv *priv = dev_get_priv(dev);
170 struct stm32_gpio_regs *regs = priv->regs;
176 idx = stm32_offset_to_index(dev, offset);
180 bits_index = MODE_BITS(idx);
181 mask = MODE_BITS_MASK << bits_index;
183 mode = (readl(®s->moder) & mask) >> bits_index;
184 if (mode == STM32_GPIO_MODE_OUT)
186 if (mode == STM32_GPIO_MODE_IN)
188 if (mode == STM32_GPIO_MODE_AN)
194 static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
197 struct stm32_gpio_priv *priv = dev_get_priv(dev);
198 struct stm32_gpio_regs *regs = priv->regs;
201 idx = stm32_offset_to_index(dev, offset);
205 if (flags & GPIOD_IS_OUT) {
206 int value = GPIOD_FLAGS_OUTPUT(flags);
208 if (flags & GPIOD_OPEN_DRAIN)
209 stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
211 stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
212 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
213 writel(BSRR_BIT(idx, value), ®s->bsrr);
215 } else if (flags & GPIOD_IS_IN) {
216 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
218 if (flags & GPIOD_PULL_UP)
219 stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
220 else if (flags & GPIOD_PULL_DOWN)
221 stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
226 static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset,
229 struct stm32_gpio_priv *priv = dev_get_priv(dev);
230 struct stm32_gpio_regs *regs = priv->regs;
234 idx = stm32_offset_to_index(dev, offset);
238 switch (stm32_gpio_get_moder(regs, idx)) {
239 case STM32_GPIO_MODE_OUT:
240 dir_flags |= GPIOD_IS_OUT;
241 if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD)
242 dir_flags |= GPIOD_OPEN_DRAIN;
243 if (readl(®s->idr) & BIT(idx))
244 dir_flags |= GPIOD_IS_OUT_ACTIVE;
246 case STM32_GPIO_MODE_IN:
247 dir_flags |= GPIOD_IS_IN;
252 switch (stm32_gpio_get_pupd(regs, idx)) {
253 case STM32_GPIO_PUPD_UP:
254 dir_flags |= GPIOD_PULL_UP;
256 case STM32_GPIO_PUPD_DOWN:
257 dir_flags |= GPIOD_PULL_DOWN;
267 static const struct dm_gpio_ops gpio_stm32_ops = {
268 .direction_input = stm32_gpio_direction_input,
269 .direction_output = stm32_gpio_direction_output,
270 .get_value = stm32_gpio_get_value,
271 .set_value = stm32_gpio_set_value,
272 .get_function = stm32_gpio_get_function,
273 .set_dir_flags = stm32_gpio_set_dir_flags,
274 .get_dir_flags = stm32_gpio_get_dir_flags,
277 static int gpio_stm32_probe(struct udevice *dev)
279 struct stm32_gpio_priv *priv = dev_get_priv(dev);
280 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
281 struct ofnode_phandle_args args;
287 addr = dev_read_addr(dev);
288 if (addr == FDT_ADDR_T_NONE)
291 priv->regs = (struct stm32_gpio_regs *)addr;
293 name = dev_read_string(dev, "st,bank-name");
296 uc_priv->bank_name = name;
299 ret = dev_read_phandle_with_args(dev, "gpio-ranges",
302 if (!ret && args.args_count < 3)
305 if (ret == -ENOENT) {
306 uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
307 priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
310 while (ret != -ENOENT) {
311 priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
314 uc_priv->gpio_count += args.args[2];
316 ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
318 if (!ret && args.args_count < 3)
322 dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
323 (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
326 ret = clk_get_by_index(dev, 0, &clk);
330 ret = clk_enable(&clk);
333 dev_err(dev, "failed to enable clock\n");
336 dev_dbg(dev, "clock enabled\n");
341 U_BOOT_DRIVER(gpio_stm32) = {
342 .name = "gpio_stm32",
344 .probe = gpio_stm32_probe,
345 .ops = &gpio_stm32_ops,
346 .flags = DM_UC_FLAG_SEQ_ALIAS,
347 .priv_auto = sizeof(struct stm32_gpio_priv),