1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
12 #include <asm/arch/gpio.h>
13 #include <asm/arch/stm32.h>
16 #include <dm/device_compat.h>
17 #include <linux/bitops.h>
18 #include <linux/errno.h>
21 #define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
22 #define MODE_BITS_MASK 3
23 #define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
25 #define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
28 #define OTYPE_BITS(gpio_pin) (gpio_pin)
31 static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
38 bits_index = MODE_BITS(idx);
39 mask = MODE_BITS_MASK << bits_index;
41 clrsetbits_le32(®s->moder, mask, mode << bits_index);
44 static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
46 enum stm32_gpio_otype otype)
50 bits = OTYPE_BITS(idx);
51 clrsetbits_le32(®s->otyper, OTYPE_MSK << bits, otype << bits);
54 static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
56 enum stm32_gpio_pupd pupd)
60 bits = PUPD_BITS(idx);
61 clrsetbits_le32(®s->pupdr, PUPD_MASK << bits, pupd << bits);
65 * convert gpio offset to gpio index taking into account gpio holes
68 int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
70 struct stm32_gpio_priv *priv = dev_get_priv(dev);
74 for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
75 if (priv->gpio_range & BIT(i)) {
81 /* shouldn't happen */
85 static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
87 struct stm32_gpio_priv *priv = dev_get_priv(dev);
88 struct stm32_gpio_regs *regs = priv->regs;
91 idx = stm32_offset_to_index(dev, offset);
95 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
100 static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
103 struct stm32_gpio_priv *priv = dev_get_priv(dev);
104 struct stm32_gpio_regs *regs = priv->regs;
107 idx = stm32_offset_to_index(dev, offset);
111 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
113 writel(BSRR_BIT(idx, value), ®s->bsrr);
118 static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
120 struct stm32_gpio_priv *priv = dev_get_priv(dev);
121 struct stm32_gpio_regs *regs = priv->regs;
124 idx = stm32_offset_to_index(dev, offset);
128 return readl(®s->idr) & BIT(idx) ? 1 : 0;
131 static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
133 struct stm32_gpio_priv *priv = dev_get_priv(dev);
134 struct stm32_gpio_regs *regs = priv->regs;
137 idx = stm32_offset_to_index(dev, offset);
141 writel(BSRR_BIT(idx, value), ®s->bsrr);
146 static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
148 struct stm32_gpio_priv *priv = dev_get_priv(dev);
149 struct stm32_gpio_regs *regs = priv->regs;
155 idx = stm32_offset_to_index(dev, offset);
159 bits_index = MODE_BITS(idx);
160 mask = MODE_BITS_MASK << bits_index;
162 mode = (readl(®s->moder) & mask) >> bits_index;
163 if (mode == STM32_GPIO_MODE_OUT)
165 if (mode == STM32_GPIO_MODE_IN)
167 if (mode == STM32_GPIO_MODE_AN)
173 static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
176 struct stm32_gpio_priv *priv = dev_get_priv(dev);
177 struct stm32_gpio_regs *regs = priv->regs;
180 idx = stm32_offset_to_index(dev, offset);
184 if (flags & GPIOD_IS_OUT) {
185 int value = GPIOD_FLAGS_OUTPUT(flags);
187 if (flags & GPIOD_OPEN_DRAIN)
188 stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
190 stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
191 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
192 writel(BSRR_BIT(idx, value), ®s->bsrr);
194 } else if (flags & GPIOD_IS_IN) {
195 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
196 if (flags & GPIOD_PULL_UP)
197 stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
198 else if (flags & GPIOD_PULL_DOWN)
199 stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
205 static const struct dm_gpio_ops gpio_stm32_ops = {
206 .direction_input = stm32_gpio_direction_input,
207 .direction_output = stm32_gpio_direction_output,
208 .get_value = stm32_gpio_get_value,
209 .set_value = stm32_gpio_set_value,
210 .get_function = stm32_gpio_get_function,
211 .set_dir_flags = stm32_gpio_set_dir_flags,
214 static int gpio_stm32_probe(struct udevice *dev)
216 struct stm32_gpio_priv *priv = dev_get_priv(dev);
221 addr = dev_read_addr(dev);
222 if (addr == FDT_ADDR_T_NONE)
225 priv->regs = (struct stm32_gpio_regs *)addr;
227 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
228 struct ofnode_phandle_args args;
232 name = dev_read_string(dev, "st,bank-name");
235 uc_priv->bank_name = name;
238 ret = dev_read_phandle_with_args(dev, "gpio-ranges",
241 if (ret == -ENOENT) {
242 uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
243 priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
246 while (ret != -ENOENT) {
247 priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
250 uc_priv->gpio_count += args.args[2];
252 ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
256 dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
257 (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
260 ret = clk_get_by_index(dev, 0, &clk);
264 ret = clk_enable(&clk);
267 dev_err(dev, "failed to enable clock\n");
270 debug("clock enabled for device %s\n", dev->name);
275 U_BOOT_DRIVER(gpio_stm32) = {
276 .name = "gpio_stm32",
278 .probe = gpio_stm32_probe,
279 .ops = &gpio_stm32_ops,
280 .flags = DM_UC_FLAG_SEQ_ALIAS,
281 .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),