1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
7 #define LOG_CATEGORY UCLASS_GPIO
14 #include <asm/arch/stm32.h>
17 #include <dm/device_compat.h>
18 #include <linux/bitops.h>
19 #include <linux/errno.h>
22 #include "stm32_gpio_priv.h"
24 #define STM32_GPIOS_PER_BANK 16
26 #define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
27 #define MODE_BITS_MASK 3
28 #define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
30 #define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
33 #define OTYPE_BITS(gpio_pin) (gpio_pin)
36 static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
43 bits_index = MODE_BITS(idx);
44 mask = MODE_BITS_MASK << bits_index;
46 clrsetbits_le32(®s->moder, mask, mode << bits_index);
49 static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
51 return (readl(®s->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
54 static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
56 enum stm32_gpio_otype otype)
60 bits = OTYPE_BITS(idx);
61 clrsetbits_le32(®s->otyper, OTYPE_MSK << bits, otype << bits);
64 static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
67 return (readl(®s->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
70 static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
72 enum stm32_gpio_pupd pupd)
76 bits = PUPD_BITS(idx);
77 clrsetbits_le32(®s->pupdr, PUPD_MASK << bits, pupd << bits);
80 static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
83 return (readl(®s->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
87 * convert gpio offset to gpio index taking into account gpio holes
90 int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
92 struct stm32_gpio_priv *priv = dev_get_priv(dev);
96 for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
97 if (priv->gpio_range & BIT(i)) {
103 /* shouldn't happen */
107 static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
109 struct stm32_gpio_priv *priv = dev_get_priv(dev);
110 struct stm32_gpio_regs *regs = priv->regs;
113 idx = stm32_offset_to_index(dev, offset);
117 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
122 static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
125 struct stm32_gpio_priv *priv = dev_get_priv(dev);
126 struct stm32_gpio_regs *regs = priv->regs;
129 idx = stm32_offset_to_index(dev, offset);
133 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
135 writel(BSRR_BIT(idx, value), ®s->bsrr);
140 static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
142 struct stm32_gpio_priv *priv = dev_get_priv(dev);
143 struct stm32_gpio_regs *regs = priv->regs;
146 idx = stm32_offset_to_index(dev, offset);
150 return readl(®s->idr) & BIT(idx) ? 1 : 0;
153 static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
155 struct stm32_gpio_priv *priv = dev_get_priv(dev);
156 struct stm32_gpio_regs *regs = priv->regs;
159 idx = stm32_offset_to_index(dev, offset);
163 writel(BSRR_BIT(idx, value), ®s->bsrr);
168 static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
170 struct stm32_gpio_priv *priv = dev_get_priv(dev);
171 struct stm32_gpio_regs *regs = priv->regs;
177 idx = stm32_offset_to_index(dev, offset);
181 bits_index = MODE_BITS(idx);
182 mask = MODE_BITS_MASK << bits_index;
184 mode = (readl(®s->moder) & mask) >> bits_index;
185 if (mode == STM32_GPIO_MODE_OUT)
187 if (mode == STM32_GPIO_MODE_IN)
189 if (mode == STM32_GPIO_MODE_AN)
195 static int stm32_gpio_set_flags(struct udevice *dev, unsigned int offset,
198 struct stm32_gpio_priv *priv = dev_get_priv(dev);
199 struct stm32_gpio_regs *regs = priv->regs;
202 idx = stm32_offset_to_index(dev, offset);
206 if (flags & GPIOD_IS_OUT) {
207 bool value = flags & GPIOD_IS_OUT_ACTIVE;
209 if (flags & GPIOD_OPEN_DRAIN)
210 stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
212 stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
214 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
215 writel(BSRR_BIT(idx, value), ®s->bsrr);
217 } else if (flags & GPIOD_IS_IN) {
218 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
220 if (flags & GPIOD_PULL_UP)
221 stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
222 else if (flags & GPIOD_PULL_DOWN)
223 stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
228 static int stm32_gpio_get_flags(struct udevice *dev, unsigned int offset,
231 struct stm32_gpio_priv *priv = dev_get_priv(dev);
232 struct stm32_gpio_regs *regs = priv->regs;
236 idx = stm32_offset_to_index(dev, offset);
240 switch (stm32_gpio_get_moder(regs, idx)) {
241 case STM32_GPIO_MODE_OUT:
242 dir_flags |= GPIOD_IS_OUT;
243 if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD)
244 dir_flags |= GPIOD_OPEN_DRAIN;
245 if (readl(®s->idr) & BIT(idx))
246 dir_flags |= GPIOD_IS_OUT_ACTIVE;
248 case STM32_GPIO_MODE_IN:
249 dir_flags |= GPIOD_IS_IN;
254 switch (stm32_gpio_get_pupd(regs, idx)) {
255 case STM32_GPIO_PUPD_UP:
256 dir_flags |= GPIOD_PULL_UP;
258 case STM32_GPIO_PUPD_DOWN:
259 dir_flags |= GPIOD_PULL_DOWN;
269 static const struct dm_gpio_ops gpio_stm32_ops = {
270 .direction_input = stm32_gpio_direction_input,
271 .direction_output = stm32_gpio_direction_output,
272 .get_value = stm32_gpio_get_value,
273 .set_value = stm32_gpio_set_value,
274 .get_function = stm32_gpio_get_function,
275 .set_flags = stm32_gpio_set_flags,
276 .get_flags = stm32_gpio_get_flags,
279 static int gpio_stm32_probe(struct udevice *dev)
281 struct stm32_gpio_priv *priv = dev_get_priv(dev);
282 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
283 struct ofnode_phandle_args args;
289 addr = dev_read_addr(dev);
290 if (addr == FDT_ADDR_T_NONE)
293 priv->regs = (struct stm32_gpio_regs *)addr;
295 name = dev_read_string(dev, "st,bank-name");
298 uc_priv->bank_name = name;
301 ret = dev_read_phandle_with_args(dev, "gpio-ranges",
304 if (!ret && args.args_count < 3)
307 if (ret == -ENOENT) {
308 uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
309 priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
312 while (ret != -ENOENT) {
313 priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
316 uc_priv->gpio_count += args.args[2];
318 ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
320 if (!ret && args.args_count < 3)
324 dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
325 (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
328 ret = clk_get_by_index(dev, 0, &clk);
332 ret = clk_enable(&clk);
335 dev_err(dev, "failed to enable clock\n");
338 dev_dbg(dev, "clock enabled\n");
343 U_BOOT_DRIVER(gpio_stm32) = {
344 .name = "gpio_stm32",
346 .probe = gpio_stm32_probe,
347 .ops = &gpio_stm32_ops,
348 .flags = DM_UC_FLAG_SEQ_ALIAS,
349 .priv_auto = sizeof(struct stm32_gpio_priv),