1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
12 #include <asm/arch/gpio.h>
13 #include <asm/arch/stm32.h>
16 #include <dm/device_compat.h>
17 #include <linux/bitops.h>
18 #include <linux/errno.h>
21 #define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
22 #define MODE_BITS_MASK 3
23 #define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
25 #define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
28 #define OTYPE_BITS(gpio_pin) (gpio_pin)
31 static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
38 bits_index = MODE_BITS(idx);
39 mask = MODE_BITS_MASK << bits_index;
41 clrsetbits_le32(®s->moder, mask, mode << bits_index);
44 static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
46 return (readl(®s->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
49 static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
51 enum stm32_gpio_otype otype)
55 bits = OTYPE_BITS(idx);
56 clrsetbits_le32(®s->otyper, OTYPE_MSK << bits, otype << bits);
59 static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
62 return (readl(®s->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
65 static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
67 enum stm32_gpio_pupd pupd)
71 bits = PUPD_BITS(idx);
72 clrsetbits_le32(®s->pupdr, PUPD_MASK << bits, pupd << bits);
75 static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
78 return (readl(®s->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
82 * convert gpio offset to gpio index taking into account gpio holes
85 int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
87 struct stm32_gpio_priv *priv = dev_get_priv(dev);
91 for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
92 if (priv->gpio_range & BIT(i)) {
98 /* shouldn't happen */
102 static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
104 struct stm32_gpio_priv *priv = dev_get_priv(dev);
105 struct stm32_gpio_regs *regs = priv->regs;
108 idx = stm32_offset_to_index(dev, offset);
112 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
117 static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
120 struct stm32_gpio_priv *priv = dev_get_priv(dev);
121 struct stm32_gpio_regs *regs = priv->regs;
124 idx = stm32_offset_to_index(dev, offset);
128 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
130 writel(BSRR_BIT(idx, value), ®s->bsrr);
135 static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
137 struct stm32_gpio_priv *priv = dev_get_priv(dev);
138 struct stm32_gpio_regs *regs = priv->regs;
141 idx = stm32_offset_to_index(dev, offset);
145 return readl(®s->idr) & BIT(idx) ? 1 : 0;
148 static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
150 struct stm32_gpio_priv *priv = dev_get_priv(dev);
151 struct stm32_gpio_regs *regs = priv->regs;
154 idx = stm32_offset_to_index(dev, offset);
158 writel(BSRR_BIT(idx, value), ®s->bsrr);
163 static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
165 struct stm32_gpio_priv *priv = dev_get_priv(dev);
166 struct stm32_gpio_regs *regs = priv->regs;
172 idx = stm32_offset_to_index(dev, offset);
176 bits_index = MODE_BITS(idx);
177 mask = MODE_BITS_MASK << bits_index;
179 mode = (readl(®s->moder) & mask) >> bits_index;
180 if (mode == STM32_GPIO_MODE_OUT)
182 if (mode == STM32_GPIO_MODE_IN)
184 if (mode == STM32_GPIO_MODE_AN)
190 static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
193 struct stm32_gpio_priv *priv = dev_get_priv(dev);
194 struct stm32_gpio_regs *regs = priv->regs;
197 idx = stm32_offset_to_index(dev, offset);
201 if (flags & GPIOD_IS_OUT) {
202 int value = GPIOD_FLAGS_OUTPUT(flags);
204 if (flags & GPIOD_OPEN_DRAIN)
205 stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
207 stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
208 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
209 writel(BSRR_BIT(idx, value), ®s->bsrr);
211 } else if (flags & GPIOD_IS_IN) {
212 stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
213 if (flags & GPIOD_PULL_UP)
214 stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
215 else if (flags & GPIOD_PULL_DOWN)
216 stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
222 static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset,
225 struct stm32_gpio_priv *priv = dev_get_priv(dev);
226 struct stm32_gpio_regs *regs = priv->regs;
230 idx = stm32_offset_to_index(dev, offset);
234 switch (stm32_gpio_get_moder(regs, idx)) {
235 case STM32_GPIO_MODE_OUT:
236 dir_flags |= GPIOD_IS_OUT;
237 if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD)
238 dir_flags |= GPIOD_OPEN_DRAIN;
239 if (readl(®s->idr) & BIT(idx))
240 dir_flags |= GPIOD_IS_OUT_ACTIVE;
242 case STM32_GPIO_MODE_IN:
243 dir_flags |= GPIOD_IS_IN;
244 switch (stm32_gpio_get_pupd(regs, idx)) {
245 case STM32_GPIO_PUPD_UP:
246 dir_flags |= GPIOD_PULL_UP;
248 case STM32_GPIO_PUPD_DOWN:
249 dir_flags |= GPIOD_PULL_DOWN;
263 static const struct dm_gpio_ops gpio_stm32_ops = {
264 .direction_input = stm32_gpio_direction_input,
265 .direction_output = stm32_gpio_direction_output,
266 .get_value = stm32_gpio_get_value,
267 .set_value = stm32_gpio_set_value,
268 .get_function = stm32_gpio_get_function,
269 .set_dir_flags = stm32_gpio_set_dir_flags,
270 .get_dir_flags = stm32_gpio_get_dir_flags,
273 static int gpio_stm32_probe(struct udevice *dev)
275 struct stm32_gpio_priv *priv = dev_get_priv(dev);
276 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
277 struct ofnode_phandle_args args;
283 addr = dev_read_addr(dev);
284 if (addr == FDT_ADDR_T_NONE)
287 priv->regs = (struct stm32_gpio_regs *)addr;
289 name = dev_read_string(dev, "st,bank-name");
292 uc_priv->bank_name = name;
295 ret = dev_read_phandle_with_args(dev, "gpio-ranges",
298 if (!ret && args.args_count < 3)
301 if (ret == -ENOENT) {
302 uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
303 priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
306 while (ret != -ENOENT) {
307 priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
310 uc_priv->gpio_count += args.args[2];
312 ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
314 if (!ret && args.args_count < 3)
318 dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
319 (u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
322 ret = clk_get_by_index(dev, 0, &clk);
326 ret = clk_enable(&clk);
329 dev_err(dev, "failed to enable clock\n");
332 debug("clock enabled for device %s\n", dev->name);
337 U_BOOT_DRIVER(gpio_stm32) = {
338 .name = "gpio_stm32",
340 .probe = gpio_stm32_probe,
341 .ops = &gpio_stm32_ops,
342 .flags = DM_UC_FLAG_SEQ_ALIAS,
343 .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),