1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2023 CR GROUP France
4 * Christophe Leroy <christophe.leroy@csgroup.eu>
11 #include <asm/immap_83xx.h>
13 #include <dm/of_access.h>
18 #define QE_DIR_IN_OUT 3
21 /* The bank's register base in memory */
22 struct gpio_n __iomem *base;
23 /* The address of the registers; used to identify the bank */
27 static inline u32 gpio_mask(uint gpio)
29 return 1U << (31 - (gpio));
32 static inline u32 gpio_mask2(uint gpio)
34 return 1U << (30 - ((gpio & 15) << 1));
37 static int qe_gpio_direction_input(struct udevice *dev, uint gpio)
39 struct qe_gpio_data *data = dev_get_priv(dev);
40 struct gpio_n __iomem *base = data->base;
41 u32 mask2 = gpio_mask2(gpio);
44 clrsetbits_be32(&base->dir1, mask2 * QE_DIR_OUT, mask2 * QE_DIR_IN);
46 clrsetbits_be32(&base->dir2, mask2 * QE_DIR_OUT, mask2 * QE_DIR_IN);
51 static int qe_gpio_set_value(struct udevice *dev, uint gpio, int value)
53 struct qe_gpio_data *data = dev_get_priv(dev);
54 struct gpio_n __iomem *base = data->base;
55 u32 mask = gpio_mask(gpio);
56 u32 mask2 = gpio_mask2(gpio);
59 clrsetbits_be32(&base->dir1, mask2 * QE_DIR_IN, mask2 * QE_DIR_OUT);
61 clrsetbits_be32(&base->dir2, mask2 * QE_DIR_IN, mask2 * QE_DIR_OUT);
64 setbits_be32(&base->pdat, mask);
66 clrbits_be32(&base->pdat, mask);
71 static int qe_gpio_get_value(struct udevice *dev, uint gpio)
73 struct qe_gpio_data *data = dev_get_priv(dev);
74 struct gpio_n __iomem *base = data->base;
75 u32 mask = gpio_mask(gpio);
77 return !!(in_be32(&base->pdat) & mask);
80 static int qe_gpio_get_function(struct udevice *dev, uint gpio)
82 struct qe_gpio_data *data = dev_get_priv(dev);
83 struct gpio_n __iomem *base = data->base;
84 u32 mask2 = gpio_mask2(gpio);
88 dir = in_be32(&base->dir1);
90 dir = in_be32(&base->dir2);
92 if ((dir & (mask2 * QE_DIR_IN_OUT)) == (mask2 & QE_DIR_IN))
94 else if ((dir & (mask2 * QE_DIR_IN_OUT)) == (mask2 & QE_DIR_OUT))
100 static int qe_gpio_of_to_plat(struct udevice *dev)
102 struct qe_gpio_plat *plat = dev_get_plat(dev);
104 plat->addr = dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size);
109 static int qe_gpio_plat_to_priv(struct udevice *dev)
111 struct qe_gpio_data *priv = dev_get_priv(dev);
112 struct qe_gpio_plat *plat = dev_get_plat(dev);
113 unsigned long size = plat->size;
116 size = sizeof(struct gpio_n);
118 priv->addr = plat->addr;
119 priv->base = (void __iomem *)plat->addr;
127 static int qe_gpio_probe(struct udevice *dev)
129 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
130 struct qe_gpio_data *data = dev_get_priv(dev);
133 qe_gpio_plat_to_priv(dev);
135 snprintf(name, sizeof(name), "QE@%.8llx",
136 (unsigned long long)data->addr);
142 uc_priv->bank_name = str;
143 uc_priv->gpio_count = 32;
148 static const struct dm_gpio_ops gpio_qe_ops = {
149 .direction_input = qe_gpio_direction_input,
150 .direction_output = qe_gpio_set_value,
151 .get_value = qe_gpio_get_value,
152 .set_value = qe_gpio_set_value,
153 .get_function = qe_gpio_get_function,
156 static const struct udevice_id qe_gpio_ids[] = {
157 { .compatible = "fsl,mpc8323-qe-pario-bank"},
161 U_BOOT_DRIVER(gpio_qe) = {
165 .of_to_plat = qe_gpio_of_to_plat,
166 .plat_auto = sizeof(struct qe_gpio_plat),
167 .of_match = qe_gpio_ids,
168 .probe = qe_gpio_probe,
169 .priv_auto = sizeof(struct qe_gpio_data),