1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2022 Nuvoton Technology Corp.
11 #define NPCM_GPIOS_PER_BANK 32
13 /* Register offsets */
14 #define GPIO_DIN 0x4 /* RO - Data In */
15 #define GPIO_DOUT 0xC /* RW - Data Out */
16 #define GPIO_OE 0x10 /* RW - Output Enable */
17 #define GPIO_IEM 0x58 /* RW - Input Enable Mask */
18 #define GPIO_OES 0x70 /* WO - Output Enable Register Set */
19 #define GPIO_OEC 0x74 /* WO - Output Enable Register Clear */
21 struct npcm_gpio_priv {
25 static int npcm_gpio_direction_input(struct udevice *dev, unsigned int offset)
27 struct npcm_gpio_priv *priv = dev_get_priv(dev);
29 writel(BIT(offset), priv->base + GPIO_OEC);
30 setbits_le32(priv->base + GPIO_IEM, BIT(offset));
35 static int npcm_gpio_direction_output(struct udevice *dev, unsigned int offset,
38 struct npcm_gpio_priv *priv = dev_get_priv(dev);
40 clrbits_le32(priv->base + GPIO_IEM, BIT(offset));
41 writel(BIT(offset), priv->base + GPIO_OES);
44 setbits_le32(priv->base + GPIO_DOUT, BIT(offset));
46 clrbits_le32(priv->base + GPIO_DOUT, BIT(offset));
51 static int npcm_gpio_get_value(struct udevice *dev, unsigned int offset)
53 struct npcm_gpio_priv *priv = dev_get_priv(dev);
55 if (readl(priv->base + GPIO_IEM) & BIT(offset))
56 return !!(readl(priv->base + GPIO_DIN) & BIT(offset));
58 if (readl(priv->base + GPIO_OE) & BIT(offset))
59 return !!(readl(priv->base + GPIO_DOUT) & BIT(offset));
64 static int npcm_gpio_set_value(struct udevice *dev, unsigned int offset,
67 struct npcm_gpio_priv *priv = dev_get_priv(dev);
70 setbits_le32(priv->base + GPIO_DOUT, BIT(offset));
72 clrbits_le32(priv->base + GPIO_DOUT, BIT(offset));
77 static int npcm_gpio_get_function(struct udevice *dev, unsigned int offset)
79 struct npcm_gpio_priv *priv = dev_get_priv(dev);
81 if (readl(priv->base + GPIO_IEM) & BIT(offset))
84 if (readl(priv->base + GPIO_OE) & BIT(offset))
90 static const struct dm_gpio_ops npcm_gpio_ops = {
91 .direction_input = npcm_gpio_direction_input,
92 .direction_output = npcm_gpio_direction_output,
93 .get_value = npcm_gpio_get_value,
94 .set_value = npcm_gpio_set_value,
95 .get_function = npcm_gpio_get_function,
98 static int npcm_gpio_probe(struct udevice *dev)
100 struct npcm_gpio_priv *priv = dev_get_priv(dev);
101 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
103 priv->base = dev_read_addr_ptr(dev);
104 uc_priv->gpio_count = NPCM_GPIOS_PER_BANK;
105 uc_priv->bank_name = dev->name;
110 static const struct udevice_id npcm_gpio_match[] = {
111 { .compatible = "nuvoton,npcm845-gpio" },
112 { .compatible = "nuvoton,npcm750-gpio" },
116 U_BOOT_DRIVER(npcm_gpio) = {
119 .of_match = npcm_gpio_match,
120 .probe = npcm_gpio_probe,
121 .priv_auto = sizeof(struct npcm_gpio_priv),
122 .ops = &npcm_gpio_ops,