1 // SPDX-License-Identifier: GPL-2.0+
4 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
7 * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
13 #include <asm/arch/imx-regs.h>
16 #include <dt-structs.h>
19 enum mxc_gpio_direction {
20 MXC_GPIO_DIRECTION_IN,
21 MXC_GPIO_DIRECTION_OUT,
24 #define GPIO_PER_BANK 32
26 struct mxc_gpio_plat {
27 #if CONFIG_IS_ENABLED(OF_PLATDATA)
28 /* Put this first since driver model will copy the data here */
29 struct dtd_gpio_mxc dtplat;
32 struct gpio_regs *regs;
35 struct mxc_bank_info {
36 struct gpio_regs *regs;
39 #if !CONFIG_IS_ENABLED(DM_GPIO)
40 #define GPIO_TO_PORT(n) ((n) / 32)
42 /* GPIO port description */
43 static unsigned long gpio_ports[] = {
44 [0] = GPIO1_BASE_ADDR,
45 [1] = GPIO2_BASE_ADDR,
46 [2] = GPIO3_BASE_ADDR,
47 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
48 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
49 defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
50 defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
51 [3] = GPIO4_BASE_ADDR,
53 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
54 defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
55 defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
56 [4] = GPIO5_BASE_ADDR,
57 #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
58 defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT1050))
59 [5] = GPIO6_BASE_ADDR,
62 #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
63 defined(CONFIG_ARCH_IMX8)
64 #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
65 [6] = GPIO7_BASE_ADDR,
68 #if defined(CONFIG_ARCH_IMX8)
69 [7] = GPIO8_BASE_ADDR,
73 static int mxc_gpio_direction(unsigned int gpio,
74 enum mxc_gpio_direction direction)
76 unsigned int port = GPIO_TO_PORT(gpio);
77 struct gpio_regs *regs;
80 if (port >= ARRAY_SIZE(gpio_ports))
85 regs = (struct gpio_regs *)gpio_ports[port];
87 l = readl(®s->gpio_dir);
90 case MXC_GPIO_DIRECTION_OUT:
93 case MXC_GPIO_DIRECTION_IN:
96 writel(l, ®s->gpio_dir);
101 int gpio_set_value(unsigned gpio, int value)
103 unsigned int port = GPIO_TO_PORT(gpio);
104 struct gpio_regs *regs;
107 if (port >= ARRAY_SIZE(gpio_ports))
112 regs = (struct gpio_regs *)gpio_ports[port];
114 l = readl(®s->gpio_dr);
119 writel(l, ®s->gpio_dr);
124 int gpio_get_value(unsigned gpio)
126 unsigned int port = GPIO_TO_PORT(gpio);
127 struct gpio_regs *regs;
130 if (port >= ARRAY_SIZE(gpio_ports))
135 regs = (struct gpio_regs *)gpio_ports[port];
137 val = (readl(®s->gpio_psr) >> gpio) & 0x01;
142 int gpio_request(unsigned gpio, const char *label)
144 unsigned int port = GPIO_TO_PORT(gpio);
145 if (port >= ARRAY_SIZE(gpio_ports))
150 int gpio_free(unsigned gpio)
155 int gpio_direction_input(unsigned gpio)
157 return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
160 int gpio_direction_output(unsigned gpio, int value)
162 int ret = gpio_set_value(gpio, value);
167 return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
171 #if CONFIG_IS_ENABLED(DM_GPIO)
173 static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
177 val = readl(®s->gpio_dir);
179 return val & (1 << offset) ? 1 : 0;
182 static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
183 enum mxc_gpio_direction direction)
187 l = readl(®s->gpio_dir);
190 case MXC_GPIO_DIRECTION_OUT:
193 case MXC_GPIO_DIRECTION_IN:
196 writel(l, ®s->gpio_dir);
199 static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
204 l = readl(®s->gpio_dr);
209 writel(l, ®s->gpio_dr);
212 static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
214 return (readl(®s->gpio_psr) >> offset) & 0x01;
217 /* set GPIO pin 'gpio' as an input */
218 static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
220 struct mxc_bank_info *bank = dev_get_priv(dev);
222 /* Configure GPIO direction as input. */
223 mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
228 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
229 static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
232 struct mxc_bank_info *bank = dev_get_priv(dev);
234 /* Configure GPIO output value. */
235 mxc_gpio_bank_set_value(bank->regs, offset, value);
237 /* Configure GPIO direction as output. */
238 mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
243 /* read GPIO IN value of pin 'gpio' */
244 static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
246 struct mxc_bank_info *bank = dev_get_priv(dev);
248 return mxc_gpio_bank_get_value(bank->regs, offset);
251 /* write GPIO OUT value to pin 'gpio' */
252 static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
255 struct mxc_bank_info *bank = dev_get_priv(dev);
257 mxc_gpio_bank_set_value(bank->regs, offset, value);
262 static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
264 struct mxc_bank_info *bank = dev_get_priv(dev);
266 /* GPIOF_FUNC is not implemented yet */
267 if (mxc_gpio_is_output(bank->regs, offset))
273 static const struct dm_gpio_ops gpio_mxc_ops = {
274 .direction_input = mxc_gpio_direction_input,
275 .direction_output = mxc_gpio_direction_output,
276 .get_value = mxc_gpio_get_value,
277 .set_value = mxc_gpio_set_value,
278 .get_function = mxc_gpio_get_function,
281 static int mxc_gpio_probe(struct udevice *dev)
283 struct mxc_bank_info *bank = dev_get_priv(dev);
284 struct mxc_gpio_plat *plat = dev_get_platdata(dev);
285 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
289 #if CONFIG_IS_ENABLED(OF_PLATDATA)
290 struct dtd_gpio_mxc *dtplat = &plat->dtplat;
292 plat->regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
295 banknum = plat->bank_index;
296 if (IS_ENABLED(CONFIG_ARCH_IMX8))
297 sprintf(name, "GPIO%d_", banknum);
299 sprintf(name, "GPIO%d_", banknum + 1);
303 uc_priv->bank_name = str;
304 uc_priv->gpio_count = GPIO_PER_BANK;
305 bank->regs = plat->regs;
310 static int mxc_gpio_ofdata_to_platdata(struct udevice *dev)
312 struct mxc_gpio_plat *plat = dev_get_platdata(dev);
313 if (!CONFIG_IS_ENABLED(OF_PLATDATA)) {
315 addr = dev_read_addr(dev);
316 if (addr == FDT_ADDR_T_NONE)
319 plat->regs = (struct gpio_regs *)addr;
321 plat->bank_index = dev->req_seq;
326 static int mxc_gpio_bind(struct udevice *dev)
331 static const struct udevice_id mxc_gpio_ids[] = {
332 { .compatible = "fsl,imx35-gpio" },
336 U_BOOT_DRIVER(gpio_mxc) = {
339 .ops = &gpio_mxc_ops,
340 .probe = mxc_gpio_probe,
341 .ofdata_to_platdata = mxc_gpio_ofdata_to_platdata,
342 .plat_auto = sizeof(struct mxc_gpio_plat),
343 .priv_auto = sizeof(struct mxc_bank_info),
344 .of_match = mxc_gpio_ids,
345 .bind = mxc_gpio_bind,
348 U_BOOT_DRIVER_ALIAS(gpio_mxc, fsl_imx6q_gpio)
350 #if !CONFIG_IS_ENABLED(OF_CONTROL)
351 static const struct mxc_gpio_plat mxc_plat[] = {
352 { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
353 { 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
354 { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
355 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
356 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
357 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
358 { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
360 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
361 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
362 { 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
364 { 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
367 #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
368 { 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
370 #if defined(CONFIG_ARCH_IMX8)
371 { 7, (struct gpio_regs *)GPIO8_BASE_ADDR },
375 U_BOOT_DEVICES(mxc_gpios) = {
376 { "gpio_mxc", &mxc_plat[0] },
377 { "gpio_mxc", &mxc_plat[1] },
378 { "gpio_mxc", &mxc_plat[2] },
379 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
380 defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
381 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
382 { "gpio_mxc", &mxc_plat[3] },
384 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
385 defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
386 { "gpio_mxc", &mxc_plat[4] },
388 { "gpio_mxc", &mxc_plat[5] },
391 #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
392 { "gpio_mxc", &mxc_plat[6] },
394 #if defined(CONFIG_ARCH_IMX8)
395 { "gpio_mxc", &mxc_plat[7] },